Showing papers on "Barrier layer published in 1996"

Selective electroless copper deposited interconnect plugs for ULSI applications

Abstract: A method or utilizing electroless copper deposition to selectively form encapsulated copper plugs to connect conductive regions on a semiconductor. A via opening in an inter-level dielectric (ILD) provides a path for connecting two conductive regions separated by the ILD. Once the underlying metal layer is exposed by the via opening, a SiN or SiON dielectric encapsulation layer is formed along the sidewalls of the via. Then, a contact displacement technique is used to form a thin activation layer of copper on a barrier metal, such as TiN, which is present as a covering layer on the underlying metal layer. After the contact displacement of copper on the barrier layer at the bottom of the via, an electroless copper deposition technique is then used to auto-catalytically deposit copper in the via. The electroless copper deposition continues until the via is almost filled, but leaving sufficient room at the top in order to form an upper encapsulation layer. The SiN or SiON sidewalls, the bottom barrier layer and the cap barrier layer function to fully encapsulate the copper plug in the via. The plug is then annealed.

Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications

Abstract: A method of utilizing electroless copper deposition to form interconnects on a semiconductor wafer. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is blanket deposited. Then, a contact displacement technique is used to form a thin activation seed layer of copper on the barrier layer. An electroless deposition technique is then used to auto-catalytically deposit copper on the activated barrier layer. The electroless copper deposition continues until the via/trench is filled. Subsequently, the surface is polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and barrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric barrier layer. The copper interconnect is fully encapsulated from the adjacent material by the TiN (or Ta) and the SiN layers.

Protected encapsulation of catalytic layer for electroless copper interconnect

Abstract: A method for utilizing electroless copper deposition to form interconnects on a semiconductor. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is deposited. Then, a catalytic copper seed layer is conformally blanket deposited in vacuum over the barrier layer. Next, without breaking the vacuum, an aluminum protective layer is deposited onto the catalytic layer to encapsulate and protect the catalytic layer from oxidizing. An electroless deposition technique is then used to auto-catalytically deposit copper on the catalytic layer. The electroless deposition solution dissolves the overlying protective layer to expose the surface of the underlying catalytic layer. The electroless copper deposition occurs on this catalytic surface, and continues until the via/trench is filled. Subsequently, the copper and barrier material are polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and barrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric barrier layer. The copper interconnect is fully encapsulated from the adjacent material by the TiN (or Ta) barrier layer and the overlying SiN layer.

Comparative study of tantalum and tantalum nitrides (Ta2N and TaN) as a diffusion barrier for Cu metallization

Abstract: Tantalum (Ta) and tantalum nitride films (Ta2N and TaN) of about 50 nm thickness were reactively sputter deposited onto (100) Si substrate by using dc magnetron sputtering and their diffusion barrier properties in between Cu and Si were investigated by using sheet resistance measurement, x‐ray diffraction, Auger electron spectroscopy, and Secco etching. With increasing amounts of nitrogen in the sputtering gas, the phases in the as‐deposited film have been identified as a mixture of β‐Ta and bcc‐Ta, bcc‐Ta, amorphous Ta2N, and crystalline fcc‐TaN. Diffusion barrier tests indicate that there are two competing mechanisms for the barrier failure; one is the migration of Cu into the Si substrate and another is the interfacial reaction between the barrier layer and the Si substrate. For instance, we identified that elemental Ta barrier failure occurs initially by the diffusion of Cu into the Si substrate through the barrier layer at 500 °C. On the other hand, the Ta2N barrier fails at 700 °C by the interfacial reaction between Ta2N and Si substrate instead of the migration of Cu into the Si substrate. For the case of TaN, the barrier failure occurs by the migration of Cu into the Si substrate at 750 °C. It is also demonstrated that the diffusion barrier property is enhanced as the nitrogen concentration in the film is increased.

Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC)

Abstract: The present invention provides an anti-reflective Ta3 N5 coating which can be used in a dual damascene structure and for I line or G line lithographies. In addition, the Ta3 N5 coating may also be used as an etch stop and a barrier layer. A dual damascene structure is formed by depositing a first dielectric layer (16). A dielectric tantalum nitride layer (18) is deposited on top of the first dielectric layer. A second dielectric layer (20) is deposited on the tantalum nitride layer. A dual damascene opening (34) is etched into the dielectric layers by patterning a first opening portion (26) and a second opening portion (32) using photolithography operations. Dielectric tantalum nitride layer (18) serves as an ARC layer during these operations to reduce the amount of reflectance from conductive region (14) to reduce distortion of the photoresist pattern. The use of a dielectric tantalum nitride layer as an ARC is particularly suitable for I line and G line lithography.

Barrier membranes including a barrier layer employing polyester polyols

Abstract: The present invention relates to barrier membranes including a barrier layer which includes one or more thermoplastic urethane formed from polyester polyols. More particularly, the membranes include a barrier layer including blends of one or more polyester polyol based thermoplastic urethanes and one or more copolymers of ethylene and vinyl alcohol. The barrier membranes can be employed in a variety of applications and can be used as either monolayers or multi-layered laminates.

Barrier layer for ferroelectric capacitor integrated on silicon

Abstract: A ferroelectric cell in which a ferroelectric stack (44) of a perovskite ferroelectric sandwiched by cubic perovskite metal-oxide conductive electrodes (50, 56) are formed over a silicon body, such as a polysilicon plug (42) penetrating a field oxide (40) over a silicon transistor (34). According to the invention, an oxidation barrier (46) is placed between the lower metal-oxide electrode and the polysilicon. The oxidation barrier may be: a refractory metal sandwiched between two platinum layers which forms a refractory oxide in a platinum matrix; an intermetallic barrier beneath a platinum electrode, e.g., of NiAl; or a combination of Ru and SrRuO3 or similar materials. Thereby, the polysilicon plug is protected from oxidation.

Filling narrow apertures and forming interconnects with a metal utilizing a crystallographically oriented liner layer

Abstract: An aluminum sputtering process, particularly useful for filling vias and contacts of high aspect ratios formed through a dielectric layer and also usefull for forming interconnects that are highly resistant to electromigration A liner or barrier layer is first deposited by a high-density plasma (HDP) physical vapor deposition (PVD, also called sputtering) process, such as is done with an inductively coupled plasma If a contact is connected at its bottom to a silicon element, the first sublayer of the liner layer is a Ti layer, which is silicided to the silicon substrate The second sublayer comprises TiN, which not only acts as a barrier against the migration of undesirable components into the underlying silicon but also when deposited with an HDP process and biased wafer forms a dense, smooth crystal structure The third sublayer comprises Ti and preferably is graded from TiN to Ti Over the liner layer, an aluminum layer is deposited in a standard, non-HDP process The liner layer allows the hottest part of the aluminum deposition to be performed at a relatively low temperature between 320 and 500° C, preferably between 350 and 420° C, while still filling narrow plug holes, and the TiN does not need to be annealed to form an effective barrier against diffusion into the silicon A horizontal interconnect formed by the inventive process is resistant to electromigration

Solder bump fabrication methods and structure including a titanium barrier layer

Abstract: A method for fabricating solder bumps on a microelectronic device having contact pads includes the steps of depositing a titanium barrier layer on the device, forming an under bump metallurgy layer on the titanium barrier layer, and forming one or more solder bumps on the under bump metallurgy layer. The solder bump or bumps define exposed portions of the under bump metallurgy layer which are removed, and then the exposed portion of the titanium barrier layer is removed. The titanium barrier layer protects the underlying microelectronic device from the etchants used to remove the under bump metallurgy layer. The titanium layer also prevents the under bump metallurgy layer from forming a residue on the underlying microelectronic device. Accordingly, the titanium barrier layer allows the under bump metallurgy layer to be quickly removed without leaving residual matter thereby reducing the possibility of electrical shorts between solder bumps.

Silicon carbide metal diffusion barrier layer

Abstract: Disclosed is the use of silicon carbide as a barrier layer to prevent the diffusion of metal atoms between adjacent conductors separated by a dielectric material. This advancement allows for the use of low resistivity metals and low dielectric constant dielectric layers in integrated circuits and wiring boards.

Fluorine barrier layer between conductor and insulator for degradation prevention

Abstract: Method of improving the resistance of a metal against degradation from exposure to fluorine released from a fluorine-containing material by forming a fluorine-barrier layer between the insulator material and the metal. The invention is especially useful in improving corrosion and poisoning resistance of metallurgy, such as aluminum metallurgy, in semiconductor structures. The invention also covers integrated circuit structures made by this method.

Trenched field effect transistor with PN depletion barrier

Abstract: A trenched MOSFET in its on-state conducts current through an accumulation region and through an inverted depletion barrier layer located along the trench sidewalls. Blocking is achieved by gate control depletion of the adjacent region and by the depletion barrier layer (having the appearance of "ears" in a cross sectional view and being of opposite doping type to the adjacent region) which extends laterally from the trench sidewalls into the drift region. This MOSFET has superior on-state specific resistance to that of prior art trenched MOSFETs and also has good performance in terms of on state resistance, while having superior blocking characteristics to those of prior art trenched MOSFETs. The improvement in the blocking characteristic is provided by the depletion barrier layer which is a semiconductor doped region. In the blocking state, the depletion barrier layer is fully or almost fully depleted to prevent parasitic bipolar conduction. The shape and extent of the depletion barrier layer may be varied and more than one depletion barrier layer may be present.

Flip-Chip interconnections using lead-free solders

Abstract: An interconnection structure suitable for the connection of microelectronic circuit chips to packages is provided by this invention. In particular, the invention pertains to the area-array or flip-chip technology often called C4 (controlled collapse chip connection). The structure comprises an adhesion/barrier layer deposited on a passivated substrate (e.g., a silicon wafer), optionally an additional adhesion layer, a solderable layer of a metal selected from the group consisting of Ni, Co, Fe, NiFe, NiCo, CoFe and NiCoFe on the adhesion/barrier layer, and a lead-free solder ball comprising tin as the predominate component and one or more alloying elements selected from Bi, Ag, and Sb, and further optionally including one or more elements selected from the group consisting of Zn, In, Ni, Co and Cu.

Low dielectric constant silicon dioxide sandwich layer

Abstract: An improved sandwich layer of silicon dioxide layers for gap filling between metal lines. This is accomplished using a first layer formed in a PECVD process using TEOS and a fluorine-containing compound to give a barrier layer with a dielectric constant of less than 4.0, preferably approximately 3.5. Subsequently, an SACVD process is used with TEOS to form a gap filling layer. By appropriately choosing the thickness of the respective layers, one can adjust the dielectric to a value which is a combination of the dielectric constants of the two different layers, preferably giving a dielectric constant of approximately 3.6-3.7.

A thin film metal barrier for electrical interconnections

Abstract: An interconnect structure and barrier layer for electrical interconnections is described incorporating a layer of TaN in the hexagonal phase between a first material such as Cu and a second material such as Al, W, and PbSn. A multilayer of TaN in the hexagonal phase and Ta in the alpha phase is also described as a barrier layer. The invention overcomes the problem of Cu diffusion into materials desired to be isolated during temperature anneal at 500° C.

Tin coated electrical connector

Abstract: An electrical conductor (10) has a copper base substrate (12) coated with a tin base coating layer (14). To inhibit the diffusion of copper from the substrate (12) into the coating layer (14) and the consequential formation of a brittle tin/copper intermetallic, a barrier layer (16) is interposed between the substrate (12) and the coating layer (14). This barrier layer (16) contains from 20 % to 40 %, by weight, of nickel and is preferably predominantly comprised of copper. In one embodiment, an intermetallic layer (38) selected from the group (Cu-Ni)3Sn, (Cu-Ni)6Sn5, Cu3Sn, Cu6Sn5 is disposed between the barrier layer (16) and the tin base coating layer (14).

Method of manufacturing copper interconnect with top barrier layer

Abstract: A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer ,while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.

An electrical interconnect for a planar fuel cell

Abstract: An electrical interconnect device for a planar fuel cell having solid oxide electrolyte, a cathode and a nickel-containing anode comprises a plate-like chromium-containing substrate having fuel gas-flow channels on one side and an oxidation-resistant coating on surfaces of the one side adapted to contact the anode. The coating comprises an outer oxygen barrier layer for electrically contacting the anode comprising Ni, a noble metal except Ag or an alloy of one or more of these metals and an electrically conductive metal barrier layer comprising Nb, Ta, Ag or alloys of one or more of these metals between the substrate and the outer layer.

Structure of Anodic Films Formed on Magnesium

Abstract: The cylindrical pore structure and barrier layer of anodic films formed on magnesium which are similar to the Keller`s model of anodic alumina are determined by direct cross-sectional observation. The ratios of cell diameter and barrier layer thickness to the forming voltage are notably smaller than those associated with anodic alumina. It is assumed that anodic film growth proceeds mainly by the formation of MgF{sub 2} and Mg{sub x+y/2}O{sub x}(OH){sub y} (magnesium oxyhydroxide) at the metal/film interface and the dissolution of the film at pore bases.

Semi-selective chemical vapor deposition

Abstract: The present invention is an apparatus and method for semi-selectively depositing a material on a substrate by chemical vapor deposition to form continuous, void-free contact holes or vias in sub-half micron applications. An insulating layer is preferentially deposited on the field of a substrate to delay or inhibit nucleation of metal on the field. A CVD metal is then deposited onto the substrate and grows selectively in the contact hole or via where a barrier layer serves as a nucleation layer. The process is preferably carried out in a multi-chamber system that includes both PVD and CVD processing chambers so that once the substrate is introduced into a vacuum environment, the filling of contact holes and vias occurs without the formation of an oxide layer on a patterned substrate.

Step coverage enhancement process for sub half micron contact/via

Abstract: A Process for creating a planar topography and enhanced step coverage for the fabrication of contact/via holes in sub-half-micron diameter range with high height vs. dimension aspect ratio. This is accomplished by interrupting the deposition of the barrier layer in the contact/via lining with a programmed reactive ion etching process, which will protect the thin barrier lining in the bottom part of the contact hole, but will etch off and planarize the excessively thick barrier layer near the opening of the hole. The resulting barrier layers show a disrupt columnar film structure which provides better barrier during subsequent metal fill deposition process.

Heterostructure field effect device having refractory ohmic contact directly on channel layer and method of making

Abstract: A complementary III-V heterostructure field effect device includes the same refractory ohmic material for providing the contacts (117, 119), to both the N-type and P-type devices. Furthermore, the refractory ohmic contacts (117, 119) directly contact the InGaAs channel layer (16) to provide improved ohmic contact, despite the fact that the structure incorporates an advantageous high aluminum composition barrier layer (18) and an advantageous GaAs cap layer (20).

Method of forming a capacitor plate and a capacitor incorporating same

Abstract: A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing an electrically conductive first layer over the node; c) providing an electrically insulative barrier second layer over the first conductive layer; d) providing a third layer over the electrically insulative barrier layer, the third layer comprising a material which is either electrically conductive and resistant to oxidation, or forms an electrically conductive material upon oxidation; e) providing an insulating inorganic metal oxide dielectric layer over the electrically conductive third layer; f) providing an electrically conductive fourth layer over the insulating inorganic metal oxide dielectric layer; and g) providing an electrically conductive interconnect to extend over the second insulative layer and electrically interconnect the first and third conductive layers. A capacitor construction having such a dielectric layer in combination with the barrier layer and electrical interconnect of a first capacitor plate is disclosed.

Heterostructure thermionic coolers

Abstract: A heterostructure thermionic cooler and a method for making thermionic coolers, employing a barrier layer of varying conduction bandedge for n-type material, or varying valence bandedge for p-type material, that is placed between two layers of material. The barrier layer has a high enough barrier for the cold side to only allow “hot” electrons, or electrons of high enough energy, across the barrier. The barrier layer is constructed to have an internal electric field such that the electrons that make it over the initial barrier are assisted in travel to the anode. Once electrons drop to the energy level of the anode, they lose energy to the lattice, thus heating the lattice at the anode. The barrier height of the barrier layer is high enough to prevent the electrons from traveling in the reverse direction.

Multilayer, halide free, retortable barrier film

Abstract: A multiple layer structure comprising a skin layer, a barrier layer, a radio frequency susceptible layer having a first polyolefin in an amount within a range of 30-60 % by weight, a second polyolefin in an amount within the range of 25-50 % by weight, a radio frequency susceptible polymer in an amount within the range of 3-40 % by weight, a styrene and hydrocarbon block copolymer in an amount within the range of 5-40 % by weight of the sealant layer.

Method for producing dual work function CMOS device

Abstract: A dual work function CMOS device and method for producing the same is disclosed. The method includes: depositing a first layer of a doped material, either n-type or p-type, over a substrate to be doped; defining the areas that are to be oppositely doped; depositing a second layer of an oppositely doped material over the entire surface; and subjecting the entire CMOS device to a high temperature, drive-in anneal. The drive-in anneal accelerates the diffusion of the dopants into the adjacent areas, thereby doping the gate polysilicon and channels with the desired dopants. A nitride barrier layer may be utilized to prevent the second dopant from diffusing through the first layer and into the substrate beneath.

Footwear insole with a moisture absorbent inner layer

Abstract: An insole for an article of footwear which includes an apertured top layer formed of a non-absorbent, thermally non-conductive thermoplastic material, a non-woven layer having a first portion formed of a mixture of moisture-wicking and moisture-absorbent fibers affixed to the top layer, and, optionally, a second portion including fibers which are non-adsorbent and non-absorbent, and, in various embodiments, a barrier layer and/or cushioning layer(s) forming a laminate in which the non-woven layer is sandwiched between the top layer and such other layers. The chemical formulation of the top layer of thermoplastic material can be varied to alter its coefficient of friction or degree of slip resistance of the insole depending upon the requirements of a particular application.

Deposition of a conductor in a via hole or trench

Abstract: The present semiconductor device and method of fabrication thereof includes the provision of a trench or hole in a dielectric (44) with a barrier layer (52) thereon extending into the trench or via hole A layer of titanium (54) is provided over the barrier layer, also extending into the trench or via hole, and aluminum or aluminum alloy (56) is provided over the titanium layer The barrier layer provides good conformal coverage while also preventing outgassing of the dielectric from adversely affecting the conductor The barrier layer also serves as a wetting agent for the deposition and flowing of aluminum or aluminum alloy The titanium layer can be extremely thin, or non-existent, so as to avoid significant growth of TiAl3 and the problems attendant thereto

Fluorescent lamp having ultraviolet reflecting layer

Abstract: A fluorescent lamp with an ultraviolet reflecting barrier layer between the glass envelope and the phosphor layer(s). The barrier layer is a blend of gamma alumina, alpha alumina and theta alumina, such as 5–80 weight percent gamma alumina, 5–80 weight percent alpha alumina, and 5–80 weight percent theta alumina.

Type II quantum well laser with enhanced optical matrix

Abstract: A type II multiple quantum well, 4 constituent active region, optically clad electrically pumped and optically pumped laser for emitting at a wavelength greater than or equal to about 2.5 microns is disclosed. The active region comprises one or more periods, each period further comprising a barrier layer, a first conduction band layer, a valence band layer and a second conduction band layer.