Showing papers on "Barrier layer published in 1997"

Plated copper interconnect structure

Abstract: A high conductivity interconnect structure is formed by electroplating or electroless plating of Cu or a Cu-base alloy on a seed layer comprising an alloy of a catalytically active metal, such as Cu, and a refractory metal, such as Ta. The seed layer also functions as a barrier/adhesion layer for the subsequently plated Cu or Cu-base alloy. Another embodiment comprises initially depositing a refractory metal barrier layer before depositing the seed layer.

Chemical mechanical polishing (CMP) slurry for polishing copper interconnects which use tantalum-based barrier layers

Abstract: A method for forming a copper interconnect on an integrated circuit (IC) begins by forming a dielectric layer (20) having an opening. A tantalum-based barrier layer (21), such as TaN or TaSiN, is formed within the opening in the layer (20). A copper layer (22) is formed over the barrier layer (21). A first CMP process is used to polish the copper (22) to expose portions of the barrier (21). A second CMP process which is different from the first CMP process is then used to polish exposed portions of the layer (21) faster than the dielectric layer (20) or the copper layer (22). After this two-step CMP process, a copper interconnect having a tantalum-based barrier is formed across the integrated circuit substrate (12).

Variability of surface layer hydrography in the tropical Pacific Ocean

Abstract: The purpose of this study is to examine the variation of ocean surface layer hydrography on interannual timescales in the tropical Pacific Ocean using conductivity-temperature-depth measurements from 1976 to 1994. We demonstrate that associated with interannual variations in atmospheric forcing, there were distinct changes in mixed layer temperature, salinity, depth, and barrier layer thickness between normal, El Nino, and La Nina time periods. During El Nino a warm, fresh mixed layer accompanied by an underlying barrier layer develops in the central and eastern Pacific in association with increased precipitation and reduced trade wind forcing. Conversely, during La Nina, when unusually cold conditions prevail in the central and eastern equatorial Pacific and the warm pool is confined to the far western Pacific, a thick barrier layer is found west of 160°E. Statistically, we demonstrate that barrier layers occur with increasing frequency as mixed layer temperatures increase from 20°C to 30°C, suggesting that barrier layer thickness may be one of the factors affecting surface temperatures. The physical mechanism underlying this relationship is likely to be related to the reduced efficiency of vertical turbulent mixing in cooling the surface via entrainment of thermocline water when the barrier layer is thick. Changes in mixed layer temperature, on the other hand, can affect precipitation and therefore mixed-layer salinity, leading to the possibility of feedbacks on interannual timescales involving the mixed-layer temperature balance and the hydrologic cycle over the ocean. The extent to which such feedbacks, if operative, may influence the detailed evolution of large-scale, lower-frequency variability in the tropical Pacific needs to be critically assessed in the context of coupled ocean-atmosphere models.

Low-temperature intermediate Au-Si wafer bonding; eutectic or silicide bond

Abstract: The actual mechanism involved in Au-Si wafer bonding is controversial. Usually a titanium or chromium layer is deposited in between the (oxidized) silicon substrate and the gold layer to ensure adhesion. The resulting bond of two such wafers after annealing is generally considered to be eutectic, however, the bond temperature required is higher than would be expected from the Au-Si eutectic temperature. Moreover, silicide grains are formed at the bonding interface. In this paper it is proposed that the actual bonding is initiated by the dissolution of the oxide layer by silicidation of the titanium adhesion/barrier layer. The subsequent direct Au-Si contact enables the formation of the euteetic phase. The silicidation is required to obtain the eutectic alloy with 19 at.% Si despite the Ti diffusion barrier. The bonding temperature required is, therefore, set by the silicidation process rather than by the eutectic phase. Several experiments have been designed to support this theory. AI-Si eutectic bonding has been investigated, as it is not complicated by an adhesion metal and experiments demonstrate reliable bonding close to its eutectic temperature. Moreover, a Ti/Au/Si/Au stack has been fabricated to be used as a eutectic solder, giving bonding at a temperature not affected by silicidation. Keywords Eutectic bonding Gold Silicide bonding Silicon Wafer bonding

Glazing comprising a substrate furnished with a multiplicity of thin layers providing thermal insulation and/or solar protection

Abstract: A glazing has a transparent substrate (1) with a thin film stack comprising an alternating sequence of 'n' (especially metallic) functional layers (3, 6) with IR and/or solar radiation reflective properties and 'n+1' coatings consisting of one or more layers (2a, 2b, 5a, 5b, 8a, 8b), of which at least one is of dielectric material. The novelty is that the optical quality of the stack is preserved, when the substrate is subjected to quenching, bending and annealing heat treatment, by provision of (a) an oxygen and water barrier layer below at least one of the functional layers (3, 6), especially the 'nth' layer; and (b) an absorbent layer, which is capable of absorbing the functional layer material, or a stabilising layer which stabilises the material of either the coating located above the functional layer (3, 6) and below the barrier layer or the coating located below the functional layer (3, 6). The glazing may be laminated glazing, with two or more glass substrates and one or more interposed thermoplastic foils, or 'asymmetric' laminated glazing with a glass substrate having its thin film stack covered by a polyurethane-based energy absorbing polymer foil. Also claimed is a production process for the above glazing, in which the thin film stack is applied to the glass substrate by (optionally magnetic field assisted) cathodic sputtering and then the glazing is subjected to quenching, bending and annealing heat treatment, without degradation of its optical quality.

Transparent high barrier multilayer structure

Abstract: A transparent multilayer structure (20, 21, 31, 31') is disclosed which may be used as a flexible self-supporting container (30) for a flowable food product such as fruit juice, cheese, milk, tomato juice, soup and the like The transparent multilayer structure (20, 21, 31) possesses superior barrier properties to oxygen, water vapor and aromatic gases The multilayer structure (20, 21, 31) may include an exterior layer (22, 22') having a metal oxide deposition (24, 24') laminated to an interior layer (28, 28') through use of an adhesive (26) In one embodiment, the metal oxide (24, 24') is SiOx where x has a value between 15 and 22 thereby allowing for a transparent multilayer structure (20, 21, 31) The metal oxide (24, 24') may be deposited on the exterior layer (22, 22') through a number of various methods An exemplary method is plasma-enhanced chemical vapor deposition The exterior layer (22, 22') may be biaxially oriented PET and an interior layer (28, 28') may be a blend of LLDPE and LDPE A barrier layer (27, 27') and a polyolefin layer (29, 29') may also be included in the transparent multilayer structure (20, 21, 31) The barrier layer (27, 27') may be EVOH, PEN, liquid crystal polymers or the like

Electroless gold plating method for forming inductor structures

Abstract: The present invention provides a method of manufacturing an inductor element 46 using an electroless Au plating solution. The invention has three embodiments for forming the inductor. In the first embodiment, a first insulating layer 30 is formed over a semiconductor structure 10 20. An adhesion layer 34 composed of polysilicon is formed over the first insulating layer 30. A first barrier layer 36 comprised of Ni is selectively formed using an Ni electroless plating process over the adhesion layer 34. In an important step, a gold layer 40 is electroless plated over the first barrier layer 36 using an Au electroless plating process. A second barrier layer 44 is formed over the gold layer 40 using an electroless Ni deposition technique. A planarization layer is formed over the second barrier layer. A novel core metal layer composed of a Fe--Co alloy is electroless plated over the planarization layer. The second and third embodiments vary in the process of defining the gold electroless inductor by forming the inductor in a trench. The gold electroless inductor 46 can withstand high current densities without suffering from electromigration effects and is highly corrosion resistant.

Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric

Abstract: A composite gate electrode layer incorporates a diffusion-retarding barrier layer disposed at the bottom of the gate electrode layer to reduce the amount of dopant which diffuses into the gate dielectric layer from the gate electrode layer. A lower nitrogen-containing gate electrode layer provides a diffusion-retarding barrier layer against dopant diffusion into the gate dielectric layer disposed therebelow, and an upper gate electrode layer is formed upon the lower layer and is doped to form a highly conductive layer. Together the first and second gate electrode layers form a composite gate electrode layer which incorporates a diffusion-retarding barrier layer adjacent to the underlying gate dielectric layer. The barrier layer may be formed by annealing a first polysilicon layer in a nitrogen-containing ambient, such as N 2 , NO, N 2 O, and NH 3 , by implanting a nitrogen-containing material, such as elemental or molecular nitrogen, into a first polysilicon layer, and by in-situ depositing a nitrogen-doped first polysilicon layer. Diffusion of dopants into the gate dielectric layer may be retarded, as most dopant atoms are prevented from diffusing from the composite gate electrode layer at all. In addition, the nitrogen concentration within the gate dielectric layer, particularly at or near the substrate interface, may be maintained at lower concentrations than otherwise necessary to prevent dopant diffusion into the underlying substrate. The present invention is particularly well suited to thin gate dielectrics, such as a those having a thickness less than approximately 60 Å when using a p-type dopant, such as boron.

Bipolar electrode-electrolyte unit

Abstract: A bipolar electrode-electrolyte unit for an electrochemical cell includes a barrier layer, at least two carrier layers and at least two active layers, and an electrolyte. The active layers comprise an electroactive material with low resistance and high capacitance. The barrier layer is electrically conducting, is impermeable to matter, and is made of compressed carbon, impregnated carbon, compressed and impregnated carbon, plastic-bonded carbon or carbon-coated sheet metal. The carrier layers, each located between a barrier layer and an active layer, form an electrically conducting porous three-dimensional structure with a large specific surface that contains a material selected from the group consenting of carbon fiber papers, carbon fiber films, carbon fiber mats, carbon fiber fabrics, compressed graphite flakes and carbon fibers, conducting plastic, and carbon produced by pyrolysis or dehydration of organic materials.

Multilayered wound dressing

Abstract: A multilayered dressing comprising a fibrous absorbent layer for absorbing wound exudate, a barrier layer and an odour adsorbing layer where said barrier layer is located between the absorbent layer and the odour adsorbing layer.

High temperature superconductivity in strained Si/SiGe

Abstract: A structure based on strained Si/SiGe that has high temperature superconductivity is disclosed. The structure for carrying superconducting current includes a substrate (12); a first epitaxial P type semiconductor layer (14), which is under compressive strain, for transporting holes; a second epitaxial barrier layer (20) positioned on the first layer (14); and a third epitaxial N type semiconductor layer (24), which is under tensile strain, for transporting electrons. The barrier layer (30) is thick enough to restrict recombination of electrons and holes, yet the barrier layer (30) is thin enough to permit coulomb force attraction between the electrons and holes to form electron-hole pairs. The first and second layers (14,20) include SiGe, such as Si 1.x Ge x , where x is 0.6-0.8 for the first layer (14), and 0.3-0.4 for the second layer (20). The third layer (24) includes Si.

Silicon IC contacts using composite TiN barrier layer

Abstract: The specification describes a composite TiN barrier layer structure formed by depositing a first TiN layer by CVD to obtain good step coverage, followed by a second TiN layer formed by PVD to obtain uniform surface morphology for subsequent deposition of an aluminum alloy contact layer. Alternatively, uniform TiN layer morphology is obtained by depositing multiple CVD TiN layers as a series of thin strata, and passivating after each deposition step to fully crystallize each stratum thereby obtaining a uniformly crystallized barrier layer.

La0.5Sr0.5CoO3/Pb(Nb0.04Zr0.28Ti0.68)O3/La0.5Sr0.5CoO3 thin film heterostructures on Si using TiN/Pt conducting barrier

Abstract: A high density ferroelectric memory process flow requires the integration of conducting barrier layers to connect the drain of the pass-gate transistor to the bottom electrode of the ferroelectric stack. We are studying the effect of crystallinity of the TiN/Pt barrier layer with Si wafers on the ferroelectric properties of La0.5Sr0.5CoO3/Pb(Nb0.04Zr0.28Ti0.68)O3/La0.5Sr0.5CoO3 (LSCO/PNZT/LSCO) capacitors. Structural studies indicate complete phase purity (i.e., fully perovskite) in both epitaxial and polycrystalline materials. The polycrystalline capacitors show lower remnant polarization and coercive voltages. However, the retention, fatigue, and imprint characteristics are similar, indicating minimal influence of crystalline quality on the ferroelectric properties.

Preparation and Characterization of Iridium Oxide Thin Films Grown by DC Reactive Sputtering

Abstract: Iridium oxide ( IrO2) thin films were successfully grown by a DC magnetron reactive sputtering method. It was found that the crystalline nature and morphology of IrO2 films were strongly dependent on the oxygen partial pressure, total pressure and growth temperature. The growth of IrO2 is well explained by the generic curve for the total pressure as a function of O2 content. The films showed good barrier performance between Pt and poly-Si up to 750° C. A 40-nm-thick Ba0.5Sr0.5TiO3 film was grown by RF magnetron sputtering on the Pt/IrO2/poly-Si electrode. The leakage current density and dielectric constant of a Pt/Ba0.5Sr0.5TiO3/Pt capacitor on the IrO2/poly-Si electrode were comparable to those of the capacitor on a SiO2/Si substrate. However, an additional ohmic layer was required to prevent the formation of a SiO2 layer between the IrO2 and poly-Si.

Formation and Dissolution of the Passive Film on Iron Studied by a Light Reflectance Technique

Abstract: The formation, growth, and dissolution of the passive film on iron in neutral and alkaline solutions was investigated using a light reflectance technique. In this study, laser light of 325 nm was used to access the amount of light absorbed in the film and to evaluate the optical absorption coefficient. After calibration, this technique allows a fast, in situ determination of the film thickness. Cyclic voltammetry and potential-step experiments with simultaneous thickness monitoring were carried out in borate buffer and in 0.1 M NaOH. For the borate buffer, anodic film formation and cathodic film dissolution are reversible, i.e., repeated anodic/cathodic cycling leads to conditions identical to the initial state. In NaOH, cathodic reduction of the film does not lead to film dissolution but to the formation of an electrochemically active layer, which does not significant contribute to the potential drop in the metal/film/electrolyte system. Hence, repeated passivation and reduction leads to successive thickening of the film, consisting of a barrier layer of constant thickness and a porous layer having increased thickness with every passivation/reduction cycle. This layer does not contribute to the passivity of iron.

Oxygen scavenging system including a by-product neutralizing material

Abstract: Provided is a system useful for oxygen scavenging which comprises at least two components, i.e., an oxygen scavenging material which forms at least one by-product upon reaction thereof with oxygen, and an effective amount of a neutralizing material capable of neutralizing at least a portion of theses by-products. In a preferred application, a multi-layer structure that can be employed in producing packages and in particular food packages, comprises a first layer including an oxygen scavenging material and a second layer which includes a material that is capable of neutralizing at least a portion of the by-products produced by the oxidation of the oxygen scavenging material within the first layer. These two layers are arranged such that, upon formation of the package, the second layer is interior to the first layer. Furthermore, the multi-layer film can include one or more of an oxygen barrier layer, a polymeric selective barrier layer, and a heat-sealable layer.

Local interconnect comprising titanium nitride barrier layer

Abstract: A method of forming a local interconnect structure is provided. A first barrier layer comprising sputtered titanium nitride is formed over a topographical structure situated upon a field oxide region within a semiconductor substrate. A hard mask layer comprising tungsten silicide is formed over the first barrier layer. A photoresist layer is then formed over the hard mask layer. The hard mask layer is selectively removed from above an adjacent gate stack on the semiconductor substrate using an etch that is selective to the first barrier layer. The first barrier layer is selectively removed using an etch that is selective to the hard mask layer. A silica layer is formed over the hard mask layer. A recess is formed in the silica layer that is aligned with an active area within the semiconductor substrate. The recess is filled with an electrically conductive material. A second method of forming a local interconnect structure is provided comprising forming a first barrier layer comprising sputter titanium nitride over a semiconductor substrate having a topographical structure situated upon a field oxide region within the semiconductor substrate. A first electrically conductive layer comprising tungsten is then formed over the first barrier layer using chemical vapor deposition. The first electrically conductive layer provides good step coverage over the topographical structure. A second barrier layer comprising sputtered titanium nitride is formed over the first electrically conductive layer. A hard mask layer comprising polysilicon or silica is then formed over the second barrier layer. The hard mask is selectively removed from above an adjacent gate stack on the semiconductor substrate with an etch that is selective to the second barrier layer. The second barrier layer, the first conductive layer, and the first barrier layer are selectively removed, thereby exposing the underlying gate stack on the semiconductor substrate using a chemical etch selective to the hard mask layer. A silica layer is then formed with a recess therein that is filled with an electrically conductive material to form an active area contact through the local interconnect structure.

Barrier Properties for Oxygen Diffusion in a TaSiN Layer

Abstract: Annealing in O2 at temperatures above 650° C is required for a thin ferroelectric capacitor. Reduction of the leakage current and an increase of capacitance can be attained in the charge storage capacitor through this annealing. A stacked structure capacitor cell must be practically employed in metal oxide semiconductor large scale integrated circuits (MOSLSI). In this capacitor cell with a conventional Pt/TiN/poly-Si lower electrode, however, O2 annealing can not be attained at high temperature because peeling of the TiN barrier layer and the formation of a thin oxide layer at the surface of poly-Si occur. An noncrystalline TaSiN layer has been studied with respect to the barrier effect for oxygen diffusion used in the barrier layer of the lower electrode. The penetration depth of oxygen diffusion decreases markedly with increasing Si composition in a TaSiN layer and reaches 20 nm deep in a Ta.22Si.35N.43 layer. However, the resistivity increases with this increase. A good diffusion barrier layer with low sheet resistance is attained in a Ta.50Si.16N.34 layer. Penetration depth below 40 nm is obtained in a slightly Si-rich Ta.36Si.27N.37 layer for O2 annealing at 850° C.

Diffusion barrier for polysilicon gate electrode of MOS device in integrated circuit structure, and method of making same

Abstract: A uniformly doped polysilicon gate electrode of an MOS device forming a part of an integrated circuit structure on a semiconductor substrate is formed by first depositing a very thin layer of amorphous or polycrystalline silicon, e.g., from about 2 nm to about 10 nm, over a gate oxide layer. The thin layer of silicon layer is then exposed to a nitrogen plasma formed from N2 at a power level sufficient to break the silicon--silicon bonds in the thin layer of silicon, but insufficient to cause sputtering of the silicon to cause a barrier layer of silicon and nitrogen to form at the surface of the thin silicon layer. Further silicon, e.g., polysilicon, is then deposited over the barrier layer to the desired thickness of the polysilicon gate electrode. The gate electrode is then conventionally doped, i.e., by implantation followed by furnace annealing, to diffuse and activate the dopant in the polysilicon gate electrode without, however, resulting in penetration of the dopant through the barrier layer into the underlying gate oxide layer or the semiconductor substrate.

Modelling the formation and growth of anodic passive films on metals in concentrated acid solutions

Abstract: Two model approaches to the formation of passive films as adsorbed layers during the active anodic dissolution of a metal in acid and their subsequent growth are presented. The first depicts passivation as proceeding in parallel to active dissolution. Adsorption of water on active surface sites leads to passivation, whereas adsorption of acid leads to active dissolution of the metal. The model is consistent with the impedance response during passivation of Fe and an Fe-20%Mo alloy in concentrated H3PO4. The second model is an updated version of the so-called surface charge approach to the mechanism of conduction of anodic passive films. It is based on the assumptions that oxygen vacancies are the main ionic charge carriers and the field strength in the barrier layer is constant. A negative surface charge built up at the film/solution interface via accumulation of metal vacancies accelerates oxygen vacancy transport, thus explaining the pseudoinductive behaviour of the metal/film/electrolyte system under small amplitude a.c. perturbation. The model describes the growth of thin anodic films on Fe, Mo and an Fe-20%Mo alloy in concentrated H3PO4.

Organic light-emitting device and method of fabricating the same

Abstract: An organic light-emitting device, comprising: a substrate; a first conductive layer formed over the substrate; at least one layer of a light-emissive organic material formed over the first conductive layer; a barrier layer formed over the at least one organic layer which acts to protect the at least one layer of organic material; and a second conductive layer, preferably a patterned sputtered layer, formed over the barrier layer.

Method for forming a conductive structure having a composite or amorphous barrier layer

Abstract: A A method for forming an improved copper barrier layer begins by providing a silicon-containing layer (10). A physical vapor deposition process is then used to form a thin tantalum nitride amorphous layer (12). A thin amorphous titanium nitride layer (14) is then deposited over the amorphous tantalum nitride layer. A collective thickness of the tantalum nitride and titanium nitride layers 12 and 14 is roughly 400 angstroms or less. A copper material 16 is then deposited on top of the amorphous titanium nitride wherein the composite tantalum nitride layer 12 and titanium nitride layer 14 effectively prevents copper from diffusion from the layer 16 to the layer 10.

Thick plated interconnect and associated auxillary interconnect

Abstract: A thick plated interconnect (80) comprising a copper lead (50) and a bonding cap (84) coupled to the copper lead (50). The bonding cap (84) may include a bondable member (86) formed from a bondable layer (62) comprising aluminum. A barrier member (88) may be formed from a barrier layer (60). The barrier member (88) may be disposed between the bondable member (86) and the copper lead (50).

Method of making a barrier layer to protect programmable antifuse structure from damage during fabrication sequence

Abstract: A method for forming an antifuse interconnect structure, for a one-time fusible link, to be used with field-programmable gate arrays, has been developed. The process features the use of an amorphous silicon layer, used as the antifuse layer, with the amorphous silicon layer protected by a thin barrier layer, during the patterning procedure. The protected antifuse layer results in a reproducible thickness, and thus reproducible pulsing voltages, needed for rupturing of the antifuse layer. Planarization of an underlying metal plug, via an insulator refill procedure, offers a smooth surface for the overlying antifuse layer.

Method for fabricating a semiconductor device having copper layer

Abstract: A semiconductor device comprises a plurality of transistors A semiconductor device comprising a plurality of transistors formed on a semiconductor substrate and a metal interconnection layer connected to at least one of the transistors, wherein the metal interconnection layer is composed of a single layer or multi layers, the single layer or at least one layer of the multi layers being formed of copper or a copper alloy, and is connected to at least one transistor wholly or partially through a barrier layer; and at least one of the transistor is controlled on its threshold voltage by a selective ion implantation after formation of the metal interconnection layer.

Method of forming a barrier layer which enables a consistently highly oriented crystalline structure in a metallic interconnect

Abstract: The aluminum crystal orientation content of an aluminum interconnect layer or the copper crystal orientation content of a copper interconnect can be maintained at a consistently high value during the processing of an entire series of semiconductor substrates in a given process chamber. To provide the stable and consistent aluminum content, or the stable and consistent copper content, it is necessary that the barrier layer structure underlying the aluminum or the copper have a consistent crystal orientation throughout the processing of the entire series of substrates, as well. We have determined that to ensure the consistent crystal orientation content of the barrier layer structure, it is necessary to form the first layer of the barrier layer structure to have a minimal thickness of at least about 150 Å, to compensate for irregularities in the crystal orientation which may by present during the initial deposition of this layer. As an alternative to increasing the thickness of the first layer of the barrier layer structure, this first layer can be deposited a low process chamber pressure, so that harmful irregularities in the crystal orientation are eliminated.

Stain blocking barrier layer

Abstract: The present invention is directed to a barrier layer which has the ability to substantially prevent the diffusion of stains, such as plasticizers and dyes or other chemicals, onto a surface of a surface covering, from a surface or object in which the surface covering is placed upon. The barrier layer contains a polyamide or polyurethane and is preferably located above a substrate or base layer in a surface covering. The barrier layer preferably is located between a UV topcoat layer and a vinyl wear layer. The present invention also relates to a method of preventing stain migration onto a surface covering from a surface on which the surface covering is placed by use of the barrier layer of the present invention and also relates to methods of making surface coverings containing the barrier layer of the present invention.