Showing papers on "Barrier layer published in 1998"

Apparatus and method for electrolytically depositing a metal on a microelectronic workpiece

Abstract: A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less than or equal to about 500 Angstroms. The ultra-thin seed layer is then enhanced by depositing additional metal thereon to provide an enhanced seed layer. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece.

Interconnect structure in a semiconductor device and method of formation

Abstract: In one embodiment, a conductive interconnect ( 38 ) is formed in a semiconductor device by depositing a dielectric layer ( 28 ) on a semiconductor substrate ( 10 ). The dielectric layer ( 28 ) is then patterned to form an interconnect opening ( 29 ). A tantalum nitride barrier layer ( 30 ) is then formed within the interconnect opening ( 29 ). A catalytic layer ( 31 ) comprising a palladium-tin colloid is then formed overlying the tantalum nitride barrier layer ( 30 ). A layer of electroless copper ( 32 ) is then deposited on the catalytic layer ( 31 ). A layer of electroplated copper ( 34 ) is then formed on the electroless copper layer ( 32 ), and the electroless copper layer ( 32 ) serves as a seed layer for the electroplated copper layer ( 34 ). Portions of the electroplated copper layer ( 34 ) are then removed to form a copper interconnect ( 38 ) within the interconnect opening ( 29 ).

Organic electroluminescent device having a protective covering comprising organic and inorganic layers

Abstract: An organic electroluminescent device comprises an electroluminescent unit having an organic layer structure provided between a pair of electrodes and capable of emitting light on application of a voltage thereto. The electroluminescent unit is covered with a protective double layer made of an organic barrier layer and an inorganic barrier layer formed on the unit in this order.

Method to selectively fill recesses with conductive metal

Abstract: Recesses in a semiconductor structure are selectively plated by providing electrical insulating layer over the semiconductor substrate and in the recesses followed by forming a conductive barrier over the insulating layer; providing a plating seed layer over the barrier layer; depositing and patterning a photoresist layer over the plating seed layer; planarizing the insulated horizontal portions by removing the horizontal portions of the seed layer between the recesses; removing the photoresist remaining in the recesses; and then electroplating the patterned seed layer with a conductive metal using the barrier layer to carry the current during the electroplating to thereby only plate on the seed layer. In an alternative process, a barrier film is deposited over recesses in an insulator. Then, relatively thick resists are lithographically defined on the field regions, on top of the barrier film over the recesses. A plating base or seedlayer is deposited, so as to be continuous on the horizontal regions of the recesses in the insulator, but discontinuous on their surround wall. The recesses are then plated using the barrier film without seedlayers at the periphery of the substrate wafers for electrical contact. After electroplating, the resist is removed by lift-off process and exposed barrier film is etched by RIE method or by CMP. Also provided is a semiconductor structure obtained by the above processes.

Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same

Abstract: A method to achieve a very low effective dielectric constant in high performance back end of the line chip interconnect wiring and the resulting multilayer structure are disclosed. The process involves fabricating the multilayer interconnect wiring structure by methods and materials currently known in the state of the art of semiconductor processing; removing the intralevel dielectric between the adjacent metal features by a suitable etching process; applying a thin passivation coating over the exposed etched structure; annealing the etched structure to remove plasma damage; laminating an insulating cover layer to the top surface of the passivated metal features; optionally depositing an insulating environmental barrier layer on top of the cover layer; etching vias in the environmental barrier layer, cover layer and the thin passivation layer for terminal pad contacts; and completing the device by fabricating terminal input/output pads. The method obviates issues such as processability and thermal stability associated with low dielectric constant materials by avoiding their use. Since air, which has the lowest dielectric constant, is used as the intralevel dielectric the structure created by this method would possess a very low capacitance and hence fast propagation speeds. Such structure is ideally suitable for high density interconnects required in high performance microelectronic device chips.

Method of and apparatus for forming a metal interconnection in the contact hole of a semiconductor device

Abstract: A method and an apparatus of fabricating a metal interconnection in a contact hole of a semiconductor device reduces contact resistance and improves step coverage. A contact hole is opened in an interlayer insulating film formed on a semiconductor substrate. A conductive layer used as an ohmic contact layer is formed on the interlayer insulating film including the contact hole. An upper surface of the conductive layer is nitrided to form a protective layer. An ALD (atomic layer deposition)-metal barrier layer is formed on the protective layer. The resulting metal barrier layer has good step coverage and no impurities, and the protective layer prevents defects in the conductive layer caused by precursor impurities used during the formation of the metal barrier layer.

Shallow trench isolation filled by high density plasma chemical vapor deposition

Abstract: A method for filling shallow trenches 28 with a HDPCVD oxide 50. The invention has two liners: (a) a thermal oxide liner 36 and (b) an overlying conformal O 3 -TEOS protective liner 40. The O 3 -TEOS protective liner 40 prevents the HDPCVD oxide 50 from sputter damaging the trench sidewalls and the masking layer 24. The O 3 -TEOS layer has novel process temperature (400 to 560° C.) and low pressure (40 to 80 torr) that allows the O 3 -TEOS layer to deposit uniformly over thermal oxide liner 36. The method begins by forming pad oxide layer 20 and a barrier layer 24 over a substrate. A trench 28 is formed in the substrate 10 through the pad oxide layer 20 and the barrier layer 24. A thermal oxide liner 36 and a protective O 3 -TEOS liner layer 40 are formed over the walls of the trench 28 and over the barrier layer 24. Lastly, a high density plasma chemical vapor deposition (HDPCVD) oxide layer 50 is formed over the protective liner layer 40 filling the trench 28.

Copper metallization of USLI by electroless process

Abstract: The invention provides three embodiments for forming Cu/Au contacts and interconnects using electroless deposition. The three embodiments have different adhesion and barrier layers for the electroless Cu or Au plugs. The invention discloses a technique of utilizing electroless deposition in USLI circuits. This metalization process is an additive and selective to provide conducting layers as well as an interconnection between layers of a multilevel conductive metal semiconductor device. The first embodiment uses adhesion layers formed of Ni, Al, polysilicon or PdSi x ; and a barrier layer composed of Ni—B, Ni, Pd, or Co and has first and second metal plugs formed by selective Cu or Au electroless processes. The second embodiment forms adhesion layers of PdSi x . The third embodiment forms adhesion layers of activated Ti or Al. Cu or Au plugs are selectively electroless deposited to form interconnects.

Gas-sensing semiconductor devices

Abstract: A gas-sensing semiconductor device (1) is fabricated on a silicon substrate (2) having a thin silicon oxide insulating layer (3) on one side and a thin silicon layer (4) on top of the insulating layer (3) using CMOS SOI technology. The silicon layer (4) may be in the form of an island surrounded by a silicon oxide insulating barrier layer (4) formed by the known LOCOS oxidation technique, although other lateral isolation techniques may also be used. The device (1) includes at least one sensing area provided with a gas-sensitive layer (18), a MOSFET heater (6) for heating the gas-sensitive layer (18) to promote gas reaction with the gas-sensitive layer (18) and a sensor (16), which may be in the form of a chemoresistor, for providing an electrical output indicative of gas reaction with the gas-sensitive layer (18). As one of the final fabrication steps, the substrate (2) is back-etched so as to form a thin membrane (20) in the sensing area. Such a device can be produced at low cost using conventional CMOS SOI technology.

Heterojunction field effect transistor

Abstract: A heterojunction field effect transistor realizing a high performance by a significant decrease. in source resistance while maintaining a sufficiently high gate resistivity to voltage is provided. Sequentially stacked on a c-face sapphire substrate via a buffer layer are an undoped GaN layer, undoped Al 0 .3 Ga 07 N layer, undoped GaN channel layer, undoped Al 0 .15 Ga 0 .85 N spacer layer, n-type Al 0 .15 Ga 0 .85 N electron supply layer, graded undoped Al z Ga 1-z N barrier layer and n-type Al 0 .06 Ga 0 .94 N contact layer, and a gate electrode, source electrode and drain electrode are formed on the n-type Al 0 .06 Ga 0 .94 N contact layer to form a AlGaN/GaN HEMT. The Al composition z in the graded undoped Al z Ga 1-z N barrier layer continuously decreases from 0.15 to 0.06, for example, from the n-type Al 0 .15 Ga 0 .85 N electron supply layer toward the n-type Al 0 .06 Ga 0 .94 N contact layer. An n ++ -type GaN contact layer may be formed on the n-type Al 0 .06 Ga 0 .94 N contact layer in the region for the source electrode and the drain electrode, and the source electrode and the drain may be formed on it.

Fabrication and properties of heteroepitaxial magnetite (Fe3O4) tunnel junctions

Abstract: Micron-size magnetic tunnel junctions consisting of ferromagnetic Fe3O4 electrodes, with MgO as a barrier layer, have been fabricated on (100) MgO substrates. Reflection high-energy electron diffraction and transmission electron microscopy studies reveal that the Fe3O4/MgO/Fe3O4 trilayers grown by pulsed laser deposition are heteroepitaxial with abrupt interfaces. To achieve different coercivities for the top and bottom Fe3O4 layers, the trilayers are grown on MgO substrates with a CoCr2O4 buffer layer. The junctions exhibit nonlinear current–voltage characteristics and changes in junction resistance with applied field corresponding to the coercivities of the two magnetic layers. However, the observed magnetoresistance (∼0.5% at 300 K, ∼1.5% at 150 K) is much lower than would be expected for a highly spin-polarized system. Possible reasons for the reduced magnetoresistance are discussed.

Transparent, flexible permeability barrier for organic electroluminescent devices

Abstract: A barrier for preventing water or oxygen from a source thereof from reaching a device that is sensitive to water or oxygen. The barrier is constructed by depositing a first polymer layer between the device and the source. An inorganic layer is deposited on the first polymer layer of the device by plasma enhanced chemical vapor deposition utilizing an electron cyclotron resonance source ECR-PECVD. A second polymer layer is then deposited on the inorganic layer. The inorganic layer is preferably an oxide or nitride. A second barrier layer having a compound that absorbs oxygen or water can be placed between the inorganic layer and the device to further retard the passage of oxygen or water. The present invention is particularly useful in encapsulating electroluminescent displays.

Barrier layers for electroplated SnPb eutectic solder joints

Abstract: The present invention provides a means of fabricating a reliable C4 flip-chip structure for low-temperature joining The electrochemically fabricated C4 interconnection has a barrier layer between the electroplated tin-rich solder bump and the ball-limiting metallurgy that protects the terminal metal in the ball-limiting metallurgy from attack by the Sn in the solder The barrier layer is electroplated through the same photoresist mask as the solder and thus does not require a separate patterning step A thin layer of electroplated nickel serves as a reliable barrier layer between a copper-based ball-limiting metallurgy and a tin-lead (Sn--Pb) eutectic C4 ball

Electrolessly deposited diffusion barriers for microelectronics

Abstract: Electrolessly deposited materials were investigated as possible diffusion barrier layers for multilayer microelectronic structures. Attention was focused on selective deposition of barrier layers on various surfaces, the barrier's capability to inhibit Cu diffusion, changes in Cu resistivity caused by barrier material diffusion into Cu, and adhesion between a polyimide film and the barrier layer. Electroless Co(P) was the most effective barrier to Cu diffusion at elevated temperature, even at Co(P) thicknesses as low as 500 A. Diffusion-barrier effectiveness of electrolessly deposited materials decreased in the following order: Co(P) > Ni-Co(P) ≃ Ni(P) > pure metals Co, Ni). Although a polyimide film bonded strongly to electrolessly deposited Ni(P) layers and only weakly to as-deposited Co(P), electroless Ni(P) significantly increased the Cu resistivity through interdiffusion. Polyimide adhesion to Co(P) was improved by oxidizing a Co(P) surface immediately after deposition to grow a passive film 50-75 A thick, yielding a surface to which the polyimide adheres strongly and reproducibly. A low-energy-beam, scanning electron microscopy/energy-dispersive X-ray analysis technique (SEM/EDX) was developed to measure the nonoxidized thin Co(P) barrier layer thickness.

Barrier Properties of Very Thin Ta and TaN Layers Against Copper Diffusion

Abstract: Diffusion barrier properties of very thin sputtered Ta and reactively sputtered TaN films used as a barrier layer between Cu and Si substrates were investigated using electrical measurement and materials analysis. The Cu/Ta/p + -n junction diodes with the Ta barrier of 5, 10, and 25 nm thicknesses were able to sustain a 30 min thermal annealing at temperatures up to 450, 500, and 550°C, respectively, without causing degradation to the device's electrical characteristics. The barrier capability of Ta layer can be effectively improved by incorporation of nitrogen in the Ta film using reactive sputtering technique. For the Cu/TaN/p + -n junction diodes with the TaN barrier of 5, 10, and 25 nm thicknesses, thermal stability was able to reach 500, 600, and 700°C, respectively. We found that failure of the very thin Ta and TaN barriers was not related to Ta silicidation at the barrier/Si interface. Failure of the barrier layer is presumably due to Cu diffusion through the barrier layer during the process of thermal annealing via local defects, such as grain boundaries and stress-induced weak points.

Dual damascene metallization

Abstract: The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual darmascene interconnect module that incorporates a barrier layer (54) deposited on all exposed surface of a dielectric layer which contains a dual damascene via and wire definition (48, 50). A conductive metal (60, 62) is deposited on the barrier layer using two or more deposition methods to fill the via (48) and wire (50) definition prior to planarization.

Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with cooper

Abstract: Improved methods for filling openings in silicon substrates with copper and the metal interconnects so produced are provided. One method involves the use of a Ti x Al y N z barrier layer which is stable to the high temperatures required to reflow copper after PVD deposition. Another method involves the use of an aluminum wetting layer between a barrier layer and the copper which effectively lowers the temperature at which copper reflows and therefore allows the use of typical barrier layers.

Diffusion barrier layers and methods of forming same

Abstract: A method for use in the fabrication of integrated circuits includes providing a substrate assembly having a surface and forming a barrier layer over at least a portion of the surface. The barrier layer is formed of a platinum(x):ruthenium(1−x) alloy, where x is in the range of about 0.60 to about 0.995; preferably, x is in the range of about 0.90 to about 0.98. The barrier layer may be formed by chemical vapor deposition and the portion of the surface upon which the barrier layer is formed may be a silicon containing surface. The method is used in formation of capacitors, storage cells, contact liners, etc.

Copper interconnect structure and method of formation

Abstract: In one embodiment, a copper interconnect structure is formed by depositing a dielectric layer ( 28 ) on a semiconductor substrate ( 10 ). The dielectric layer ( 28 ) is then patterned to form interconnect openings ( 29 ). A layer of copper ( 34 ) is then formed within the interconnect openings ( 29 ). A portion of the copper layer ( 34 ) is then removed to form copper interconnects ( 39 ) within the interconnect openings ( 29 ). A copper barrier layer ( 40 ) is then formed overlying the copper interconnects ( 39 ). Adhesion between the copper barrier layer ( 40 ) and the copper interconnects ( 39 ) is improved by exposing the exposed surface of the copper interconnects ( 39 ) to a plasma generated using only ammonia as a source gas.

Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof

Abstract: Semiconductor devices having a metal gate electrode and a titanium or tantalum nitride gate dielectric barrier layer and processes for fabricating such devices are provided. The use of a metal gate electrode along with a titanium or tantalum nitride gate dielectric barrier layer can, for example, provide a highly reliable semiconductor device having an increased operating speed as compared to conventional transistors.

Complementary metal gates and a process for implementation

Abstract: A transistor device includes a gate dielectric overlying a substrate, a barrier layer overlying the gate dielectric, and a gate electrode overlying the barrier layer. The barrier layer of the device has a physical property that inhibits interaction between the gate dielectric and the gate electrode.

Method of electroplating a copper or copper alloy interconnect

Abstract: Copper or a copper alloy is electroplated to fill via/contact holes and/or trenches in a dielectric layer. A barrier layer is initially deposited on the dielectric layer lining the hole/trench. A thin conformal layer of copper or a copper alloy is sputter deposited on the barrier layer outside the hole/trench. Copper or a copper alloy is then electroplated on the conformal copper or copper alloy layer and filling the hole/trench. During electroplating, the barrier layer functions as a seed layer within the hole/trench while the sputter deposited conformal copper or copper alloy layer enhances the flow of electrons from the wafer edge inwardly to provide a favorable deposition rate.

Anode modification for organic light emitting diodes

Abstract: An organic light emitting device is provided which includes a cathode (51), an anode (47, 46, 48), and an organic electroluminescent region (49, 50). The anode includes a metal layer (46), a barrier layer (47), and an anode modification layer (48). Light is emitted through the cathode (51) when a voltage is applied between the anode (47, 46, 48) and the cathode (51).

Semiconductor laser device

Abstract: PROBLEM TO BE SOLVED: To provide a gain joint type distribution feedback(DFB) laser without increase of threshold current or shortage of the service life of a laser due to crystal failures. SOLUTION: This device is made of n-type GaAs and projections 102 (fine pattern) are formed on the main surface of (n11) B surface (n=1, 2,..., 7) of a substrate 101 with a specified interval of distance, and further a barrier layer 103 made of AlGaAs is grown thereon, and then an active layer 104 made of InGaAS with island structure for confining carriers is formed through interruption of growth.

Light emitting element

Abstract: PROBLEM TO BE SOLVED: To provide a light emitting element with high light emission efficiency and a low operation current or a low threshold current. SOLUTION: A p-type impurity is doped having in the vicinity of an interface in the [000-1] direction in a quantum well layer 8b or is doped heavily near an interface in the [000-1] direction in a barrier layer 8a. Or an n-type impurity may be doped heavily near an interface in the [0001] direction in a quantum well layer 8b or doped heavily near an interface in the [0001] direction in a barrier layer 8a. In this way, at least p-type or n-type impurity is added uniformly in the light emitting layer in the quantum well structure, so that the potential generated by piezoelectric effect in the confinement direction can be reduced in the quantum well structure. Then, the isolation between electorons and holes injected as a current can be restricted, and a decrease in luminous efficiency and the increase in operation current or threshold current can be reduced.

Ferromagnetic tunnel-junction magnetic sensor utilizing a barrier layer having a metal layer carrying an oxide film

Abstract: A ferromagnetic tunnel-junction magnetic sensor includes a first ferromagnetic layer, an insulation barrier layer formed on the first ferromagnetic layer and including therein a tunnel oxide film, and a second ferromagnetic layer formed on the insulation barrier layer, wherein the insulation barrier layer includes a metal layer carrying the tunnel oxide film thereon such that the tunnel oxide film is formed of an oxide of a metal element constituting the metal layer, and wherein the insulation barrier layer has a thickness of about 1.7 nm or less but larger than 1 molecular layer in terms of the oxide forming the tunnel oxide film.

Enhanced Thermionic Emission Cooling in High Barrier Superlattice Heterostructures

Abstract: Thermionic emission current in heterostructures can be used to enhance thermoelectric properties beyond what can be achieved with conventional bulk materials. The Bandgap discontinuity at the junction between two materials is used to selectively emit hot electrons over a barrier layer from cathode to anode. This evaporative cooling can be optimized at various temperatures by adjusting the barrier height and thickness. Theoretical and experimental results for nonisothermal thermionic emission in heterostructures are presented. Single stage InGaAsP-based heterostructure integrated thermionic (HIT) coolers are fabricated and characterized. Cooling on the order of a degree over one micron thick barriers has been observed. Nonisothermal transport in highly doped tall barrier superlattices is also investigated. An order of magnitude improvement in cooling efficiency is predicted for InAlAs/InP superlattices.

A method for preventing electroplanting of copper on an exposed surface at the edge exclusion of a semiconductor wafer

Abstract: A method for forming a copper interconnect (54) begins by depositing a barrier layer (48). An intermediate layer (50) is formed over the barrier layer (48) by exposing the barrier layer (48) to a plasma silane environment. The layer (50) is conductive when deposited so that contact resistance is not affected. The layer(50) is insitu covered with a copper seed layer (52). The layer (52) is not formed in an edge exclusion region (20) thereby exposing a portion (50a) of the layer (50). This portion (50a) will natively oxidize in a room ambient to form a copper electroplating prevention barrier whereby copper will not electroplate in the region (20). Therefore, the region (50a) prevents barrier-to-copper interfaces to avoid delamination of the copper while preserving the edge exclusion region desired for copper electroplating.

Semiconductor device with a copper barrier layer and formation thereof

Abstract: A method of forming a semiconductor device by first providing a substrate in a processing chamber. The substrate has an insulating layer and an opening in the insulating layer. A copper barrier layer is formed on the insulating layer and in the opening by providing a plurality of refractory metal atoms and a plurality of silicon atoms in the processing chamber. The atoms are ionized by applying a first bias to the atoms to form a plasma. The substrate is then biased by a first stage bias followed by a second stage bias to accelerate the plasma to the substrate to form the copper barrier layer, where the first stage bias is less than the second stage bias. The copper-containing metal is then deposited on the copper barrier layer over the insulating layer and in the opening. The present invention further includes a semiconductor device formed by the above method.

Magnetic recording medium having a nitrogen-containing barrier layer

Abstract: A magnetic recording medium having a barrier layer deposited directly on the magnetic recording layer is described. The barrier layer is deposited by sputter deposition under a nitrogen-containing sputtering atmosphere to form a nitrogen-containing chromium or chromium alloy barrier layer. The barrier layer is effective to inhibit migration of cobalt from the underlying magnetic recording layer, reducing corrosion of the medium and improving magnetic recording performance.