Showing papers on "Barrier layer published in 2002"

CaCu3Ti4O12: One-step internal barrier layer capacitor

Abstract: There has been much recent interest in a so-called “giant-dielectric phenomenon” displayed by an unusual cubic perovskite-type material, CaCu3Ti4O12; however, the origin of the high permittivity has been unclear [M. A. Subramanian, L. Dong, N. Duan, B. A. Reisner, and A. W. Sleight, J. Solid State Chem. 151, 323 (2000); C. C. Homes, T. Vogt, S. M. Shapiro, S. Wakimoto, and A. P. Ramirez, Science 293, 673 (2001); A. P. Ramirez, M. A. Subramanian, M. Gardel, G. Blumberg, D. Li, T. Vogt, and S. M. Shapiro, Solid State Commun. 115, 217 (2000)]. Impedance spectroscopy on CaCu3Ti4O12 ceramics demonstrates that they are electrically heterogeneous and consist of semiconducting grains with insulating grain boundaries. The giant-dielectric phenomenon is therefore attributed to a grain boundary (internal) barrier layer capacitance (IBLC) instead of an intrinsic property associated with the crystal structure. This barrier layer electrical microstructure with effective permittivity values in excess of 10 000 can be fa...

Group-iii nitride based high electron mobility transistor (hemt) with barrier/spacer layer

Abstract: A group III nitride based high electron mobility transistor (HEMT) (10) is disclosed that provides improved high frequency performance. One embodiment of the HEMT (10) comprises a GaN buffer layer (26), with an AlyGa1-yN (y=1 or y 1) layer (28) on the Gan buffer layer (26). An AlxGa1-xN (0≤x≤0.5) barrier layer (30) is on the AlyGa1-yN layer (28), opposite the GaN buffer layer (26), the AlyGa1-yN layer (28) having a higher Al concentration than that of the AlxGa1-xN barrirer layer (30). A preferred AlyGa1-yN layer (28) has y=1 or y≃1 and a preferred AlxGa1-xN barrier layer (30) has 0≤0.5. A 2DEG (38) forms at the interface between the GaN buffer layer (26) and the AlyGa1-yN layer (28). Respective source, drain and gate contacts (32, 34, 36) are formed on the AlxGa1-xN barrier layer (30). The HEMT (10) can also include a substrate (22) adjacent to the buffer layer (26), opposite the AlyGa1-yN layer (28) and a nucleation layer (24) can be included between the GaN buffer layer (26) and the substrate (22).

Multiple layer phase-change memory

Abstract: A phase-change memory may be formed with at least two phase-change material layers separated by a barrier layer. The use of more than one phase-change layer enables a reduction in the programming volume while still providing adequate thermal insulation.

Observations of barrier layer formation in the Bay of Bengal during summer monsoon

Abstract: Time series of temperature and salinity in the upper ocean,measured at 17degrees30'N, 89degreesE in the northern Bay of Bengal,from 27 July to 6 August 1999 captured an event of upper layer freshening. Initially, the upper layer that is homogeneous in both temperature and salinity was about 30 m deep. Subsequently, the arrival of a freshwater plume caused the depth of the mixed layer to decrease to about 10 m and the salinity in the surface layer by about 4 psu. The plume led to the formation of a new halocline and hence a barrier layer within the upper 30 m of the water column. The ensuing ocean-atmosphere interaction was restricted to the new thinner mixed layer. The cooling that was restricted to the mixed layer led to an inversion in temperature amounting to 0.5degreesC just below the mixed layer. The source of the plume is traced to freshwater from river discharge and rainfall that was advected by Ekman flow as a 15 m thick layer. This study suggests that wind-driven circulation is crucial in determining the path of freshwater in the Bay of Bengal. The fresh water affects the sea surface temperature and ocean-atmosphere coupling through the dependence of the depth of the mixed layer on salinity.

Barrier formation using novel sputter deposition method with PVD, CVD, or ALD

Abstract: Methods and apparatus are provided for forming a metal or metal silicide barrier layer. In one aspect, a method is provided for processing a substrate including positioning a substrate having a silicon material disposed thereon in a substrate processing system, depositing a first metal layer on the substrate surface in a first processing chamber, forming a metal silicide layer by reacting the silicon material and the first metal layer, and depositing a second metal layer in situ on the substrate in a second processing chamber. In another aspect, the method is performed in an apparatus including a load lock chamber, the intermediate substrate transfer region including a first substrate transfer chamber and a second substrate transfer chamber, a physical vapor deposition processing chamber coupled to the first substrate transfer chamber, and a chemical vapor deposition chamber coupled to the second substrate transfer chamber.

Integration of ALD tantalum nitride and alpha-phase tantalum for copper metallization application

Abstract: A method for forming a metal interconnect on a substrate is provided. The method includes depositing a refractory metal-containing barrier layer having a thickness less than about 20 angstroms on at least a portion of a metal layer by alternately introducing one or more pulses of a metal-containing compound and one or more pulses of a nitrogen-containing compound. The method also includes depositing a seed layer on at least a portion of the barrier layer, and depositing a second metal layer on at least a portion of the seed layer. The barrier layer provides adequate barrier properties and allows the grain growth of the metal layer to continue across the barrier layer into the second metal layer thereby enhancing the electrical performance of the interconnect.

Insulating gate AlGaN/GaN HEMT

Abstract: AlGaN/GaN HEMTs are disclosed having a thin AlGaN layer to reduce trapping and also having additional layers to reduce gate leakage and increase the maximum drive current. One HEMT according to the present invention comprises a high resistivity semiconductor layer with a barrier semiconductor layer on it. The barrier layer has a wider bandgap than the high resistivity layer and a 2DEG forms between the layers. Source and drain contacts contact the barrier layer, with part of the surface of the barrier layer uncovered by the contacts. An insulating layer is included on the uncovered surface of the barrier layer and a gate contact is included on the insulating layer. The insulating layer forms a barrier to gate leakage current and also helps to increase the HEMT's maximum current drive. The invention also includes methods for fabricating HEMTs according to the present invention. In one method, the HEMT and its insulating layer are fabricated using metal-organic chemical vapor deposition (MOCVD). In another method the insulating layer is sputtered onto the top surface of the HEMT in a sputtering chamber.

Method of electroless plating copper on nitride barrier

Abstract: A method with three embodiments of manufacturing metal lines and solder bumps using electroless deposition techniques. The first embodiment uses a PdSi x seed layer 50 for electroless deposition. The PdSi x layer 50 does not require activation. A metal line is formed on a barrier layer 20 and an adhesion layer 30. A Palladium silicide seed layer 50 is then formed and patterned. Ni, Pd or Cu is electroless deposited over the Palladium silicide layer 50 to form a metal line. The second embodiment selectively electrolessly deposits metal 140 over an Adhesion layer 130 composed of Poly Si, Al, or Ti. A photoresist pattern 132 is formed over the adhesion layer. A metal layer 140 of Cu or Ni is electrolessly deposited over the adhesion layer. The photoresist layer 132 is removed and the exposed portion of the adhesion layer 130 and the underlying barrier metal layer 120 are etched thereby forming a metal line. The third embodiment electroless deposits metal over a metal barrier layer that is roughen by chemical mechanical polishing. A solder bump is formed using an electroless deposition of Cu or Ni by: depositing an Al layer 220 and a barrier metal layer 230 over a substrate 10. The barrier layer 230 is polished and activated. Next, the aluminum layer 220 and the barrier metal layer 230 are patterned. A metal layer 240 is electroless deposited. Next a solder bump 250 is formed over the electroless metal layer 240.

Electroless deposition apparatus

Abstract: An apparatus and a method of depositing a catalytic layer comprising at least one metal selected from the group consisting of noble metals, semi-noble metals, alloys thereof, and combinations thereof in sub-micron features formed on a substrate. Examples of noble metals include palladium and platinum. Examples of semi-noble metals include cobalt, nickel, and tungsten. The catalytic layer may be deposited by electroless deposition, electroplating, or chemical vapor deposition. In one embodiment, the catalytic layer may be deposited in the feature to act as a barrier layer to a subsequently deposited conductive material. In another embodiment, the catalytic layer may be deposited over a barrier layer. In yet another embodiment, the catalytic layer may be deposited over a seed layer deposited over the barrier layer to act as a “patch” of any discontinuities in the seed layer. Once the catalytic layer has been deposited, a conductive material, such as copper, may be deposited over the catalytic layer. In one embodiment, the conductive material is deposited over the catalytic layer by electroless deposition. In another embodiment, the conductive material is deposited over the catalytic layer by electroless deposition followed by electroplating or followed by chemical vapor deposition. In still another embodiment, the conductive material is deposited over the catalytic layer by electroplating or by chemical vapor deposition.

Method of depositing dielectric materials in damascene applications

Abstract: Methods are provided for depositing an oxygen-doped dielectric layer. The oxygen-doped dielectric layer may be used for a barrier layer or a hardmask. In one aspect, a method is provided for processing a substrate including positioning the substrate in a processing chamber, introducing a processing gas comprising an oxygen-containing organosilicon compound, carbon dioxide, or combinations thereof, and an oxygen-free organosilicon compound to the processing chamber, and reacting the processing gas to deposit an oxygen-doped dielectric material on the substrate, wherein the dielectric material has an oxygen content of about 15 atomic percent or less. The oxygen-doped dielectric material may be used as a barrier layer in damascene or dual damascene applications.

Electroless deposition method

Abstract: Methods and apparatus are provided for forming a metal or metal silicide layer by an electroless deposition technique. In one aspect, a method is provided for processing a substrate including depositing an initiation layer on a substrate surface, cleaning the substrate surface, and depositing a conductive material on the initiation layer by exposing the initiation layer to an electroless solution. The method may further comprise etching the substrate surface with an acidic solution and cleaning the substrate of the acidic solution prior to depositing the initiation layer. The initiation layer may be formed by exposing the substrate surface to a noble metal electroless solution or a borane-containing solution. The conductive material may be deposited with a borane-containing reducing agent. The conductive material may be used as a passivation layer, a barrier layer, a seed layer, or for use in forming a metal silicide layer.

Packaging material for battery

Abstract: Disclosed is a packaging material for forming an armor body for a battery, the armor body being adapted for use in such a manner that a battery body is inserted into the armor body and the peripheral edge of the armor body is then heat sealed for hermetic sealing, the packaging material being a laminate comprising at least a substrate layer, an adhesive layer, a barrier layer, a dry laminate layer, and a sealant layer, characterized in that at least the sealant layer comprises a low-fluidity polypropylene layer having low susceptibility to collapse upon exposure to heat and pressure at the time of heat sealing and a high-fluidity polypropylene layer having high susceptibility to collapse upon exposure to heat and pressure at the time of heat sealing, and the innermost layer is the high-fluidity polypropylene layer. This battery packaging material can impart moisture barrier properties and resistance to contents of the battery.

Strain balanced nitride heterojunction transistors and methods of fabricating strain balanced nitride heterojunction transistors

Abstract: A nitride based heterojunction transistor includes a substrate and a first Group III nitride layer, such as an AlGaN based layer, on the substrate. The first Group III-nitride based layer has an associated first strain. A second Group III-nitride based layer, such as a GaN based layer, is on the first Group III-nitride based layer. The second Group III-nitride based layer has a bandgap that is less than a bandgap of the first Group III-nitride based layer and has an associated second strain. The second strain has a magnitude that is greater than a magnitude of the first strain. A third Group III-nitride based layer, such as an AlGaN or AlN layer, is on the GaN layer. The third Group III-nitride based layer has a bandgap that is greater than the bandgap of the second Group III-nitride based layer and has an associated third strain. The third strain is of opposite strain type to the second strain. A source contact, a drain contact and a gate contact may be provided on the third Group III-nitride based layer. Nitride based heterojunction transistors having an AlGaN based bottom confinement layer, a GaN based channel layer on the bottom confinement layer and an AlGaN based barrier layer on the channel layer, the barrier layer having a higher concentration of aluminum than the bottom confinement layer, are also provided. Methods of fabricating such transistor are also provided.

Formation and Microstructures of Anodic Alumina Films from Aluminum Sputtered on Glass Substrate

Abstract: A transparent porous alumina nanostructure was formed on a glass covered tin-doped indium oxide ~ITO! substrate by anodization of a highly pure sputtered aluminum layer. Details of the fabrication and microstructures of porous anodic alumina films are described and a possible mechanism of anodization is outlined. The variation of anodic current density reflects three processes, i.e., ~i! anodization of the sputtered aluminum layer, ~ii! transition of electrolysis from aluminum to the underlying ITO film, and~iii! electrochemical reactions on the ITO film beneath the anodic alumina film. As all the aluminum is completely anodized, the resultant oxide films on the ITO/glass substrate possess a parallel porous structure ~f80-100 nm, cell size in ;350 nm! with a thin arched barrier layer ~;80 nm! and exhibit a high transmittance in the ultraviolet-visible light range ~75-100% transmittance 300-900 nm!.

Capacitor compatible with high dielectric constant materials having two independent insulative layers and the method for forming same

Abstract: The invention is a storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode comprising a barrier layer interposed between a conductive plug and an oxidation resistant layer. A thick insulative layer protects the sidewalls of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant. The method comprises forming the conductive plug in a thick layer of insulative material such as oxide or oxide/nitride. The conductive plug is recessed from a planarized top surface of the thick insulative layer. The barrier layer is then formed in the recess. The process is continued with a formation of a second insulative layer, a potion of which is removed to form an opening exposing a portion of the barrier layer. An oxidation resistant conductive layer is deposited in the recess and forms at least a portion the storage node electrode of the capacitor. Next a dielectric layer having a high dielectric constant is formed to overly the storage node electrode and a cell plate electrode is fabricated to overly the dielectric layer.

Barrier enhancement process for copper interconnects

Abstract: A damascene process for introducing copper into metallization layers in microelectronic structures includes a step of forming an enhancement layer (24) of a metal alloy, such as a copper alloy or Co-W-P, over the barrier layer (16), using PVD, CVD or electrochemical deposition prior to electrochemically depositing copper metallization. The enhancement layer (24) has a thickness from 101 to 1001 and conformally covers the discontinuities, seams and grain boundary defects in the barrier layer. The enhancement layer provides a conductive surface onto which a metal layer, such as copper metallization, may be applied with electrochemical deposition. Alternatively, a seed layer (28) may be deposited over the enhancement layer prior to copper metallization.

Etch stop for copper damascene process

Abstract: The invention describes the application of copper damascene connectors to a double level metal process. A dual damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded is described. Out-diffusion of copper from the connector is prevented by at least two barrier layers. One or two barrier layers are located at the interface between the connector and the insulating layer while another barrier layer comprises conductive material and covers the upper surface of the connector. When a second damascene connector is formed above the first connector the conductive barrier layer facilitates good contact between the two connectors. It also acts as an etch stop layer during the formation of the second connector. A process for manufacturing this structure is also described. It involves over-filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing.

Influence of Si-doping on the characteristics of InGaN-GaN multiple quantum-well blue light emitting diodes

Abstract: A detailed study on the effects of Si-doping in the GaN barrier layers of InGaN-GaN multiquantum well (MQW) light-emitting diodes (LEDs) has been performed. Compared with unintentionally doped samples, X-ray diffraction results indicate that Si-doping in barrier layers can improve the crystal and interfacial qualities of the InGaN-GaN MQW LEDs. It was also found that the forward voltage is 3.5 and 4.52 V, the 20-mA luminous intensity is 36.1 and 25.1 mcd for LEDs with a Si-doped barrier and an unintentionally doped barrier, respectively. These results suggests that one can significantly improve the performance of InGaN-GaN MQW LEDs by introducing Si doping in the GaN barrier layers.

Magnetic tunneling junction with improved power consumption

Abstract: A method and system for providing a magnetic tunneling junction is disclosed. The method and system includes providing a free layer, a pinned layer, and a barrier between the free layer and the pinned layer. The free layer and the pinned layer are ferromagnetic. The barrier layer is an insulator. The magnetic tunneling junction is coupled to a bit line. The bit line includes a ferromagnetic liner and a nonmagnetic core. The nonmagnetic core includes a top, a bottom and sides. The ferromagnetic liner includes at least one tab and is adjacent to the sides and a portion of the bottom of the nonmagnetic core. The at least one tab is adjacent to the portion of the bottom of the nonmagnetic core.

Atomically thin highly resistive barrier layer in a copper via

Abstract: A method of forming a copper via and the resultant structure. A thin layer of an insulating barrier material (30), such as aluminum oxide or tantalum nitride, is conformally coated onto the sides and bottom of the via hole, for example, by atomic layer deposition (ALD) to a thickness of less than 5nm, preferably less than 2nm and having an electrical resistivity of more than 500 microohm-cm. A copper seed layer (40) is then deposited under conditions such that copper is deposited on the via sidewalls but not deposited over most of the bottom of via hole. Instead energetic copper ions sputter the barrier material from the via bottom. Copper (50) is electroplated into the via hole lined only on its sidewalls with the barrier. The invention preferably extends also to dual-damascene structures in which the copper seed sputter process sputters the barrier layer from the via bottom but not the trench floor.

InAlN/(In)GaN high electron mobility transistors: some aspects of the quantum well heterostructure proposal

Abstract: The replacement of the AlGaN barrier layer of the AlGaN/GaN high electron mobility transistors (HEMTs) with InAlN of various In molar fractions is suggested. Internal polarization fields in the InAlN/(In)GaN quantum well are described using analytical formulae. InAlN/(In)GaN HEMTs quantum well free electron densities, transistor open channel drain currents and threshold voltages are calculated for different In molar fractions considering the maximal acceptable strain. It is suggested that 0.08 ≤ x ≤ 0.27 for a 15 nm thick InxAl1−xN barrier or 0 ≤ y ≤ 0.18 for a 5–10 nm thick InyGa1−yN channel can be applied for strain without layer relaxation while the quantum well free electron densities up to 4.6 × 1017 m−2 and the transistor open channel drain currents up to 4.5 A mm−1 can be expected.

α-tantalum lead for use with magnetic tunneling junctions

Abstract: A method and system for providing a tunneling junction is disclosed. The method and system includes providing a free layer, a pinned layer, and a barrier between the free layer and the pinned layer. The free layer and the pinned layer are ferromagnetic. The barrier layer is an insulator. The magnetic tunneling junction is coupled to an α-Ta lead.

Reliability barrier integration for Cu application

Abstract: Embodiments of the present invention provide a process sequence and related hardware for filling a patterned feature on a substrate with a metal, such as copper. The sequence comprises first forming a reliable barrier layer in the patterned feature to prevent diffusion of the metal into the dielectric layer through which the patterned feature is formed. One sequence comprises forming a generally conformal barrier layer over a patterned dielectric, etching the barrier layer at the bottom of the patterned feature, depositing a second barrier layer, and then filling the patterned feature with a metal, such as copper.

OLEDs having increased external electroluminescence quantum efficiencies

Abstract: OLED devices are disclosed having increased external electroluminescence quantum efficiencies, i.e., increased “out-coupling” efficiencies. OLED devices that have increased out-coupling efficiencies and that are also protected from environmental elements such as moisture and oxygen are also disclosed. The OLED device of the present invention comprises a substrate; an active region positioned on the substrate, wherein the active region comprises an anode layer, a cathode layer and a light-emitting layer disposed between the anode layer and the cathode layer; and a polymeric layer disposed (a) over the active region, (b) under the active region or (c) both over and under the active region. The polymeric layer has microparticles incorporated therein, and the microparticles are effective to increase the out-coupling efficiency of the OLED. In one embodiment, the OLED device comprises a composite barrier layer and the microparticles are incorporated in a polymeric planarizing sublayer of the composite barrier layer. The composite barrier layer in this embodiment also protects the OLED from damage caused by environmental elements such as moisture and/or oxygen.

Barrier formation using novel sputter-deposition method

Abstract: Methods and apparatus are provided for forming a metal or metal silicide barrier layer. In one aspect, a method is provided for processing a substrate including positioning a substrate having a silicon material disposed thereon in a substrate processing system, depositing a first metal layer on the substrate surface in a first processing chamber, forming a metal silicide layer by reacting the silicon material and the first metal layer, and depositing a second metal layer in situ on the substrate in a second processing chamber. In another aspect, the method is performed in an apparatus including a load lock chamber, the intermediate substrate transfer region including a first substrate transfer chamber and a second substrate transfer chamber, a physical vapor deposition processing chamber coupled to the first substrate transfer chamber, and a chemical vapor deposition chamber coupled to the second substrate transfer chamber.

Long life thin film battery and method therefor

Abstract: A thin film battery including an anode layer, a cathode layer and a solid electrolyte layer. The battery also includes, a planarization layer applied to the thin film battery. The planarization layer has a surface roughness of no more than about 1.0 nanometers root mean square and a flatness no larger than about 0.005 cm/inch. A barrier layer is applied to the planarization layer. The barrier layer is provided by one or more layers of material selected from the group consisting of polymeric materials, metals and ceramic materials. The planarization layer and barrier layer are sufficient to reduce oxygen flux through the barrier layer to the anode layer to no more than about 1.6 μmol/m2-day, and H2O flux through the barrier layer to the anode layer to less than about 3.3 μmol/m2-day thereby improving the life of the thin film battery.

Encapsulation for organic electronic devices

Abstract: An embodiment of the present invention pertains to encapsulating an organic electronic device by selectively depositing a catalyst layer and then exposing the catalyst layer to a monomer to produce a planarization layer. The monomer reacts only in the areas where the catalyst layer is present so there is minimal or no contamination of other areas of the organic electronic device. Selectively depositing the catalyst layer allows the resulting planarization layer to be patterned. A barrier layer is selectively deposited on at least the planarization layer. Another embodiment of the present invention pertains to encapsulating an organic electronic device by depositing a planarization layer on a transfer substrate and then allowing it to stabilize to minimize its reactivity. The planarization layer is transferred from the transfer substrate onto at least an active area of the organic electronic device. A barrier layer is selectively deposited on at least the planarization layer.

Multilayer article characterized by low coefficient of thermal expansion outer layer

Abstract: A multilayer article comprises a substrate comprising a ceramic or a silicon-containing metal alloy. The ceramic is a Si-containing ceramic or an oxide ceramic with or without silicon. An outer layer overlies the substrate and at least one intermediate layer is located between the outer layer and the substrate. An optional bond layer is disposed between the at least one intermediate layer and the substrate. The at least one intermediate layer may comprise an optional chemical barrier layer adjacent the outer layer, a mullite-containing layer and an optional chemical barrier layer adjacent to the bond layer or substrate. The outer layer comprises a compound having a low coefficient of thermal expansion selected from one of the following systems: rare earth (RE) silicates; at least one of hafnia and hafnia-containing composite oxides; zirconia-containing composite oxides and combinations thereof.