scispace - formally typeset
Search or ask a question

Showing papers on "Barrier layer published in 2005"


Patent
22 Apr 2005
TL;DR: An edge-sealed barrier film composite is described in this paper, where the composite includes a substrate and at least one initial barrier stack adjacent to the substrate, which is sealed by the first barrier layer within the area of barrier material.
Abstract: An edge-sealed barrier film composite The composite includes a substrate and at least one initial barrier stack adjacent to the substrate The at least one initial barrier stack includes at least one decoupling layer and at least one barrier layer One of the barrier layers has an area greater than the area of one of the decoupling layers The decoupling layer is sealed by the first barrier layer within the area of barrier material An edge-sealed, encapsulated environmentally sensitive device is provided A method of making the edge-sealed barrier film composite is also provided

287 citations


Journal ArticleDOI
TL;DR: In this paper, the authors investigated the possibility of the self-forming barrier layer in Cu-Mn alloy thin films deposited directly on SiO2 and found that after annealing at 450°C for 30 min, a Mn containing amorphous oxide layer of 3-4 nm in thickness was formed uniformly at the interface.
Abstract: Advancement of semiconductor devices requires the realization of an ultrathin diffusion barrier layer between Cu interconnect and insulating layers. The present work investigated the possibility of the self-forming barrier layer in Cu–Mn alloy thin films deposited directly on SiO2. After annealing at 450 °C for 30 min, a Mn containing amorphous oxide layer of 3–4 nm in thickness was formed uniformly at the interface. Residual Mn atoms were removed to form a surface oxide layer, leading to a drastic resistivity decrease of the film. No interdiffusion was detected between Cu and SiO2 within the detection limit of x-ray energy dispersive spectroscopy.

251 citations


Patent
26 Jul 2005
TL;DR: Magnetic or magnetoresistive tunnel junctions (MTJ) have diffusion stop layers to eliminate or reduce diffusion of oxygen, nitrogen or other particles from the barrier layer to the ferromagnetic layers during the film deposition process including the barrier oxidation or nitridation process and the post annealing process as discussed by the authors.
Abstract: Magnetic or magnetoresistive tunnel junctions (MTJs) having diffusion stop layers to eliminate or reduce diffusion of oxygen, nitrogen or other particles from the barrier layer to the ferromagnetic layers during the film deposition process including the barrier oxidation or nitridation process and the post annealing process. Such MTJs may be used in various applications including magnetic memory (MRAM) devices and magnetic recording heads.

200 citations


Patent
18 Feb 2005
TL;DR: In this paper, a method and system for providing a magnetic element that can be used in a magnetic memory is disclosed, which includes pinned, nonmagnetic spacer, and free layers.
Abstract: A method and system for providing a magnetic element that can be used in a magnetic memory is disclosed. The magnetic element includes pinned, nonmagnetic spacer, and free layers. The spacer layer resides between the pinned and free layers. The free layer can be switched using spin transfer when a write current is passed through the magnetic element. The magnetic element may also include a barrier layer, a second pinned layer. Alternatively, second pinned and second spacer layers and a second free layer magnetostatically coupled to the free layer are included. In one aspect, the free layer(s) include ferromagnetic material(s) diluted with nonmagnetic material(s) and/or ferrimagnetically doped to provide low saturation magnetization(s).

195 citations


Patent
14 Jun 2005
TL;DR: In this paper, an MTJ in an MRAM array or in a TMR read head is comprised of a capping layer with a lower interdiffusion barrier layer, an intermediate oxygen gettering layer, and an upper metal layer that contacts a top conductor.
Abstract: An MTJ in an MRAM array or in a TMR read head is comprised of a capping layer with a lower inter-diffusion barrier layer, an intermediate oxygen gettering layer, and an upper metal layer that contacts a top conductor. The composite capping layer is especially useful with a moderate spin polarization free layer such as a NiFe layer with a Fe content of about 17.5 to 20 atomic %. The capping layer preferably has a Ru/Ta/Ru configuration in which the lower Ru layer is about 10 to 30 Angstroms thick and the Ta layer is about 30 Angstroms thick. As a result, a high dR/R of about 40% is achieved with low magnetostriction less than about 1.0 E-6 in an MTJ in an MRAM array. Best results are obtained with an AlOx tunnel barrier layer formed by an in-situ ROX process on an 8 to 10 Angstrom thick Al layer.

182 citations


Patent
08 Aug 2005
TL;DR: In this article, a method of forming a conductor in a thin-film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls.
Abstract: A method of forming a conductor in a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier metal on the surfaces of the high aspect ratio openings including the vertical side walls, depositing a metal barrier layer comprising the barrier metal on the first barrier layer, depositing a main conductor species seed layer on the metal barrier layer and depositing a main conductor layer. The method further includes annealing the main conductor layer by (a) directing light from an array of continuous wave lasers into a line of light extending at least partially across the thin film structure, and (b) translating the line of light relative to the thin film structure in a direction transverse to the line of light. The method of Claim 1 further comprising, prior to the annealing step, depositing an amorphous carbon optical absorber layer on the main conductor layer. The step of depositing an amorphous carbon optical absorber layer includes introducing a carbon-containing process gas into a reactor chamber containing the substrate in a process zone of the reactor, applying RF source power to an external reentrant conduit of the reactor to generate a reentrant toroidal RF plasma current passing through the process zone and applying a bias voltage to the substrate.

176 citations


Patent
08 Aug 2005
TL;DR: In this article, a method of forming a barrier layer for a thin-film structure on a semiconductor substrate is proposed, which includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dieellectric compound of a barrier metal on the surfaces of the high aspect ratios openings including the vertical side wall and reflowing the metal barrier layer by directing light from an array of continuous wave lasers into a line of light extending at least partially across the thin film structure.
Abstract: A method of forming a barrier layer for a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier metal on the surfaces of the high aspect ratio openings including the vertical side walls and depositing a metal barrier layer comprising the barrier metal on the first barrier layer. The method further includes reflowing the metal barrier layer by (a) directing light from an array of continuous wave lasers into a line of light extending at least partially across the thin film structure, and (b) translating the line of light relative to the thin film structure in a direction transverse to the line of light.

172 citations


Journal ArticleDOI
TL;DR: Evidence of optical coupling between the two band gap emissions was observed and total photoluminescence quantum efficiency of the dual emitting bands reached as high as 30% at room temperature under synthetic conditions not optimized for high emission.
Abstract: Dual quantum systems, 0-dimensional quantum dot, and 2-dimensional quantum wells were constructed in one II-VI semiconductor nanocrystal by the epitaxial growth of a barrier (ZnS) layer between the systems in solution. By alteration of the thickness of the barrier layer, the two quantum systems were controlled to either electronically coupled or decoupled. Evidence of optical coupling between the two band gap emissions was also observed. The position and relative intensity of the two emissions can be independently tuned by reaction conditions. Total photoluminescence quantum efficiency of the dual emitting bands reached as high as 30% at room temperature under synthetic conditions not optimized for high emission.

168 citations


Patent
01 Nov 2005
TL;DR: In this article, a method for forming a first barrier layer over the sidewalls and bottom of a via using atomic layer deposition within an ALD chamber is described, followed by removing at least a portion of the barrier layer from the bottom of the via by sputter etching.
Abstract: In a first aspect, a method is provided that includes (1) forming a first barrier layer over the sidewalls and bottom of a via using atomic layer deposition within an atomic layer deposition (ALD) chamber; (2) removing at least a portion of the first barrier layer from the bottom of the via by sputter etching; and (3) depositing a second barrier layer on the sidewalls and bottom of the via within the ALD chamber. Numerous other embodiments are provided, as are systems, methods and computer program products in accordance with these and other aspects.

156 citations


Patent
Yiming Huai, Mahendra Pakala1
22 Dec 2005
TL;DR: In this article, a method and system for providing a magnetic element is disclosed, which includes providing first (102) and second (120) pinned layers, a free layer (114), and first (112, and second(116) barrier layers between the first and second pinned layers and the free layer.
Abstract: A method and system for providing a magnetic element are disclosed. The method and system include providing first (102) and second (120) pinned layers, a free layer (114), and first (112) and second (116) barrier layers between the first and second pinned layers, respectively, and the free layer. The first barrier layer is oreferably crystalline MgO, which is insulating, and configured to allow tunneling through the first barrier layer. Furthermore, the first barrier layer has an interface with another layer, such as the free layer or the first pinned layer. The interface has a structure that provides a high spin polarization of at least fifty percent and preferably over eighty percent. The second barrier layer is insulating and configured to allow tunneling through the second barrier layer. The magnetic element is configured to allow the free layer to be switched due to spin transfer when a write current is passed through the magnetic element.

152 citations


Patent
11 May 2005
TL;DR: In this article, a method and system for providing a magnetic element that is used in a magnetic memory device is presented. But the magnetic element includes pinned (122), spacer (13), free (140), and spin barrier layers (150), and the spin barrier layer (150) is configured to reduce an outer surface contribution to a damping constant of the free layer.
Abstract: A method and system for providing a magnetic element that is used in a magnetic memory device. The magnetic element includes pinned (122), spacer (13), free (140), and spin barrier layers (150). The spacer layer (130) is nonmagnetic and resides between the pinned (122) and free layers (140). The free layer (140) can be switched using spin transfer when a write current is passed through the magnetic element. The free layer (140) resides between the spacer layer (130) and the spin barrier (150) layer. The spin barrier layer (150) is configured to reduce an outer surface contribution to a damping constant of the free layer (140).

Journal ArticleDOI
TL;DR: For square wave depositions into sulfuric acid grown pores, the reductive/oxidative pulse polarity produces more uniform pore-filling, likely as a result of enhanced resonant tunneling through the barrier layer and reoxidation of copper in faster filling pores.
Abstract: The effect of several deposition parameters on the uniformity of copper electrodeposition through the alumina barrier layer into porous aluminum oxide templates grown in sulfuric or oxalic acid was systematically investigated. A fractional factorial design of experiment was conducted to find suitable deposition conditions among the variables: frequency, voltage, pulsed or continuous deposition, electrolyte concentration, and barrier layer thinning voltage. Continuous ac sine wave deposition conditions yielded excellent uniformity of pore-filling but damaged the porous aluminum oxide templates when deposition was continued to grow bulk copper on the surface. Pulsed electrodeposition yielded comparable uniformity of pore-filling and no damage to the porous aluminum oxide templates, even when bulk copper was deposited on them. Further optimization of pulsed deposition conditions was accomplished by comparing square and sine waveforms and pulse polarity. Pulsed square waveforms produced better pore-filling than pulsed sine waveforms. For sine wave depositions, the oxidative/reductive pulse polarity was more efficient than the commonly used reductive/oxidative pulse polarity. For square wave depositions into sulfuric acid grown pores, the reductive/oxidative pulse polarity produces more uniform pore-filling, likely as a result of enhanced resonant tunneling through the barrier layer and reoxidation of copper in faster filling pores.

Journal ArticleDOI
TL;DR: A simple method for penetrating the barrier layer of an anodic aluminum oxide (AAO) film and for detaching the AAO film from residual Al foil was developed by reversing the bias voltage in situ after the anodization process is completed.
Abstract: A simple method for penetrating the barrier layer of an anodic aluminum oxide (AAO) film and for detaching the AAO film from residual Al foil was developed by reversing the bias voltage in situ after the anodization process is completed. With this technique, we have been able to obtain large pieces of free-standing AAO membranes with regular pore sizes of sub-10 nm. By combining Ar ion milling and wetting enhancement processes, Au nanowires were grown in the sub-10 nm pores of the AAO films. Further scaling down of the pore size and extension to the deposition of nanowires and nanotubes of materials other than Au should be possible by further optimizing this procedure.

Journal ArticleDOI
TL;DR: In this article, the design, fabrication, and characterization of double-channel HEMTs are presented, where two carrier channels are formed in an AlGaN-GaN/AlGaN+GaN multilayer structure grown on a sapphire substrate.
Abstract: We present the design, fabrication, and characterization of AlGaN-GaN double-channel HEMTs. Two carrier channels are formed in an AlGaN-GaN-AlGaN-GaN multilayer structure grown on a sapphire substrate. Polarization field in the lower AlGaN layer fosters formation of a second carrier channel at the lower AlGaN-GaN interface, without creating any parasitic conduction path in the AlGaN barrier layer. Unambiguous double-channel behaviors are observed at both dc and RF. Bias dependent RF small-signal characterization and parameter extraction were performed. Gain compression at a high current level was attributed to electron velocity degradation induced by interface scattering. Dynamic IV measurement was carried out to analyze large-signal behaviors of the double-channel high-electron mobility transistors. It was found that current collapse mainly occurs in the channel closer to device surface, while the lower channel suffers minimal current collapse, suggesting that trapping/detrapping of surface states is mainly responsible for current collapse. This argument is supported by RF large-signal measurement results.

Patent
18 May 2005
TL;DR: In this article, a method and apparatus for depositing a material layer onto a substrate is described, which can be used as an encapsulating layer for various display applications which require low temperature deposition process due to thermal instability of underlying materials used.
Abstract: A method and apparatus for depositing a material layer onto a substrate is described. The method includes delivering a mixture of precursors for the material layer into a process chamber and depositing the material layer on the substrate at low temperature. The material layer can be used as an encapsulating layer for various display applications which require low temperature deposition process due to thermal instability of underlying materials used. In one aspect, the encapsulating layer includes one or more material layers (multilayer) having one or more barrier layer materials and one or more low-dielectric constant materials. The encapsulating layer thus deposited provides reduced surface roughness, improved water-barrier performance, reduce thermal stress, good step coverage, and can be applied to many substrate types and many substrate sizes. Accordingly, the encapsulating layer thus deposited provides good device lifetime for various display devices, such as OLED devices. In another aspect, a method of depositing an amorphous carbon material on a substrate at low temperature is provided. The amorphous carbon material can be used to reduce thermal stress and prevent the deposited thin film from peeling off the substrate.

Journal ArticleDOI
TL;DR: In this article, anodic aluminum oxide (AAO2O) was used as a template to prepare highly ordered Ni-Fe-Co alloy nanowire arrays and a two-step anodizing method was used to obtain an optimum barrier thickness to obtain a successful electrodeposition in pores of AAO.

Journal ArticleDOI
TL;DR: In this article, the authors evaluated the wettability of Cu on Ru and Ta glue layers as the index of Cu adhesion strength onto glue layers and found that the wetting angle of Cu (43°) on a Ru substrate was three times lower than that of Ta substrate after annealing.
Abstract: The main issue of Cu metallization is the electromigration of Cu through the interface between Cu and the barrier or capping layer. To improve electromigration resistance at the Cu and barrier metal interface, insertion of a glue layer which enhances the adhesion of Cu onto the under layer may be effective. The wettability of Cu on Ru and Ta glue layers was evaluated as the index of Cu adhesion strength onto glue layers. The wetting angle of Cu (43°) on a Ru substrate was three times lower than that of Cu (123°) on a Ta substrate after annealing. Lower wetting angle of Cu on a Ru substrate indicates a good adhesion property between Cu and Ru and may imply a high electromigration resistance. The better Cu wettability of Ru compared to Ta can be explained by the concept of lattice misfit. A Ru(002) plane has lower lattice misfit, which suggests lower interface energy, and enhanced the adhesion of Cu onto Ru. However, the Ru film showed poor Cu diffusion barrier properties, which suggests Ru should be used as a glue layer in combination with another barrier layer.

Journal ArticleDOI
TL;DR: In this article, the potential influence of vertical salinity stratification on the heat buildup and thus on El Nino was considered using sea level observations and coupled models, which revealed the concomitant presence of heat accumulation and a significant barrier layer in the western equatorial Pacific.
Abstract: Several studies using sea level observations and coupled models have shown that heat buildup in the western equatorial Pacific is a necessary condition for a major El Nino to develop. However, none of these studies has considered the potential influence of the vertical salinity stratification on the heat buildup and thus on El Nino. In the warm pool, this stratification results in the presence of a barrier layer that controls the base of the ocean mixed layer. Analyses of in situ and TOPEX/Poseidon data, associated with indirect estimates of the vertical salinity stratification, reveal the concomitant presence of heat buildup and a significant barrier layer in the western equatorial Pacific. This relationship occurs during periods of about one year prior to the mature phase of El Nino events over the period 1993–2002. Analyses from a coupled ocean–atmosphere general circulation model suggest that this relationship is statistically robust. The ability of the coupled model to reproduce a realistic ...

Patent
31 Aug 2005
TL;DR: In this paper, a non-uniform aluminum concentration AlGaN-based cap layer has been provided for wide bandgap semiconductor devices and Graphitic BN passivation structures have been provided.
Abstract: High electron mobility transistors are provided that include a non-uniform aluminum concentration AlGaN based cap layer having a high aluminum concentration adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. High electron mobility transistors are provided that include a cap layer having a doped region adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. Graphitic BN passivation structures for wide bandgap semiconductor devices are provided. SiC passivation structures for Group III-nitride semiconductor devices are provided. Oxygen anneals of passivation structures are also provided. Ohmic contacts without a recess are also provided.

Patent
13 Oct 2005
TL;DR: In this article, a method for the production of a solar cell comprising a semiconductor substrate is described, where the electrical contact of which is achieved on the back face of the substrate is avoided by applying an etching barrier layer to the whole surface.
Abstract: A method for production of a solar cell (1), comprising a semiconductor substrate (2), is disclosed, the electrical contact of which is achieved on the back face of the semiconductor substrate. The back face of the semiconductor substrate comprises locally doped regions (3). The adjacent regions (4) have a different doping from said region (3). According to the invention, short-circuiting of the conducting material (5) of the solar cell may be avoided, whereby both regions (3,4), at least at the boundaries (6) thereof, are coated with a thin electrically-insulating layer (7). Both regions (3,4) are then coated over the whole surface thereof with an electrically-conducting material (5). The separation of the electrically-conducting layers (5) is achieved by application of an etching barrier layer (8) to the whole surface, which is then selectively removed without a mask, for example by laser ablation, locally above the insulating layer (7). By the subsequent attack of an etching solution the etching barrier layer (8) is locally removed from the conducting layer (5) in the region of the openings (9).

Patent
09 Feb 2005
TL;DR: In this paper, a high electron mobility transistor (HEMT) and methods of fabricating a HEMT are presented, which includes a high-level channel layer on a substrate, a barrier layer on the channel layer, an n-type nitride-based semiconductor material contact region on the barrier layer, a contact recess in the barrier layers that extends into the channel layers in the contact recess, an ohmic contact on the polysilicon contact region and a gate contact disposed on the gate contact adjacent the ohmic contacts.
Abstract: Transistor fabrication includes forming a nitride-based channel layer on a substrate, forming a barrier layer on the nitride-based channel layer, forming a contact recess in the barrier layer to expose a contact region of the nitride-based channel layer, forming a contact layer on the exposed contact region of the nitride-based channel layer, for example, using a low temperature deposition process, forming an ohmic contact on the contact layer and forming a gate contact disposed on the barrier layer adjacent the ohmic contact. A high electron mobility transistor (HEMT) and methods of fabricating a HEMT are also provided. The HEMT includes a nitride-based channel layer on a substrate, a barrier layer on the nitride-based channel layer, a contact recess in the barrier layer that extends into the channel layer, an n-type nitride-based semiconductor material contact region on the nitride-based channel layer in the contact recess, an ohmic contact on the nitride-based contact region and a gate contact disposed on the barrier layer adjacent the ohmic contact. The n-type nitride-based semiconductor material contact region and the nitride-based channel layer include a surface area enlargement structure.

Patent
05 Dec 2005
TL;DR: In this article, an improved nitride-based light emitting heterostructure is provided, which includes an electron supply layer and a hole supply layer with a light generating structure disposed there between.
Abstract: An improved nitride-based light emitting heterostructure is provided. The nitride-based light emitting heterostructure includes an electron supply layer and a hole supply layer with a light generating structure disposed there between. The light generating structure includes a set of barrier layers, each of which has a graded composition and a set of quantum wells, each of which adjoins at least one barrier layer. Additional features, such as a thickness of each quantum well, can be selected/incorporated into the heterostructure to improve one or more of its characteristics. Further, one or more additional layers that include a graded composition can be included in the heterostructure outside of the light generating structure. The graded composition layer(s) cause electrons to lose energy prior to entering a quantum well in the light generating structure, which enables the electrons to recombine with holes more efficiently in the quantum well.

Patent
06 Jan 2005
TL;DR: In this article, the authors proposed a layered structure, including a plurality of pairs of layers, each pair including a physical configuration layer and a barrier layer with low gas-transmission rates, may be used in reducing gas transmission rate to beyond currently detectable levels.
Abstract: A system provides an environmental barrier also useful for providing a circuit, for example, one having a thin-film battery such as one that includes lithium or lithium compounds connected to an electronic circuit. An environmental barrier is deposited as alternating layers, at least one of the layers providing a smoothing, planarizing, and/or leveling physical-configuration function, and at least one other layer providing a diffusion-barrier function. The layer providing the physical-configuration function may include a photoresist, a photodefinable, an energy-definable, and/or a maskable layer. The physical-configuration layer may also be a dielectric. A layered structure, including a plurality of pairs of layers, each pair including a physical configuration layer and a barrier layer with low gas-transmission rates, may be used in reducing gas transmission rate to beyond currently detectable levels.

Journal ArticleDOI
TL;DR: It is demonstrated that the impurity-assisted IEC becomes antiferromagnetic if the energy of the impurities states matches the Fermi energy and that the coupling strength decreases with temperature.
Abstract: Localized impurity or defect states in the insulating barrier layer separating two ferromagnetic films affect dramatically the interlayer exchange coupling (IEC), making it significantly stronger compared to perfect barriers. We demonstrate that the impurity-assisted IEC becomes antiferromagnetic if the energy of the impurity states matches the Fermi energy and that the coupling strength decreases with temperature. These results explain available experimental data on the IEC across tunnel barriers.

Patent
30 Dec 2005
TL;DR: In this article, a barrier layer between a well of the substrate and a channel region was proposed to separate the source and drain regions of the well from the channels of the channel.
Abstract: A method including forming a channel region between source and drain regions in a substrate, the channel region including a first dopant profile; and forming a barrier layer between the channel region and a well of the substrate, the barrier layer including a second dopant profile different from the first dopant profile. An apparatus including a gate electrode on a substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region, the barrier layer including a dopant profile different than a dopant profile of the channel region and different than a dopant profile of the well. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices formed in a substrate, each of the plurality of transistor devices including a gate electrode on the substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region.

Patent
22 Apr 2005
TL;DR: By performing a wet chemical process after etching a via, contaminations may be removed and a thin passivation layer may be formed that may then be readily removed in a subsequent sputter etch process for forming a barrier/adhesion layer as discussed by the authors.
Abstract: By performing a wet chemical process after etching a via, contaminations may be removed and a thin passivation layer may be formed that may then be readily removed in a subsequent sputter etch process for forming a barrier/adhesion layer. In a particular embodiment, the wet chemical process may be performed on the basis of fluoric acid and triazole or a compound thereof.

Journal ArticleDOI
TL;DR: In this article, the isothermal, mixed layer, and barrier layer in the southeastern tropical Indian Ocean were investigated using historical hydrographic and recent Argo-float profile data.
Abstract: [1] The isothermal layer, mixed layer, and barrier layer in the southeastern tropical Indian Ocean are investigated using historical hydrographic and recent Argo-float profile data. The annual average isothermal and mixed layers are deep (>50 m) near the equator, but they do not have the same topographic structure. The mixed layer is more orientated along the coastline owing to the effect of precipitation and runoff. This forms a thick barrier layer (>25 m) to the west of Sumatra. The thickness decreases to 10 m near eastern Java and less farther to the east and south. The seasonal variation of barrier layer along the equator and off Sumatra/Java is a consequence of interplay between annual and semiannual variations. Surface water convergence, wave propagation, and precipitation are essentially responsible for these variations. Annual (1 cpy) variation is dominant in most of the region studied except for two locations where semiannual variation is also large. The semiannual variation in isothermal depth (ID), mixed layer depth (MLD), and barrier layer thickness (BLT) is most evident along the equator, with a comparable strength to the annual variation. The other region of large semiannual variation in ID and MLD is off Northwest Australia, but no significant variation in BLT is observed there.

Patent
11 Aug 2005
TL;DR: In this article, a quantum-dot infrared photodetector comprises a semiconductor substrate, a buffer layer, an undoped first obstructing layer formed on the buffer layer and a doped second contact layer.
Abstract: A quantum-dot infrared photodetector comprises a semiconductor substrate; a buffer layer formed on the semiconductor substrate; an undoped first obstructing layer formed on the buffer layer; a first quantum-dot layer formed on the first barrier layer; a heavily doped first contact layer formed on the first quantum-dot layer; a second quantum-dot layer formed on the first contact layer; an undoped second obstructing layer formed on the second quantum-dot layer; and a doped second contact layer formed on the second quantum-dot layer. In another embodiment, the first obstructing layer and the second obstructing layer may be formed optionally. The quantum-dot photodetector may increase photo current and constrict dark current such that detectability is improved and the operation temperature can be increased.

Patent
16 Dec 2005
TL;DR: In this article, a method for forming a semiconductor device (100) is described, which consists of a substrate having a first region, a gate dielectric, a conductive metal oxide, and a capping layer.
Abstract: A method for forming a semiconductor device (100) includes a semiconductor substrate having a first region (104), forming a gate dielectric (108) over the first region, forming a conductive metal oxide (110) over the gate dielectric, forming an oxidation resistant barrier layer (111) over the conductive metal oxide, and forming a capping layer (116) over the oxidation resistant barrier layer. In one embodiment, the conductive metal oxide is IrO2, MoO2, and RuO2, and the oxidation resistant barrier layer includes TiN.

Patent
Adam William Saxler1
29 Apr 2005
TL;DR: In this paper, the binary Group III-nitride high electron mobility transistors (HEMTs) and methods of fabricating binary GIII-NITR HEMTs are provided.
Abstract: Binary Group III-nitride high electron mobility transistors (HEMTs) and methods of fabricating binary Group III-nitride HEMTs are provided. In some embodiments, the binary Group III-nitride HEMTs include a first binary Group III-nitride barrier layer, a binary Group III-nitride channel layer on the first barrier layer; and a second binary Group III-nitride barrier layer on the channel layer. In some embodiments, the binary Group III-nitride HEMTs include a first AIN barrier layer, a GaN channel layer and a second AIN barrier layer.