Showing papers on "Barrier layer published in 2008"

42.1: Invited Paper: Improved Amorphous In‐Ga‐Zn‐O TFTs

Abstract: We review the features of amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs), as well as circuit operation based on these TFTs. We also report a novel TFT structure which improves environmental stability of the TFT operation by taking full advantage of the a-IGZO properties, where a conventional PECVD a-SiNX:H films serve not only as an effective barrier layer but also as a hydrogen source to form the coplanar source and drain.

Barrier material and process for Cu interconnect

Abstract: A semiconductor diffusion barrier layer and its method of manufacture is described. The barrier layer includes of at least one layer of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinations thereof. The barrier layer may further include a metal rich surface. Embodiments preferably include a glue layer about 10 to 500 Angstroms thick, the glue layer consisting of Ru, Ta, Ti, W, Co, Ni, Al, Nb, AlCu, and a metal-rich nitride, and combinations thereof. The ratio of the glue layer thickness to the barrier layer thickness is preferably about 1 to 50. Other alternative preferred embodiments further include a conductor annealing step. The various layers may be deposited using PVD, CVD, PECVD, PEALD and/or ALD methods including nitridation and silicidation methods.

Tunnel Magnetoresistance Over 100% in MgO-Based Magnetic Tunnel Junction Films With Perpendicular Magnetic L1 $_{0}$ -FePt Electrodes

Abstract: Perpendicular L10-FePt/MgO/Fe/L10 -FePt magnetic tunnel junction (MTJ) films with the (001) texture were successfully developed to obtain a large tunnel magnetoresistance (TMR) above 100 % at room temperature. The TMR ratio in the L10-FePt/MgO/Fe/L10-FePt MTJ was strongly dependent on the Fe interfacial layer thickness. The lattice mismatch between the MgO(001) barrier layer and the L10 -FePt(001) layer is too large for the MgO barrier layer to grow epitaxially on the L10-FePt(001) layer. The insertion of the Fe interfacial layer improves the quality of the MgO(001) barrier layer and achieves an epitaxy in the L10-FePt/MgO/Fe/L10-FePt stack. As a result, the optimization of the Fe interfacial layer thickness is a key to obtain the large TMR ratio in the MgO-based MTJ with the L10-FePt electrodes.

Method and system for providing a magnetoresistive structure

Abstract: A method and system for providing a magnetoresistive structure are described. The magnetoresistive structure includes a first electrode, an insertion layer, a crystalline tunneling barrier layer, and a second electrode. The first electrode includes at least a first magnetic material and boron. The crystalline tunneling barrier layer includes at least one constituent. The insertion layer has a first boron affinity. The at least one constituent of the crystalline tunneling barrier layer has at least a second boron affinity that is less than the first boron affinity. The second electrode includes at least a second magnetic material.

Method of forming trench isolation structures and semiconductor device produced thereby

Abstract: A method for forming a trench isolation structure and a semiconductor device are provided. The method comprises the following steps: forming a patterned mask on a semiconductor substrate; defining a trench with a predetermined depth D by using the patterned mask, wherein the trench has a bottom and a side wall; forming a liner layer covering the bottom and the side wall of the trench; substantially filling the trench with a flowable oxide from the bottom to a thickness d1 to form an oxide layer; forming a barrier layer with a thickness d′ to cover and completely seal the surface of the oxide layer, wherein d′

Integrated circuit and manufacturing method of copper germanide and copper silicide as copper capping layer

Abstract: A method is provided for forming a capping layer comprising Cu, N, and also Si and/or Ge onto a copper conductive structure, said method comprising the sequential steps of: forming, at a temperature range between 200° C. up to 400° C., at least one capping layer onto said copper conductive structure by exposing said structure to a GeH 4 and/or a SiH 4 comprising ambient, performing a NH 3 plasma treatment thereby forming an at least partly nitrided capping layer, forming a dielectric barrier layer onto said at least partly nitrided capping layer, wherein prior to said step of forming said at least one capping layer a pre-annealing step of said copper conductive structure is performed at a temperature range between 250° C. up to 450° C.

Organic electroluminescent device

Abstract: An organic electroluminescent device. The organic electroluminescent device comprises a first barrier layer disposed on a substrate; organic electroluminescent elements disposed over the first barrier layer and encapsulated with a second barrier layer; and a getter layer disposed between the first and second barrier layers. Each of the first and second barrier layers includes an organic layer and an inorganic layer covering the top and sidewall surfaces of the organic layer, thus providing stacked inorganic sidewalls to hinder moisture and oxygen.

Nitride semiconductor device, doherty amplifier and drain voltage controlled amplifier

Abstract: A nitride semiconductor device includes a substrate, a stacked semiconductor structure formed over the substrate and including a electron channel layer of an undoped nitride semiconductor and an electron supplying layer of an n-type nitride semiconductor formed epitaxially over the electron channel layer, the n-type nitride semiconductor having an electron affinity smaller than an electron affinity of said undoped nitride semiconductor and a two-dimensional electron gas being formed in the electron channel layer along an interface to the electron supply layer, a gate electrode formed over the stacked semiconductor structure in correspondence to a channel region, and source and drain electrodes formed over the stacked semiconductor structure in ohmic contact therewith respectively at a first side and a second side of the gate electrode, the stacked semiconductor structure including, between the substrate and the electron channel layer, an n-type conductive layer and a barrier layer containing Al formed consecutively and epitaxially.

Tracer Investigation of Pore Formation in Anodic Titania

Abstract: Using a sputtering-deposited titanium substrate, incorporating six equally spaced nanolayers of Ti-W alloy, the volume and composition changes accompanying the formation of porous anodic films on titanium in 0.5 wt % NH 4 F in glycerol are investigated. The findings reveal amorphous films with nanotubes of TiO 2 , containing fluoride ions and possibly glycerol derivatives. Tungsten and titanium species are lost to the electrolyte at differing rates during anodizing, leading to an enrichment of tungsten in the film relative to the composition of the substrate. The spacing of tungsten-containing bands in the film is ∼2.3 that of the original alloy layers during growth of the major pores. The generation of the nanotubes can be explained either by field-assisted flow of film material within the barrier layer to the pore walls, with cation and anion transport numbers of anodic titania in the barrier layer region similar to those of barrier films and with field-assisted ejection of Ti 4+ ions to the electrolyte, or by field-assisted dissolution, but with a reduction in cation transport number.

Barrier-Layer Scaling of InAlN/GaN HEMTs

Abstract: We discuss the characteristics of high-electron mobility transistors with barrier thicknesses between 33 and 3 nm, which are grown on sapphire substrates by metal-organic chemical vapor deposition. The maximum drain current (at VG = 2.0 V) decreased with decreasing barrier thickness due to the gate forward drive limitation and residual surface-depletion effect. Full pinchoff and low leakage are observed. Even with 3-nm ultrathin barrier, the heterostructure and contacts are thermally highly stable (up to 1000degC).

Methods for depositing tungsten layers employing atomic layer deposition techniques

Abstract: In one embodiment of the invention, a method for forming a tungsten-containing layer on a substrate is provided which includes positioning a substrate containing a barrier layer disposed thereon in a process chamber, exposing the substrate to a first soak process for a first time period and depositing a nucleation layer on the barrier layer by flowing a tungsten-containing precursor and a reductant into the process chamber. The method further includes exposing the nucleation layer to a second soak process for a second time period and depositing a bulk layer on the nucleation layer. In one example, the barrier layer contains titanium nitride, the first and second soak processes independently comprise at least one reducing gas selected from the group consisting of hydrogen, silane, disilane, dichlorosilane, borane, diborane, derivatives thereof and combinations thereof and the nucleation layer may be deposited by an atomic layer deposition process or a pulsed chemical vapor deposition process while the bulk layer may be deposited by a chemical vapor deposition process or a physical vapor deposition process.

Perpendicular magnetic tunnel junction with tunneling magnetoresistance ratio of 64% using MgO (100) barrier layer prepared at room temperature

Abstract: MgO (100) textured films can be prepared by reactive facing targets sputtering at room temperature without postdeposition annealing process when they were deposited on (100) oriented Fe buffer layers. This method allows fabrication of perpendicular magnetic tunnel junction (p-MTJ) with MgO (100) tunneling barrier layer and rare-earth transition metal (RE-TM) alloy thin films as perpendicularly magnetized free and pinned layers. The 3-nm-thick MgO tunneling barrier layer in p-MTJ multilayer prepared on glass substrate revealed (100) crystalline orientation. Extraordinary Hall effect measurement clarified that the perpendicular magnetic components of 3-nm-thick Fe buffer layers on the two ends of MgO tunneling barrier layer were increased by exchange coupling with RE-TM alloy layers. The RA of 35kΩμm2 and tunneling magnetoresistance ratio of 64% was observed in the multilayered p-MTJ element by current-in-plane-tunneling.

A General Method for the Anodic Formation of Crystalline Metal Oxide Nanotube Arrays without the Use of Thermal Annealing

Abstract: Valve metal oxides are versatile in their range of applications, which include high-K dielectrics, gas sensing, biomedical implants, field emitters, and photovoltaic cells. It is now generally recognized that nanoscale control of metal oxide architectures permits significant enhancement of the properties utilized in the above applications. In particular, TiO2 nanotube arrays formed by anodization have demonstrated outstanding performance in gas sensing, photocatalytic, and photovoltaic applications. Review papers on the subject are available. To date, amorphous nanotube arrays have been synthesized by Ti anodization with an elevated-temperature heat treatment, with temperatures typically greater than 350 8C being required to induce crystallinity. With regard to photoelectrochemical water splitting using thick-film Ti foil samples, annealing at temperatures sufficient to induce crystallinity usually leads to the formation of a thick barrier layer, separating the nanotube-array film from the underlying metal substrate, where recombination losses can occur. This barrier layer acts to hinder electron transfer to themetal electrode (cathode) where water reduction takes place, in turn reducing the overall water-splitting efficiency. The need for high-temperature crystallization limits nanotube array use with temperaturesensitive materials, such as polymers, for applications such as photocatalytic membranes. Therefore, low-temperature synthetic routes, where a high-temperature annealing step for crystallization is not required, are needed to obtain the full

Three-dimensional atom probe analysis of green- and blue-emitting InxGa1−xN∕GaN multiple quantum well structures

Abstract: The three-dimensional atom probe has been used to characterize green- and blue-emitting InxGa1−xN∕GaN multiple quantum well structures with subnanometer resolution over a 100nm field of view. The distribution of indium in InxGa1−xN samples with different compositions is analyzed. No evidence is found wherein the indium distribution deviates from that of a random alloy, which appears to preclude indium clustering as the cause of the reported carrier localization in these structures. The upper interface of each quantum well layer is shown to be rougher and more diffuse than the lower interface, and the existence of monolayer steps in the upper interfaces is revealed. These steps could effectively localize carriers at room temperature. Indium is shown to be present in the GaN barrier layers despite the absence of indium precursor flux during barrier layer growth. A strong evidence is produced to support a mechanism for the presence of indium in these layers, namely, that a layer of indium forms on the surfac...

Method of fabricating flexible display device

Abstract: A method of fabricating a flexible display device, the method including applying a transparent adhesive layer on a carrier substrate, laminating a flexible substrate comprising a barrier layer on the transparent adhesive layer, forming a thin film transistor array on the flexible substrate, and separating the carrier substrate from the flexible substrate by irradiating a laser beam onto the barrier layer.

Interconnections for flip-chip using lead-free solders and having reaction barrier layers

Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

Passivation of wide band-gap based semiconductor devices with hydrogen-free sputtered nitrides

Abstract: A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and the thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on the thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on the first layer for positioning subsequent passivation layers further from the substrate without encapsulating the structure; a sputtered stoichiometric silicon nitride layer on the second sputtered layer for encapsulating the structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on the encapsulant layer.

Undercut-free blm process for pb-free and pb-reduced c4

Abstract: A system and method for eliminating undercut when forming a C4 solder bump for BLM (Ball Limiting Metallurgy) and improving the C4 pitch. In the process, a barrier layer metal stack is deposited above a metal pad layer. A top layer of the barrier layer metals (e.g., Cu) is patterned by CMP with a bottom conductive layer of the barrier metal stack removed by etching. The diffusion barrier and C4 solder bump may be formed by electroless plating, in one embodiment, using a maskless technique, or by an electroplating techniques using a patterned mask. This allows the pitch of the C4 solder bumps to be reduced.

Low resistance high-TMR magnetic tunnel junction and process for fabrication thereof

Abstract: One embodiment of the present invention includes a non-volatile magnetic memory element including a fixed layer, a barrier layer formed on top of the fixed layer, and a free layer formed on top of the barrier layer, wherein the electrical resistivity of the barrier layer is reduced by placing said barrier layer under compressive stress. Compressive stress is induced by either using a compressive stress inducing layer, or by using inert gases at low pressure during the sputtering process as the barrier layer is deposited, or by introducing compressive stress inducing molecules into the molecular lattice of the barrier layer.

Field effect transistor

Abstract: PROBLEM TO BE SOLVED: To provide an MOS transistor of high soft error resistance. SOLUTION: A barrier layer 7 comprising an impurity region of the same conductive type as source-drain regions 4 and 5 is provided, just under the source-drain regions 4 and 5 of transistor 10, 20 formation region subject to element separation by an STI2 comprising an embedded insulating film. The barrier layer 7 is so provided at the position shallower than the STI2 so that its periphery contacts to the side surface of the embedded insulating film 2. Since the perimeter and bottom surface of the transistor 10, 20 formation region are surrounded with the STI2 and the barrier layer 7, effects to adjacent elements voltage fluctuation of the transistor 10, 20 formation region on an adjoining element when α ray enters are suppressed. The upper surface of the barrier layer 7 acts as a barrier wall against a positive hole or electron and prohibits transmission of the positive hole or electron generated deeper than the impurity region 7, reducing noises at entering of α ray. COPYRIGHT: (C)2009,JPO&INPIT

Colossal internal barrier layer capacitance effect in polycrystalline copper (II) oxide

Abstract: Dielectric spectroscopy analysis of the high permittivity (κ∼104) copper (II) oxide (CuO) ceramic shows that the grain contribution plays a major role for the giant-κ value at low temperature, whereas grain boundary (GB) contribution dominates around room temperature and above. Moreover, impedance spectroscopy analysis reveals electrically heterogeneous microstructure in CuO consisting of semiconducting grains and insulating GBs. Finally, the giant dielectric phenomenon exhibited by CuO is attributed to the internal barrier layer (due to GB) capacitance mechanism.

The electrochemical behaviour of Ti-13Nb-13Zr alloy in various solutions

Abstract: The electrochemical behaviour of a near-/3 Ti-13Nb-13Zr alloy for the application as implants was investigated in various solutions. The electrolytes used were 0.9 wt% NaCI solution, Hanks' solution and a culture medium known as minimum essential medium (MEM) composed of salts, vitamins and amino acids, all at 37°C. The electrochemical behaviour was investigated by the following electrochemical techniques: open circuit potential measurements as a function of time, electrochemical impedance spectroscopy (EIS) and determination of polarisation curves. The obtained results showed that the Ti alloy was passive in all electrolytes. The EIS results were analysed using an equivalent electrical circuit representing a duplex structure oxide layer, composed of an inner barrier layer, mainly responsible for the alloy corrosion resistance, and an outer and porous layer that has been associated to osteointegration ability. The properties of both layers were dependent on the electrolyte used. The results suggested that the thickest porous layer is formed in the MEM solution whereas the impedance of the barrier layer formed in this solution was the lowest among the electrolytes used. The polarisation curves showed a current increase at potentials around 1300 mV versus saturated calomel electrode (SCE), and this increase was also dependent on the electrolyte used. The highest increase in current density was also associated to the MEM solution suggesting that this is the most aggressive electrolyte to the Ti alloy among the three tested solutions.

Cobalt deposition on barrier surfaces

Abstract: Embodiments of the invention provide processes for depositing a cobalt layer on a barrier layer and subsequently depositing a conductive material, such as copper or a copper alloy, thereon. In one embodiment, a method for depositing materials on a substrate surface is provided which includes forming a barrier layer on a substrate, exposing the substrate to dicobalt hexacarbonyl butylacetylene (CCTBA) and hydrogen to form a cobalt layer on the barrier layer during a vapor deposition process (e.g., CVD or ALD), and depositing a conductive material over the cobalt layer. In some examples, the barrier layer and/or the cobalt layer may be exposed to a gas or a reagent during a treatment process, such as a thermal process, an in situ plasma process, or a remote plasma process.

Method of MRAM fabrication with zero electrical shorting

Abstract: An MTJ cell without footings and free from electrical short-circuits across a tunneling barrier layer is formed by using a Ta hard mask layer and a combination of etches. A first etch patterns the Ta hard mask, while a second etch uses O 2 applied in a single high power process at two successive different power levels. A first power level of between approximately 200 W and 500 W removes BARC, photoresist and Ta residue from the first etch, the second power level, between approximately 400 W and 600 W continues an etch of the stack layers and forms a protective oxide around the etched sides of the stack. Finally, an etch using a carbon, hydrogen and oxygen gas completes the etch while the oxide layer protects the cell from short-circuits across the lateral edges of the barrier layer.

Novel Silicon-Carbon (Si:C) Schottky Barrier Enhancement Layer for Dark-Current Suppression in Ge-on-SOI MSM Photodetectors

Abstract: This letter reports the first demonstration of an evanescent coupled germanium-on-silicon-on-insulator (Ge-on-SOI) metal-semiconductor-metal (MSM) photodetector with a novel silicon-carbon (Si:C) Schottky barrier enhancement layer. Through the insertion of a Si:C barrier layer between the metal/Ge interface, the hole Schottky barrier height phibh can effectively be enhanced to ~0.52 eV above the valence band edge. As a result, significant dark-current IDark suppression by more than four orders of magnitude was demonstrated, leading to an impressive IDark of ~11.5 nA for an applied bias VA of 1.0 V. Optical measurements performed at a photon wavelength of 1550 nm revealed the achievement of good internal responsivity and quantum efficiency of ~530 mA/W and 42.4%, respectively, making such a high-performance Ge-on-SOI MSM photodetector a promising option for optical communication applications.