Showing papers on "Barrier layer published in 2009"

Characterization of AC PEO coatings on magnesium alloys

Abstract: Optical emission spectroscopy, fast video imaging and coating characterization are employed to investigate AC plasma electrolytic oxidation (PEO) of magnesium alloys The findings revealed initiation and gradual increase in the number of discharges after 2–4 ms of each anodic pulse once a critical voltage was reached No discharges were observed during the cathodic half-cycles The lifetimes of discharges were in the range of 005–4 ms A transition in the voltage-time response, accompanied by a change in the acoustic and optical emission characteristics of discharges, was associated with the development of an intermediate coating layer with an average hardness of 270–450 HV 005 The coatings grew at a rate in the range 40–75 µm min − 1 , depending on the substrate composition Regardless of the substrate, the coatings consisted of MgO and Mg 2 SiO 4 , with incorporation of alloying element species Electrolyte species were mainly present in a more porous layer at the coating surface, constituting 20–40% of the coating thickness A thin barrier layer consisting of polycrystalline MgO was located next to the alloy The corrosion rate of the magnesium alloys determined using potentiodynamic polarization in 35 wt% NaCl was reduced by 2–4 orders of magnitude by the PEO treatment

Origin(s) of the apparent high permittivity in CaCu3Ti4O12 ceramics: clarification on the contributions from internal barrier layer capacitor and sample-electrode contact effects

Abstract: CaCu3Ti4O12 ceramics with a range of resistivities have been prepared using both conventional sintering and spark plasma sintering. For all cases, the high effective permittivity is associated primarily with an internal barrier layer capacitor mechanism. Additional polarization associated with the electrode-sample interface may appear but its visibility depends on the grain boundary resistivity (Rgb) of the ceramic. If the Rgb is large, the electrode polarization is obscured by sample-related effects; if the Rgb is small, a separate impedance associated with the electrode polarization may be seen. Discrepancies in the literature regarding the magnitude and origin of the high effective permittivity are attributed to a combination of differences in processing conditions, electrode contact material and measuring frequency range.

Method and system for fabricating magnetic transducers with improved pinning

Abstract: A method and system for providing a magnetic transducer are disclosed. The method and system include providing a magnetic element that includes a free layer, a pinned layer, and a nonmagnetic spacer layer between the free layer and the pinned layer. The nonmagnetic spacer layer is a tunneling barrier layer. The free layer is configured to be biased in a first direction. The pinned layer has a pinned layer magnetization configured to be pinned in a second direction that is at a first angle from perpendicular to the ABS. The first angle is nonzero and different from ninety degrees. The second direction and the first direction form a second angle that is different from ninety degrees.

Magnetoresistive sensors having an improved free layer

Abstract: A magnetoresistive sensor having a novel free layer and a method of producing the same are disclosed. The magnetoresistive sensor comprises a pinned layer, a barrier layer disposed over the pinned layer, and a free layer disposed over the barrier layer. The free layer comprises a first magnetic layer disposed over the barrier layer. The first magnetic layer has a positive spin polarization, a positive magnetostriction, and a polycrystalline structure. The free layer further comprises a second magnetic layer disposed over the first magnetic layer. The second magnetic layer has a negative magnetostriction and comprises at least cobalt (Co) and boron (B).

TMR read head structures with differential stripe heights

Abstract: A tunneling magnetoresistance (TMR) read head and a method of producing the same are disclosed. A free layer having a free layer stripe height is provided, the free layer having a first side and a second side. A tunneling barrier layer is formed adjacent to the first side of the free layer, the tunneling barrier layer having a first side and a second side, the second side of the tunneling barrier layer facing the first side of the free layer. A pinned stack is formed adjacent to the first side of the tunneling barrier layer. The pinned stack comprises at least one magnetic layer having a current path stripe height that is less than the free layer stripe height.

Method for providing a magnetic recording transducer

Abstract: A method for providing a magnetic recording transducer is described. The method includes providing a pinned layer for a magnetic element. In one aspect, a portion of a tunneling barrier layer for the magnetic element is provided. The magnetic recording transducer annealed is after the portion of the tunneling barrier layer is provided. The annealing is at a temperature higher than room temperature. A remaining portion of the tunneling barrier layer is provided after the annealing. In another aspect, the magnetic transducer is transferred to a high vacuum annealing apparatus before annealing the magnetic transducer. In this aspect, the magnetic transducer may be annealed before any portion of the tunneling barrier is provided or after at least a portion of the tunneling barrier is provided. The annealing is performed in the high vacuum annealing apparatus. A free layer for the magnetic element is also provided.

Normally-off semiconductor devices and methods of fabricating the same

Abstract: Normally-off semiconductor devices are provided. A Group III-nitride buffer layer is provided. A Group III-nitride barrier layer is provided on the Group III-nitride buffer layer. A non-conducting spacer layer is provided on the Group III-nitride barrier layer. The Group III-nitride barrier layer and the spacer layer are etched to form a trench. The trench extends through the barrier layer and exposes a portion of the buffer layer. A dielectric layer is formed on the spacer layer and in the trench and a gate electrode is formed on the dielectric layer. Related methods of forming semiconductor devices are also provided herein.

Tunneling electroresistance in ferroelectric tunnel junctions with a composite barrier

Abstract: Tunneling electroresistance (TER) effect is the change in the electrical resistance of a ferroelectric tunnel junction (FTJ) associated with polarization reversal in the ferroelectric barrier layer. Here we predict that a FTJ with a composite barrier that combines a functional ferroelectric film and a thin layer of a nonpolar dielectric can exhibit a significantly enhanced TER. Due to the change in the electrostatic potential with polarization reversal, the nonpolar dielectric barrier acts as a switch that changes its barrier height from a low to high value. The predicted values of TER are giant and indicate that the resistance of the FTJ can be changed by several orders in magnitude at the coercive electric field of ferroelectric.

Non volatile memory device ion barrier

Abstract: An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile.

Method for manufacturing transistor

Abstract: A hydrogen barrier layer is selectively provided over an oxide semiconductor layer including hydrogen and hydrogen is selectively desorbed from a given region in the oxide semiconductor layer by conducting oxidation treatment, so that regions with different conductivities are formed in the oxide semiconductor layer. After that, a channel formation region, a source region, and a drain region can be formed with the use of the regions with different conductivities formed in the oxide semiconductor layer.

Impact of Barrier Layer Thickness on SST in the Central Tropical North Atlantic

Abstract: Measurements from three long-term moored buoys are used to investigate the impact of barrier layer thickness (BLT) on the seasonal cycle of sea surface temperature (SST) in the central tropical North Atlantic Ocean. It is found that seasonal variations of the BLT exert a considerable influence on SST through their modulation of the vertical heatflux at the base of the mixed layer, estimated as the residual in the mixed layer heat balance. Cooling associated with this term is strongest when the barrier layer is thin and the vertical temperature gradient at the base of the mixed layer is strong. Conversely, thick barrier layers are associated with a significant reduction in the vertical temperature gradient at the base of the mixed layer, which suppresses the upward transfer of cooler water into the mixed layer. Forced ocean and coupled ocean‐ atmosphere models that do not properly simulate the barrier layer may have difficulty reproducing the observed seasonal cycle of SST in the tropical North Atlantic.

Westward propagation of barrier layer formation in the 2006–07 Rossby wave event over the tropical southwest Indian Ocean

Abstract: [1] A suite of satellite and in-situ observations are used to study ocean-atmospheric conditions over the tropical Southwest Indian Ocean (SWIO) during 2006–2007 when El Nino and an Indian Ocean dipole took place simultaneously. Argo profiles reveal a pronounced up-westward propagation of subsurface warming in the southern tropical Indian Ocean associated with Rossby waves traveling on the sloping thermocline. With the thermocline deepening by 60 m, a thick barrier layer forms and propagates with the Rossby wave, potentially contributing to the mixed layer warming.

Spin-Transfer Switching Magnetic Element Utilizing a Composite Free Layer Comprising a Superparamagnetic Layer

Abstract: A system and method for forming a magnetic tunnel junction (MTJ) storage element utilizes a composite free layer structure. The MTJ element includes a stack comprising a pinned layer, a barrier layer, and a composite free layer. The composite free layer includes a first free layer, a superparamagnetic layer and a nonmagnetic spacer layer interspersed between the first free layer and the superparamagnetic layer. A thickness of the spacer layer controls a manner of magnetic coupling between the first free layer and the superparamagnetic layer.

Method for Producing an Electronic Component and Electronic Component

Abstract: The invention relates to a method for producing an electronic component that comprises barrier layers for encapsulating the component, comprising the following steps: making available a substrate (1) having at least one functional layer (22), applying at least one first barrier layer (3) to the functional layer (22) by way of plasma-less atomic layer deposition (PLALD) and applying at least one second barrier layer (4) to the functional layer (22) by way of plasma-enhanced chemical vapor deposition (PECVD).

Driver circuit and semiconductor device

Abstract: The silicon nitride layer 910 formed by plasma CVD using a gas containing a hydrogen compound such as silane (SiH4) and ammonia (NH3) is provided on and in direct contact with the oxide semiconductor layer 905 used for the resistor 354, and the silicon nitride layer 910 is provided over the oxide semiconductor layer 906 used for the thin film transistor 355 with the silicon oxide layer 909 serving as a barrier layer interposed therebetween. Therefore, a higher concentration of hydrogen is introduced into the oxide semiconductor layer 905 than into the oxide semiconductor layer 906. As a result, the resistance of the oxide semiconductor layer 905 used for the resistor 354 is made lower than that of the oxide semiconductor layer 906 used for the thin film transistor 355.

Method of fabricating the trench isolation layer for semiconductor device

Abstract: A method for fabricating an NBO(nitride barrier oxide)-trench isolation layer for a semiconductor device is provided to improve leakage current characteristic by making a nitride barrier layer pattern function as a barrier in forming a filed oxide layer so that a portion for the field oxide layer can be confined restrictively. A first trench(131) is formed in an interface between an isolation region(101) and an active region(102) of a semiconductor substrate(100), having a width of 20~60 nanometers and a depth of 200-350 nanometers. A buffer oxide layer(140) is formed on the front surface of the substrate having the first trench. A nitride barrier layer is formed on the buffer oxide layer to fill the first trench. The nitride barrier layer is patterned to form a nitride barrier layer pattern(151) that exposes a partial surface of the isolation region surrounded by the first trench. The isolation region exposed by the nitride barrier layer pattern is removed by a predetermined thickness to form a second trench. An oxide process is performed on the substrate in the periphery of the second trench to form a field oxide layer(160). The nitride barrier layer pattern on the surface of the substrate is removed.

A simple approach for synthesis of TiO2 nanotubes with through‐hole morphology

Abstract: The present work reports a simple approach for fabrication of self-standing titania (TiO2) nanotube membranes with through-hole morphology. The method is hydrofluoric acid free and the pore opening of TiO2 nanotubes is performed by electrochemical thinning of the oxide barrier layer. A reduction of anodization voltage was applied at the end of the anodization process to cause a successful removal of the remaining barrier layer from the TiO2 nanotubes during their detachment from the underlying titanium substrate. (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Barrier film and laminated material, container for wrapping and image display medium using the same, and manufacturing method for barrier film

Abstract: An object of the present invention is to provide a barrier film having the extremely high barrier property and the better transparency, a method for manufacturing the same, and a laminated material, a container for wrapping and an image displaying medium using the barrier film. According to the present invention, there is provided a barrier film provided with a barrier layer on at least one surface of a substrate film, wherein the barrier layer is a silicon oxide film having an atomic ratio in a range of Si:O:C=100:140 to 170:20 to 40, peak position of infrared-ray absorption due to Si—O—Si stretching vibration between 1060 to 1090 cm−1, a film density in a range of 2.6 to 2.8 g/cm3, and a distance between grains of 30 nm or shorter. Still more, there is provided a barrier film provided with a barrier layer on at least one surface of a substrate film, has a composition wherein the barrier layer is a silicon oxi-nitride film, and the silicon oxi-nitride film has an atomic ratio in a range of Si:O:N:C=100:60 to 90:60 to 90:20 to 40, a maximum peak of infrared-ray absorption due to Si—O stretching vibration and Si—N stretching vibration is in a range of 820 to 930 cm−1, a film density is in a range of 2.9 to 3.2 g/cm3, and a distance between grains is 30 nm or shorter.

Non-volatile resistive sense memory

Abstract: A resistive sense memory cell includes a layer of crystalline praseodymium calcium manganese oxide and a layer of amorphous praseodymium calcium manganese oxide disposed on the layer of crystalline praseodymium calcium manganese oxide forming a resistive sense memory stack. A first and second electrode are separated by the resistive sense memory stack. The resistive sense memory cell can further include an oxygen diffusion barrier layer separating the layer of crystalline praseodymium calcium manganese oxide from the layer of amorphous praseodymium calcium manganese oxide a layer. Methods include depositing an amorphous praseodymium calcium manganese oxide disposed on the layer of crystalline praseodymium calcium manganese oxide forming a resistive sense memory stack.

Nonvolatile semiconductor memory device and method for manufacturing the same

Abstract: PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device and a method for manufacturing the same equipped with a resistance change type nonvolatile memory cell which reduces a leak current by preventing short between memory cells. SOLUTION: The nonvolatile semiconductor memory device has a first wiring layer 13 which is provided on a first insulating layer 11 and extended in a first direction, and a nonvolatile memory cell MC which is provided in a peeler shape on the first wiring layer 13 to include a non-ohmic element 18 and a variable resistance element 14 connected in series. A barrier layer 21 is provided on the memory cell MC and constituted of a single layer in an in-plane direction. A conductive layer 30 is provided on the barrier layer 21 and constituted of a single layer in an in-plane direction. A second insulating layer 20 is provided on the first insulating layer 11 to cover the side surfaces of the memory cell MC, the barrier layer 21, and the conductive layer 30. A second wiring layer 22 is provided on the conductive layer 30 and extended in a second direction. COPYRIGHT: (C)2010,JPO&INPIT

Communication cable with improved crosstalk attenuation

Abstract: The present invention relates to a barrier tape used as part of a communication cable to improve crosstalk attenuation. The barrier tape is provided with one or more barrier layers of discontinuous conductive segments. Conductive segments of one barrier layer are preferably sized and shaped to overlie gaps between conductive segments of another barrier layer.

Magnetic stack design

Abstract: A magnetic stack having a free layer having a switchable magnetization orientation, a reference layer having a pinned magnetization orientation, and a barrier layer therebetween. The stack includes an annular antiferromagnetic pinning layer electrically isolated from the free layer and in physical contact with the reference layer. In some embodiments, the reference layer is larger than the free layer.

Thin film sodium species barrier method and structure for cigs based thin film photovoltaic cell

Abstract: A method for fabricating a thin film solar cell includes providing a soda lime glass substrate comprising a surface region and a concentration of sodium oxide of greater than about 10 wt % and treating the surface region with one or more cleaning process, using a deionized water rinse, to remove surface contaminants having a particles size of greater than three microns. The method also includes forming a barrier layer overlying the surface region, forming a first molybdenum layer in tensile configuration overlying the barrier layer, and forming a second molybdenum layer in compressive configuration using a second process overlying the first molybdenum layer. Additionally, the method includes patterning the first molybdenum layer and the second molybdenum layer to form a lower electrode layer and forming a layer of photovoltaic material overlying the lower electrode layer. Moreover, the method includes forming a first zinc oxide layer overlying the layer of photovoltaic materials.