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Showing papers on "Barrier layer published in 2016"


Patent
Chih-Chien Chi1, Hung-Wen Su1
17 May 2016
TL;DR: In this article, a representative semiconductor device includes a first dielectric layer overlying a substrate, at least a first opening in the first layer, a conformal dense layer lining the at least first opening, a barrier layer overlaying the conformal layer, and a conductive feature in the second layer.
Abstract: A representative semiconductor device includes a first dielectric layer overlying a substrate, at least a first opening in the first dielectric layer, a conformal dense layer lining the at least first opening in the first dielectric layer, a barrier layer overlying the conformal dense layer, a conductive feature in the at least first opening, where a portion of the first dielectric layer between any two adjacent conductive features is removed to form a second opening, the second opening exposing the conformal dense layer between the two adjacent conductive features, and a second dielectric layer having an air gap formed therein, the second dielectric layer disposed between the two adjacent conductive features.

81 citations


Journal ArticleDOI
TL;DR: Anomalous decrease in effective damping parameter αeff in sputtered Ni81Fe19 (Py) thin films in contact with a very thin β-Ta layer without necessitating the flow of DC-current is observed, highlighting the potential of employing β- Ta based nanostructures in developing low power spintronic devices having tunable as well as low value of α.
Abstract: Anomalous decrease in effective damping parameter αeff in sputtered Ni81Fe19 (Py) thin films in contact with a very thin β-Ta layer without necessitating the flow of DC-current is observed. This reduction in αeff, which is also referred to as anti-damping effect, is found to be critically dependent on the thickness of β-Ta layer; αeff being highest, i.e., 0.0093 ± 0.0003 for bare Ni81Fe19(18 nm)/SiO2/Si compared to the smallest value of 0.0077 ± 0.0001 for β-Ta(6 nm)/Py(18 nm)/SiO2/Si. This anomalous anti-damping effect is understood in terms of interfacial Rashba effect associated with the formation of a thin protective Ta2O5 barrier layer and also the spin pumping induced non-equilibrium diffusive spin-accumulation effect in β-Ta layer near the Ta/Py interface which induces additional spin orbit torque (SOT) on the moments in Py leading to reduction in . The fitting of (tTa) revealed an anomalous negative interfacial spin mixing conductance, and spin diffusion length, . The increase in αeff observed above tTa = 6 nm is attributed to the weakening of SOT at higher tTa. The study highlights the potential of employing β-Ta based nanostructures in developing low power spintronic devices having tunable as well as low value of α.

50 citations


Journal ArticleDOI
TL;DR: In this paper, a SiC-p/microporous Ag composite structure was prepared by sintering a Ag microflake paste containing 2 wt% sub-micron SiCp under mild conditions (250 °C and 0.4 MPa for 30 min).
Abstract: This paper explores the possibility of using Ag paste containing silicon carbide particles (SiC-p) as a novel high-temperature die-attachment solution for the design of power devices. The bonding structure used in this research was composed of silicon dies and a direct bonded copper (DBC) substrate. A SiC-p/microporous Ag composite structure was prepared by sintering a Ag microflake paste containing 2 wt% sub-micron SiC-p under mild conditions (250 °C and 0.4 MPa for 30 min). In addition to the Ag paste, the surface metallization of the DBC substrate was also evaluated in this research. Ag metallization layers deposited by electroplating and sputtering were compared, along with samples also containing a titanium (Ti) diffusion barrier layer between Cu and Ag. The results indicated that the SiC-p-containing Ag sinter paste showed better stability in storage tests than the paste without SiC-p at the temperatures such as 150, 250 and 350 °C. Additionally, the Ti diffusion barrier layer played an active role in preventing the oxidation of Cu and inter-diffusion between Cu and Ag during use at high temperatures exceeding 250 °C. The joint bonded by SiC-p-containing Ag paste on DBC substrate with Ti barrier layer exhibited excellent stability up to 1000 h at 150 and 250 °C.

48 citations


Journal ArticleDOI
TL;DR: These studies reveal that, in addition to modulation of the depletion region in n-SrTiO_{3}, the BaTiO_3} barrier layer becomes conducting near the interface for polarization pointing into n- SrTi O_{3], leading to dramatic enhancement of TER.
Abstract: Realizing a large tunneling electroresistance (TER) effect is crucial for device application of ferroelectric tunnel junctions (FTJs) FTJs are typically composed of a thin ferroelectric layer sandwiched by two metallic electrodes, where TER generally results from the dependence of the effective tunneling barrier height on the ferroelectric polarization Since the resistance depends exponentially not only on barrier height but also on barrier width, TER is expected to be greatly enhanced when one of the electrodes is a semiconductor where the depletion region near the interface can be controlled via ferroelectric polarization To explore this possibility, we perform studies of SrRuO_{3}/BaTiO_{3}/n-SrTiO_{3} FTJs, where n-SrTiO_{3} is an electron doped SrTiO_{3} electrode, using first-principles density functional theory Our studies reveal that, in addition to modulation of the depletion region in n-SrTiO_{3}, the BaTiO_{3} barrier layer becomes conducting near the interface for polarization pointing into n-SrTiO_{3}, leading to dramatic enhancement of TER The effect is controlled by the band alignment between the semiconductor and the ferroelectric insulator and opens the way for experimental realization of enhanced TER in FTJs through the choice of a semiconducting electrode and interface engineering

48 citations


Journal ArticleDOI
TL;DR: In this paper, a plasma-free etch stop structure is developed for GaN HEMTs toward enhancement-mode operation, where a selfterminated precision gate recess is realized by inserting a thin AlN/GaN bilayer in the AlGaN barrier layer.
Abstract: In this letter, a plasma-free etch stop structure is developed for GaN HEMT toward enhancement-mode operation. The self-terminated precision gate recess is realized by inserting a thin AlN/GaN bilayer in the AlGaN barrier layer. The gate recess is stopped automatically at the GaN insertion layer after high-temperature oxidation and wet etch, leaving a thin AlGaN barrier to maintain a quantum well channel that is normally pinched off. With addition of an Al2O3 gate dielectric, quasi normally OFF GaN MOSHEMTs have been fabricated with high threshold uniformity and low ON-resistance comparable with the normally ON devices on the same wafer. A high channel mobility of 1400 cm $^{2}/\textrm {V}\cdot \textrm {s}$ was obtained due to the preservation of the high electron mobility in the quantum-well channel under the gate.

48 citations


Journal ArticleDOI
TL;DR: In this paper, a binary anti-corrosion structures on the surface of aluminum alloys with super-hydrophobic properties were fabricated via chemical etching, anodic oxidation and chemical modification.
Abstract: Aluminum alloys with novel binary anti-corrosion structures on the surface showing superhydrophobic properties were fabricated via chemical etching, anodic oxidation and chemical modification. Surface morphologies and chemical elements of the as-prepared films were investigated by Fourier transform infrared spectrometer, scanning electron microscopy and confocal laser scanning microscope. Surface wettability was investigated by the contact angle meter. Manipulation of surface morphology by anodic oxidation current density and the influence of surface chemical modification on the wettability were investigated. The anti-corrosion properties of the as-prepared films were characterized using an electrochemistry workstation. The results showed that surface water contact angle could reach 156° after chemical modification when the current density of anodic oxidation was 5 A dm−2. The corrosion potential (Ecorr) was positively increased from −1189 mV for bare Al alloys to −304 mV for the samples anodized at 5 A dm−2. The synergetic effect between the protective properties of air trapped in a low adhesion superhydrophobic surface and good barrier properties of the barrier layer of anodic oxidation film was remarkably enhanced the corrosion resistance of aluminum alloys. Influences of the anodic oxidation current density and the self-assembled films on the anti-corrosion performance were discussed in detail.

48 citations


Patent
Mike Andersson1, Hossein Fashandi1
08 Jul 2016
TL;DR: In this paper, a field effect gas sensor for detecting a presence of a gaseous substance in a gas mixture was proposed. But the sensor was not designed to detect the presence of the gas in the gas mixture.
Abstract: A field effect gas sensor, for detecting a presence of a gaseous substance in a gas mixture, the field effect gas sensor comprising: a SiC semiconductor structure (2, 3); an electron insulating layer (7) covering a first portion of the SiC semiconductor structure; a first contact structure (12) at least partly separated from the SiC semiconductor structure by the electron insulating layer; and a second contact structure (8b) conductively connected to a second portion of the SiC semiconductor structure, wherein at least one of the electron insulating layer (7) and the first contact structure (12) is configured to interact with the gaseous substance to change an electrical property of the SiC semiconductor structure; and wherein the second contact structure comprises: an ohmic contact layer (9) in direct contact with the second portion of the SiC semiconductor structure; and a barrier layer (10) formed by an electrically conducting mid-transition-metal oxide covering the ohmic contact layer.

47 citations


Patent
27 Apr 2016
TL;DR: In this article, a communication equipment metal shell is described, which consists of a metal substrate with more than one slit, an anodic oxidation film layer and a plastic support layer.
Abstract: The invention discloses a communication equipment metal shell and preparation method thereof. The communication equipment metal shell comprises a metal substrate with more than one slit, an anodic oxidation film layer and a plastic support layer, wherein the anodic oxidation film layer is at least located on the inner surface of the metal substrate; the plastic support layer is formed on the anodic oxidation film layer; the anodic oxidation film layer comprises a barrier layer and a loose layer; the barrier layer is in contact with the metal substrate and the loose layer is located on the outer surface of the barrier layer; the loose layer contains loose layer micropores; the apertures of the loose layer micropores are 10nm to 800microns; the barrier layer contains barrier layer micropores; and the apertures of the barrier layer micropores are 10nm to 800 microns. The binding force of the plastic support layer and the metal substrate of the communication equipment metal shell disclosed by the invention is high; and the communication equipment metal shell has an integrated effect in appearance.

44 citations


Journal ArticleDOI
TL;DR: In this article, the authors proposed to limit charge injection from a semi-conducting electrode into low density polyethylene (LDPE) under dc field by tailoring the polymer surface using a silver nanoparticles-containing layer.
Abstract: The aim of this work is to limit charge injection from a semi-conducting electrode into low density polyethylene (LDPE) under dc field by tailoring the polymer surface using a silver nanoparticles-containing layer. The layer is composed of a plane of silver nanoparticles embedded in a semi-insulating organosilicon matrix deposited on the polyethylene surface by a plasma process. Size, density and surface coverage of the nanoparticles are controlled through the plasma process. Space charge distribution in 300 μm thick LDPE samples is measured by the pulsed-electroacoustic technique following a short term (step-wise voltage increase up to 50 kV mm−1, 20 min in duration each, followed by a polarity inversion) and a longer term (up to 12 h under 40 kV mm−1) protocols for voltage application. A comparative study of space charge distribution between a reference polyethylene sample and the tailored samples is presented. It is shown that the barrier effect depends on the size distribution and the surface area covered by the nanoparticles: 15 nm (average size) silver nanoparticles with a high surface density but still not percolating form an efficient barrier layer that suppress charge injection. It is worthy to note that charge injection is detected for samples tailored with (i) percolating nanoparticles embedded in organosilicon layer; (ii) with organosilicon layer only, without nanoparticles and (iii) with smaller size silver particles (<10 nm) embedded in organosilicon layer. The amount of injected charges in the tailored samples increases gradually in the samples ranking given above. The mechanism of charge injection mitigation is discussed on the basis of complementary experiments carried out on the nanocomposite layer such as surface potential measurements. The ability of silver clusters to stabilize electrical charges close to the electrode thereby counterbalancing the applied field appears to be a key factor in explaining the charge injection mitigation effect.

37 citations


Patent
20 Jan 2016
TL;DR: In this paper, a light-emitting diode epitaxial wafer is characterized by comprising a low-temperature buffer layer GaN, an undoped GaN layer, a uAl superlattice layer, an N-type GaNlayer, a first barrier layer, shallow quantum well layer, multi-quantum well layer and an electronic barrier layer.
Abstract: The invention discloses a light-emitting diode epitaxial wafer and a preparation method thereof. The light-emitting diode epitaxial wafer is characterized by comprising a low-temperature buffer layer GaN, an undoped GaN layer, a uAl superlattice layer, an N-type GaN layer, a first barrier layer, a shallow quantum well layer, a multi-quantum well layer, an electronic barrier layer, an Mg-doped P-type GaN layer and a CTL layer, wherein the undoped GaN layer is located on the low-temperature buffer layer GaN; the uAl superlattice layer is located on the undoped GaN layer; the N-type GaN layer is located on the uAl superlattice layer; the first barrier layer is located on the N-type GaN layer; the shallow quantum well layer is located on the first barrier layer; the multi-quantum well layer is located on the shallow quantum well layer; the electronic barrier layer is located on the multi-quantum well layer; the Mg-doped P-type GaN layer is located on the electronic barrier layer; and the CTL layer is located on the Mg-doped P-type GaN layer. According to the light-emitting diode epitaxial wafer and the preparation method thereof disclosed by the invention, the backward voltage can be significantly improved by adding the uAl superlattice layer structure.

36 citations


Patent
13 Oct 2016
TL;DR: The method of manufacturing a semiconductor device includes forming an insulating film of a silicon compound-group insulation film; forming an opening in the insulation film, applying an active energy beam in an atmosphere containing hydrocarbon gas to form a barrier layer of a crystalline SiC, and forming an interconnection structure of copper in the opening with the barrier layer formed in this paper.
Abstract: The method of manufacturing a semiconductor device includes forming an insulating film of a silicon compound-group insulation film; forming an opening in the insulation film, applying an active energy beam in an atmosphere containing hydrocarbon gas to form a barrier layer of a crystalline SiC, and forming an interconnection structure of copper in the opening with the barrier layer formed in

Journal ArticleDOI
TL;DR: In this article, the barrier effect, adhesion, and contact resistance of each of these materials were evaluated, and it was shown that Mg appeared on the Ti surface and TiSi2 deposited on Mg2Si; however, no Mg was detected on the surface of TiN or in the inner part of the Ni electrode.
Abstract: The durability of Ni electrodes, which are often used for Mg2Si thermoelectric chips, is poor at high working temperatures because of deposition of Mg at the Mg2Si/Ni interface and on the surface. Hence, a “Mg2Si/barrier material/Ni” structure was adopted instead of direct adhesion of Ni to Mg2Si. Ti, TiSi2, and TiN were selected as candidate materials for the barrier layer between Mg2Si and Ni, and the barrier effect, adhesion, and contact resistance of each of these materials were evaluated. After the samples had been annealed at 873 K for 1 h, Mg appeared on the Ti surface and TiSi2 deposited on Mg2Si; however, no Mg was detected on the surface of TiN or in the inner part of the Ni electrode. Continuous, low contact resistance was also observed for Mg2Si/TiN/Ni samples. TiN does not adhere strongly to Mg2Si but is a promising barrier material for Mg2Si/Ni interfaces.

Journal ArticleDOI
TL;DR: Capacitance voltage (CV) analysis, before and after tube furnace anneals of the fabricated MOS structures showed that the presence of the MnSiO3 barrier layer significantly improved electric stability of the device structures.
Abstract: Copper/SiO2/Si metal-oxide-semiconductor (MOS) devices both with and without a MnSiO3 barrier layer at the Cu/SiO2 interface have been fabricated in an ultrahigh vacuum X-ray photoelectron spectroscopy (XPS) system, which allows interface chemical characterization of the barrier formation process to be directly correlated with electrical testing of barrier layer effectiveness. Capacitance voltage (CV) analysis, before and after tube furnace anneals of the fabricated MOS structures showed that the presence of the MnSiO3 barrier layer significantly improved electric stability of the device structures. Evidence of improved adhesion of the deposited copper layer to the MnSiO3 surface compared to the clean SiO2 surface was apparent both from tape tests and while probing the samples during electrical testing. Secondary ion mass spectroscopy (SIMS) depth profiling measurements of the MOS test structures reveal distinct differences of copper diffusion into the SiO2 dielectric layers following the thermal anneal d...

Journal ArticleDOI
TL;DR: In this paper, a modified Nb2O5 blocking layer was inserted at the fluorine doped tin oxide (FTO)/TiO2 interface via a Rf magnetron sputtering process.
Abstract: The prevention of back electron transfer by inserting an energy barrier layer at the interface of a photo-anode is an effective method for improving the photovoltaic parameters in dye sensitised solar cells (DSSCs). In this study, phase a modified Nb2O5 blocking layer was inserted at the fluorine doped tin oxide (FTO)/TiO2 interface via a Rf magnetron sputtering process. For a critical tunnelling distance of ∼40 nm, the crystalline Nb2O5 blocking layer improved the efficiency close to 7% and outperformed the amorphous blocking layer by about 68%. The longer electron lifetime observed in DSSCs containing an inhomogeneous Nb2O5 layer indicates that trapping/de-trapping impedes the discharge of electrons to the TiO2 band edge. The origin of the longer electron lifetime is explained by formulating a theory from photovoltage decay measurements.

Journal ArticleDOI
TL;DR: In this article, the authors investigated the impact of a Mo barrier layer (Mob) on the formation of MoSe2, as it relates to the performance of CIGS thin film solar cells with a structure of glass/Mo/Mob/CIGS/CdS/i-ZnNO/ZnO:Al/Al.

Journal ArticleDOI
01 Mar 2016-Carbon
TL;DR: In this paper, the authors demonstrate the growth of high quality single-walled carbon nanotube (SWCNT) forests on commercial Cu foils by cold-wall chemical vapor deposition.

Journal ArticleDOI
TL;DR: In this article, the authors reported an enhancement in the selectivity of the vapor sensing properties of free base porphyrin 5,10,15,20-tetrakis[3,4-bis(2-ethylhexyloxy)phenyl]-21H,23H-porphine (EHO) Langmuir-Schaefer (LS) films.

Journal ArticleDOI
TL;DR: In this paper, CdIn2S4 (CdIS) quantum dots were synthesized via a solid-state thermal decomposition approach for the first time, and the as-synthesized products were characterized extensively by techniques such as XRD, EDS, SEM, TEM, AFM, FTIR and DRS.
Abstract: Herein, CdIn2S4 (CdIS) quantum dots were synthesized via a solid-state thermal decomposition approach for the first time. [Cd(en)2]SO4, In(NO3)3·5H2O and thioacetamide were used as the cadmium, indium and sulfur sources. The as-synthesized products were characterized extensively by techniques such as XRD, EDS, SEM, TEM, AFM, FTIR and DRS. The effect of the cadmium source type, temperature and reaction atmosphere on the morphology and purity of the final products were studied. The results showed that choosing the appropriate temperature and cadmium source has a significant influence on CdIS–QDs synthesis. Moreover, the as-prepared CdIS–QDs were utilized as a barrier layer in dye sensitized solar cells (DSSCs) for the first time. The short-circuit photocurrent density (Jsc), open-circuit voltage (Voc), fill factor (FF) and efficiency of the solar cell were studied. The power conversion efficiency of the DSSCs using a CdIS–QDs barrier layer was 8.17%, which is 32.2% higher than the cell without a novel barrier layer (6.18%).

Journal ArticleDOI
TL;DR: In this paper, a flexible charge-trap-type memory (f-CTM) thin-film transistor was proposed and fabricated on poly(ethylene naphthalate) (PEN) substrate.
Abstract: A flexible charge-trap-type memory (f-CTM) thin-film transistor was proposed and fabricated on poly(ethylene naphthalate) (PEN) substrate. All the fabrication process temperature was suppressed below 180 °C. To improve the surface roughness and water vapor transmission rate of the PEN substrate, the organic/inorganic hybrid barrier layer was introduced. The gate-stack was composed of all oxide layers, such as In–Ga–Zn–O active channel, ZnO charge-trap layer, Al2O3 blocking/tunneling layers, and In–Sn–O transparent electrode, in which double-layered tunneling and top-protection layers were designed, so that the f-CTMs could exhibit stable and excellent device performance. As results, wide memory margin (25.6 V), fast programming speed ( $\sim 500$ ns), and long retention time (>3 h) were obtained at room temperature and at 80 °C. Furthermore, these memory device characteristics were not degraded even after the delamination of PEN substrate and under the bending situation with a given curvature radius (3.3 mm).

Patent
Dong-Kyun Kang1
25 Jul 2016
TL;DR: In this article, a transistor is defined as a source region and a drain region that are formed in a substrate to be spaced apart from each other; a trench formed in the substrate between the source regions and the drain region; and a buried gate electrode inside the trench, wherein the buried gate electrodes includes a lower buried portion which includes a high work-function barrier layer including an aluminum-containing titanium nitride, and an upper buried portion including a low work function barrier layer disposed over the lower buried part and overlapping with the source region, and a second low-resistivity layer disposed
Abstract: A transistor includes: a source region and a drain region that are formed in a substrate to be spaced apart from each other; a trench formed in the substrate between the source region and the drain region; and a buried gate electrode inside the trench, wherein the buried gate electrode includes: a lower buried portion which includes a high work-function barrier layer including an aluminum-containing titanium nitride, and a first low-resistivity layer disposed over the high work-function barrier layer; and an upper buried portion which includes a low work-function barrier layer disposed over the lower buried portion and overlapping with the source region and the drain region, and a second low-resistivity layer disposed over the low work-function barrier layer.

Journal ArticleDOI
TL;DR: According to the transmission electron microscope measurements, the layer structure improvement with barrier layers can be attributed to the suppression of the crystallization of vanadium inside the structure.
Abstract: To develop the high reflectance mirror for the short wavelength range of the water window region (λ=2.42-2.73 nm), Cr/V multilayers with B4C barrier layers are studied. The grazing incidence x-ray reflectometry results show that the multilayer interface widths are significantly reduced down to 0.21-0.31 nm, after the introduction of 0.1 nm B4C barrier layers at both interfaces. The [B4C/Cr/B4C/V] multilayer with a large number of bilayers of N=300 maintains the same small interface widths while the surface roughness is only 0.2 nm. According to the transmission electron microscope measurements, the layer structure improvement with barrier layers can be attributed to the suppression of the crystallization of vanadium inside the structure. Using the interface engineered multilayer, a maximum soft x-ray reflectance of 24.3% is achieved at λ=2.441 nm, under the grazing incidence of 42°.

Journal ArticleDOI
TL;DR: In this article, the defect occurrence rate has been calculated to be 0.268/cm2/h for devices with the single Al2O3 barrier layer, τ has been estimated to be 64 h.
Abstract: Al2O3 [20 nm, atomic layer deposition (ALD)] and SiO films' [25 nm, physical vacuum deposition (PVD)] single barriers as well as hybrid barriers of the Al2O3/SiO or SiO/Al2O3 have been deposited onto single 100 nm thick tris-(8-hydroxyquinoline) aluminum (AlQ3) organic films made onto silicon wafers. The defects in the different barrier layers could be easily observed as nonfluorescent AlQ3 black spots, under ultraviolet light on the different systems stored into accelerated aging conditions (85 °C/85% RH, ∼2000 h). It has been observed that all devices containing an Al2O3 layer present a lag time τ from which defect densities of the different systems start to increase significantly. This is coherent with the supposed pinhole-free nature of fresh, ALD-deposited, Al2O3 films. For t > τ, the number of defect grows linearly with storage time. For devices with the single Al2O3 barrier layer, τ has been estimated to be 64 h. For t > τ, the defect occurrence rate has been calculated to be 0.268/cm2/h. Then, a t...

Journal ArticleDOI
TL;DR: In this article, a GaN-on-Si high electron mobility transistor (HEMT) with a 1702 V breakdown voltage (BV) and low current collapse was fabricated.
Abstract: This paper reports the successful fabrication of a GaN-on-Si high electron mobility transistor (HEMT) with a 1702 V breakdown voltage (BV) and low current collapse. The strain and threading dislocation density were well-controlled by 100 pairs of AlN/GaN superlattice buffer layers. Relative to the carbon-doped GaN spacer layer, we grew the AlGaN back barrier layer at a high temperature, resulting in a low carbon-doping concentration. The high-bandgap AlGaN provided an effective barrier for blocking leakage from the channel to substrate, leading to a BV comparable to the ordinary carbon-doped GaN HEMTs. In addition, the AlGaN back barrier showed a low dispersion of transiently pulsed ID under substrate bias, implying that the buffer traps were effectively suppressed. Therefore, we obtained a low-dynamic on-resistance with this AlGaN back barrier. These two approaches of high BV with low current collapse improved the device performance, yielding a device that is reliable in power device applications.

Journal ArticleDOI
TL;DR: In this article, the electrochemical behavior of the Ti-6Al-4V ELI alloy with different microstructures was investigated in Ringer's solution at 25 °C.
Abstract: The electrochemical behaviour of the Ti-6Al-4V ELI alloy with different microstructures was investigated in Ringer's solution at 25 °C. It was found that the properties of both inner barrier and outer porous layers of the passive film were dependent on the microstructural morphology and distribution of the alloying elements resulting in various amounts of their oxides incorporated in the TiO2 matrix. A more resistant and capacitive barrier layer formed on the alloy with fully lamellar, martensitic and globular microstructures in different thickness assured its high corrosion protection. The improved corrosion resistance of the alloy with equiaxed microstructure was provided by the existence of the larger amounts of the Al2O3 and V2O5 oxides, contributing to higher resistance of the outer porous layer. The Al2O3 amount is smaller than that of the V2O5 oxide due to its higher dissolution, especially in the case of the alloy with fully lamellar microstructure, resulting in the formation of a more porous outer layer.

Patent
24 Feb 2016
TL;DR: In this paper, a flexible display panel consisting of a flexible substrate, a first barrier layer, display parts, a second barrier layer and a barrier effect indication layer is presented, which can indicate the packaging effect of an organic light emitting diode device.
Abstract: The invention discloses a display device, a flexible display panel and a manufacturing method thereof. The flexible display panel comprises a flexible substrate, a first barrier layer, display parts, a second barrier layer and a barrier effect indication layer, wherein the first barrier layer is arranged on the flexible substrate; the display parts are arranged on the first barrier layer; the second barrier layer is arranged on the first barrier layer, and covers the display parts; the barrier effect indication layer is arranged between the first barrier layer and the second barrier layer, and surrounds the display parts. The flexible display panel can indicate the packaging effect thereof, and ensures packaging effect thereof, thereby guaranteeing photoelectric characteristics of an organic light emitting diode device, and prolonging the service life of the organic light emitting diode device.

Patent
20 Jan 2016
TL;DR: In this article, a flexible OLED display panel is proposed, which comprises a flexible substrate, an OELD device, a first encapsulation layer, a barrier layer and a second encapsulation layers.
Abstract: The invention discloses a flexible OLED display panel, which comprises a flexible substrate, an OELD device, a first encapsulation layer, a barrier layer and a second encapsulation layer, wherein the OLED device is arranged on the flexible substrate; the first encapsulation layer is arranged on the flexile substrate and covers the OLED device; the barrier layer is arranged on the flexible substrate, surrounds the periphery of the first encapsulation layer, and comprises a plurality of discontinuous barrier units; the plurality of barrier units are arranged in a chain form; and the second encapsulation layer is arranged on the flexible substrate and covers the first encapsulation material and the barrier layer. The flexible OLED display panel is capable of effectively blocking the diffusion effect of atomic deposition coating and enhancing the water blocking capacity of a thin-film encapsulation on the periphery of the flexible OLED display panel; meanwhile, the reelability of the barrier layer is increased; the development requirement of the flexible OLED display panel is relatively well met; and an important idea is also provided for development of the flexible OLED display panel.

Patent
Rahul Sharangpani1, Raghuveer S. Makala1, Keerti Shukla1, Fei Zhou1, Somesh Peri1 
12 Oct 2016
TL;DR: In this article, an electrically conductive, amorphous barrier layer can be formed prior to formation of a metal fill material layer to provide a diffusion barrier that reduces fluorine diffusion between the metal fill materials layer and memory films of memory stack structures.
Abstract: Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. An electrically conductive, amorphous barrier layer can be formed prior to formation of a metal fill material layer to provide a diffusion barrier that reduces fluorine diffusion between the metal fill material layer and memory films of memory stack structures. The electrically conductive, amorphous barrier layer can be an oxygen-containing titanium compound or a ternary transition metal nitride.

Patent
23 Aug 2016
TL;DR: In this paper, a light-emitting device is disclosed, comprising a substrate, a light emitting structure on the substrate comprising a first region and a second region; a barrier layer on the first region having a bottom surface and a sidewall, wherein an angle between the sidewall and the bottom surface is between 10°70°.
Abstract: A light-emitting device is disclosed, comprising a substrate; a light-emitting structure on the substrate comprising a first region and a second region; a barrier layer on the first region having a bottom surface and a sidewall, wherein an angle between the sidewall and the bottom surface is between 10°70°; and a transparent conductive layer formed on the light-emitting structure and the barrier layer; wherein a difference between a thickness of the transparent conductive layer at the sidewall on the barrier layer and a thickness of the transparent conductive layer on the second region of the light-emitting structure forms a ratio not larger than 10 %.

Journal ArticleDOI
TL;DR: In this paper, an $8 \times 8$ k.p Hamiltonian combined with nonequilibrium Green's function formalism has been employed to numerically demonstrate that the single-band effective mass approximation is an adequate numerical approach, which is valid for the modeling, design, and optimization of band alignment and carrier transport in HgCdTe-based nBn detectors incorporating a wide bandgap superlattice barrier.
Abstract: Implementation of the unipolar barrier detector concept in HgCdTe-based compound semiconductor alloys is a challenging problem, primarily because practical lattice-matched materials that can be employed as the wide bandgap barrier layer in HgCdTe nBn structures present a significant valence band offset at the n-type/barrier interface, thus impeding the free flow of photogenerated minority carriers. However, it is possible to minimize the valence band offset by replacing the bulk HgCdTe alloy-based barrier with a CdTe–HgTe superlattice barrier structure. In this paper, an $8 \times 8$ k.p Hamiltonian combined with the nonequilibrium Green’s function formalism has been employed to numerically demonstrate that the single-band effective mass approximation is an adequate numerical approach, which is valid for the modeling, design, and optimization of band alignment and carrier transport in HgCdTe-based nBn detectors incorporating a wide bandgap superlattice barrier.

Journal ArticleDOI
TL;DR: Time constant spectra are extracted from current transients based on the Bayesian deconvolution and used to characterize traps in GaN high-electron mobility transistors and observe that the trap in the AlGaN barrier layer requires sufficient electric field to activate the trapping process and a high drain voltage accelerates the trapping processes both in theAlGaN Barrier layer and the GaN layer.