Showing papers on "Barrier layer published in 2017"

Flexible display device

Abstract: A flexible display device includes a flexible substrate, an inorganic barrier layer, a metal layer, an organic buffer layer, and an insulating layer. The inorganic barrier layer is located on the flexible substrate. The metal layer is located on the inorganic barrier layer and in contact with the inorganic barrier layer. The organic buffer layer covers the inorganic barrier layer and the metal layer, and has at least one conductive via connected to the metal layer. The insulating layer is located on the organic buffer layer.

14nm metal gate film stack development and challenges

Abstract: As IC technology advances to 16/14 nm and beyond, FinFET architecture with advantage of excellent leakage performance becomes main stream in IC industry. However, it also brings big challenges for integration and processes due to its very aggressive structure and profile, CD shrinkage, shadow effect and gap-fill difficulty. In this work, atomic layer deposition (ALD) metal films, including TaN, TiN (TiSiN), TiAl and CVD W, were studied for replacement metal gate application. Challenges of step coverage & gap-fill, loading effect and tunable range of work function will be discussed and addressed. Thickness of high K capping layer (TiN or TaN), work function metal (TiN & TiAl), W barrier layer (TiN) all show strong effect on N/P MOS device Vt, and more than 300 mv tunable range of work function can be achieved. Besides, higher Al : Ti ratio process, interfacial special treatment between TiAl & W barrier TiN and different W process can lower down NMOS Vt. At the last, ALD and CVD process ensure good gap-fill performance when CD opening is larger than 5nm (aspect ratio is about 20∶1).

Method of forming metal interconnection and method of fabricating semiconductor apparatus using the method

Abstract: A semiconductor manufacturing method includes depositing a low-k dielectric layer, forming a trench in the low-k dielectric layer, forming a barrier layer in the trench, filling a metal on the barrier layer, planarizing the metal, and forming a capping layer on the planarized metal, wherein the capping layer includes at least two layers.

Barrier-Layer Optimization for Enhanced GaN-on-Diamond Device Cooling.

Abstract: GaN-on-diamond device cooling can be enhanced by reducing the effective thermal boundary resistance (TBReff) of the GaN/diamond interface. The thermal properties of this interface and of the polycrystalline diamond grown onto GaN using SiN and AlN barrier layers as well as without any barrier layer under different growth conditions are investigated and systematically compared for the first time. TBReff values are correlated with transmission electron microscopy analysis, showing that the lowest reported TBReff (∼6.5 m2 K/GW) is obtained by using ultrathin SiN barrier layers with a smooth interface formed, whereas the direct growth of diamond onto GaN results in one to two orders of magnitude higher TBReff due to the formation of a rough interface. AlN barrier layers can produce a TBReff as low as SiN barrier layers in some cases; however, their TBReff are rather dependent on growth conditions. We also observe a decreasing diamond thermal resistance with increasing growth temperature.

Colossal permittivity in (In1/2Nb1/2)xTi1−xO2 ceramics prepared by a glycine nitrate process

Abstract: (In + Nb) co-doped TiO2 nanoparticles with very low dopant concentrations were prepared using a glycine nitrate process. A pure rutile—TiO2 phase with a dense microstructure and homogeneous dispersion of dopants was achieved. By doping TiO2 with 1.5% (In + Nb) ions, a very high dielectric permittivity of e′ = 42,376 and low loss tangents of tanδ = 0.06 (at room temperature) were achieved. The large conduction activation energy at the grain boundary decreased with decreasing dopant concentration. The colossal permittivity was primarily attributed to the internal barrier layer capacitor (IBLC) effect. The dominant effect of interfacial polarization at the non–Ohmic sample–electrode contact was observed when the dopant concentration was ≤1.0 mol%. Interestingly, the sample–electrode contact and resistive–outer surface layer effects, i.e., surface barrier layer capacitor (SBLC) effect, has also an effect on the colossal dielectric response in (In + Nb) co-doped TiO2 ceramics.

Studies of two-dimensional h-BN and MoS 2 for potential diffusion barrier application in copper interconnect technology

Abstract: Copper interconnects in modern integrated circuits require a barrier layer to prevent Cu diffusion into surrounding dielectrics. However, conventional barrier materials like TaN are highly resistive compared to Cu and will occupy a large fraction of the cross-section of ultra-scaled Cu interconnects due to their thickness scaling limits at 2–3 nm, which will significantly increase the Cu line resistance. It is well understood that ultrathin, effective diffusion barriers are required to continue the interconnect scaling. In this study, a new class of two-dimensional (2D) materials, hexagonal boron nitride (h-BN) and molybdenum disulfide (MoS2), is explored as alternative Cu diffusion barriers. Based on time-dependent dielectric breakdown measurements and scanning transmission electron microscopy imaging coupled with energy dispersive X-ray spectroscopy and electron energy loss spectroscopy characterizations, these 2D materials are shown to be promising barrier solutions for Cu interconnect technology. The predicted lifetime of devices with directly deposited 2D barriers can achieve three orders of magnitude improvement compared to control devices without barriers. Atomically thin h-BN and MoS2 may provide a viable alternative to conventional barrier materials in Cu interconnects. A team led by Zhihong Chen at Purdue University utilized two-dimensional crystals to mitigate Cu diffusion into the dielectric, a known cause of chip failure. By means of time-dependent dielectric breakdown measurements to investigate the diffusion barrier properties of atomically thin h-BN and MoS2, they recorded a substantial improvement of the time-to-breakdown, owing to a reliability enhancement of the dielectric underneath Cu under normal operating conditions. A number of structural and electrical characterizations, including scanning transmission electron microscopy, energy dispersive X-ray spectroscopy, and electron energy loss spectroscopy confirmed that two-dimensional h-BN and MoS2 films effectively prevent Cu diffusion, highlighting their potential applicability as sub-nanometer barrier for interconnect technology.

Semiconductor device including a resonant tunneling diode structure with electron mean free path control layers

Abstract: A semiconductor device including at least one double-barrier resonant tunneling diode (DBRTD) is provided. The at least one DBRTD may include a first doped semiconductor layer, and a first barrier layer on the first doped semiconductor layer and including a superlattice. The DBRTD may further include a first intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the first intrinsic semiconductor layer and also including the superlattice, a second intrinsic semiconductor layer on the second barrier layer, a third barrier layer on the second intrinsic semiconductor layer and also including the superlattice. A third intrinsic semiconductor layer may be on the third barrier layer, a fourth barrier layer may be on the third intrinsic semiconductor layer and also including the superlattice, a second doped semiconductor layer on the fourth barrier layer.

Atmospheric pressure roll‐to‐roll plasma enhanced CVD of high quality silica‐like bilayer encapsulation films

Abstract: A glow like atmospheric pressure dielectric barrier discharge in a roll-to-roll setup was used to synthesize 90 nm silica-like bilayer encapsulation films composed of a 30 nm dense “barrier layer” and a comparatively less dense 60 nm “buffer layer” onto a polyethylene 2,6 naphthalate substrate by means of plasma enhanced chemical vapor deposition. Tetraethyl orthosilicate was used as the precursor gas, together with a mixture of nitrogen, oxygen, and argon. The microstructure, chemical composition, morphology, and permeation properties of the films were studied as a function of the specific energy delivered per precursor molecule, and oxygen concentration in the gas mixture, during the deposition of the barrier layer. The presence of the buffer layer within the bilayer architecture critically enhanced the encapsulation performance of the bilayer films, and this in conjunction with increasing the specific energy delivered per precursor molecule during the barrier layer deposition to a value of 20 keV, enabled an effective water vapor transmission rate as low as 6.9 × 10−4 g m−2 d−1 (at 40 °C, 90% relative humidity (RH)) to be achieved. Furthermore, the bilayer film structure has given rise to a remarkable 50% reduction in deposition energy consumption per barrier area with respect to single layer silica-like films of equivalent encapsulation performance and thickness.

Light-emitting diode display device

Abstract: A light emitting diode (LED) display device including an array substrate, an opposite substrate, wall structures, at least one LED, an upper reflection layer, a first light barrier layer, a lower reflection layer and a light diffusion material layer. The array substrate, the wall structures and the opposite substrate define an accommodating region. The upper reflection layer is disposed on the LED, wherein the upper reflection layer at least partially covers an upper surface of the LED. The first light barrier layer is disposed on a side of the upper reflection layer away from the array substrate. An orthographic projection of the upper reflection layer on the array substrate is at least partially overlapped with an orthographic projection of the lower reflection layer on the array substrate. The light diffusion material layer is filled in the accommodating region.

Solving the BEOL compatibility challenge of top-pinned magnetic tunnel junction stacks

Abstract: For the first time, we report on 400°C compatible top-pinned perpendicular magnetic tunnel junction (MTJ) stacks with dual MgO free layer for STT-MRAM applications Using a texture-inducing parallel-coupling barrier layer (TICPB), we enforce the pinning layer and control diffusion, which enables BEOL compatibility while keeping TMR as high as 184% In addition, we demonstrate that using such synthetic ferro-magnetic stack (SFM) design with TICPB layer allows a free layer off-set control and a switching current of 38 MA/cm2 in 25 nm e-CD devices

Electronic device and method for fabricating the same

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate; and a stepped structure including first interlayer dielectric layers and conductive layers which are alternately stacked over the substrate, wherein ends of the conductive layers are exposed along the profile of the stepped structure, and the stepped structure further includes a barrier layer formed on a sidewall of the conductive layer.

Morphology and corrosion resistance of hybrid plasma electrolytic oxidation on CP-Ti

Abstract: In this research, double plasma electrolytic oxidation coating in two different electrolytes on commercially pure titanium was done. First layer of PEO coating was synthesized in acidic solution of phosphoric/sulfuric acid with 4 levels of current density and the second layer was synthesized in the solution containing calcium acetate/sodium hypophosphite monohydrate. The role of current density on first layer's morphology, hybrid coating's morphology, and corrosion performance is investigated. Mott-Schottky analyses in combination with EIS test were used to reveal the underlying causes of corrosion resistance changes of hybrid PEO coatings. It was revealed that at low current densities grooved microstructure develops which showed high corrosion resistance, compared to porous microstructure. It was also found that grooved microstructure, as first layer, is not favorable for hybrid PEO coating and has detrimental effect on corrosion performance due to its effect on discharge behavior of the second layer. Comparison of corrosion performance of samples with porous morphology revealed that application of low current density improves corrosion resistance.Application of the hybrid-layered coating with the optimized process parameters led to 5 times increase of polarization resistance compared to single-layered coating. EIS studies revealed that corrosion resistance changes were mainly originated from changes in properties of the barrier layer. Analysis of Mott-Schottky plots showed that samples with more resistance has lower donor density which is ascribed to their compact microstructure.

Investigation of micro- and nanoscale barrier layer capacitance mechanisms of conductivity in CaCu3Ti4O12via scanning probe microscopy technique

Abstract: In this work we disclose micro- and nanoscale origins of the unusually high dielectric constant characteristic of CaCu3Ti4O12 (CCTO) ceramic by using the Scanning Probe Microscopy (SPM) technique. Two main mechanisms responsible for the colossal dielectric constant specific to the CCTO compound have been revealed. There is a microscale barrier layer capacitance (MBLC) mechanism, attributed to the potential grain-to-grain barriers, and a nanoscale barrier layer capacitance (NBLC) mechanism, attributed to the potential barriers created by the structural defects such as twinning or slip planes. Using the contact spreading resistance mode of SPM, we have found two types of surface morphology which, being originated from planar defects, can be related to the NBLC mechanism. A clear confirmation of NBLC as the origin of the huge dielectric constant in CCTO has been obtained via the local current–voltage dependence measurements. By using this method, we have found the existence of two sources of conductivity (charge transfer and charge hopping) which simultaneously contribute to the NBLC mechanism. These sources (providing semiconducting and n-type conducting behavior, respectively) have been associated with the different stacking faults predicted for CCTO. The present work promotes a general understanding of anomalous colossal dielectric constant behavior in CCTO material at the macro- and nanoscale levels.

Buffer Layer Engineering for High ( $\geq 10^{\mathrm {13}}$ cm $^{\mathrm {-2}}$ ) 2-DEG Density in ZnO-Based Heterostructures

Abstract: In this paper, we report on the prospect of achieving very high values ( $\geq 10^{13}$ cm $^{-2}$ ) of 2-D electron gas (2-DEG) density in ZnO-based heterostructures through buffer layer engineering. A physics-based analytical model is developed and utilized to demonstrate up to $25\times $ higher 2-DEG values in MgZnO/CdZnO as compared with that in the MgZnO/ZnO heterostructure at lower Mg composition of 0.10 in barrier layer. It is shown that a lower spontaneous polarization in buffer layer due to more electronegative Cd and higher lattice constant of CdZnO, which introduces tensile piezoelectric strain in the barrier layer, favorably add up, and increase polarization difference at barrier-buffer interface, which eventually enhances 2-DEG density. This paper demonstrates new opportunities to effectively utilize buffer layer properties to significantly improve the 2-DEG sheet density (~ $4 \times 10^{\mathrm { {13}}}$ cm $^{\mathrm { {-2}}}$ ) in ZnO heterostructures.

Ultrathin Epitaxial Barrier Layer to Avoid Thermally Induced Phase Transformation in Oxide Heterostructures

Abstract: Incorporating oxides with radically different physical and chemical properties into heterostructures offers tantalizing possibilities to derive new functions and structures. Recently, we have fabricated freestanding 2D oxide membranes using the water-soluble perovskite Sr3Al2O6 as a sacrificial buffer layer. Here, with atomic-resolution spectroscopic imaging, we observe that direct growth of oxide thin films on Sr3Al2O6 can cause complete phase transformation of the buffer layer, rendering it water-insoluble. More importantly, we demonstrate that an ultrathin SrTiO3 layer can be employed as an effective barrier to preserve Sr3Al2O6 during subsequent growth, thus allowing its integration in a wider range of oxide heterostructures.

Barrier layer for correlated electron material

Abstract: Subject matter disclosed herein relates to correlated electron switch devices, and relates more particularly to one or more barrier layers (615, 625) having various characteristics formed under and/or over and/or around correlated electron material (620)

Electrophoretic Deposition of Gadolinium‐doped Ceria as a Barrier Layer on Yttrium‐stabilized Zirconia Electrolyte for Solid Oxide Fuel Cells

Abstract: Replacing the electronically conductive (LaSr)MnO3±δ (LSM) cathode in the LSM/yttrium-stabilized zirconia (YSZ) system with the mixed ion-electron conductive (MIEC) (LaSr)(CoFe)O3–δ will promote cathode performance in solid oxide fuel cells (SOFCs) significantly. However, a barrier layer between LSCF and YSZ is necessary for preventing chemical reaction between these two components. In this study, a gadolinium-doped ceria (GDC) barrier layer was deposited on the YSZ electrolyte by scalable and cost-effective electrophoretic deposition (EPD). Polypyrrole (PPy) was coated on the YSZ surface as the conductive agent. A highly compact GDC green layer was obtained by the EPD process in an ethanol-based suspension. GDC barrier layers ranging in thickness from 5 µm to 8 µm were successfully densified at temperatures as low as 1,300 °C. The performance of these cells was evaluated using a symmetrical cell configuration through electrochemical impedance spectroscopy (EIS). Ohmic resistance of the GDC barrier layer made by EPD versus the conventional spin-coating method was reduced by 0.09 Ω cm2 at 750 °C, which generally accounts for 30% of the total ohmic resistance for the electrode-supported fuel cells (0.30 Ω cm2). This result suggests that EPD is a highly desirable method for efficiently manufacturing an electrolyte barrier layer with improved performance.

Partial oxidation of the absorber layer reduces charge carrier recombination in antimony sulfide solar cells.

Abstract: We investigate the effect of a post heat treatment of the absorber layer in air for antimony sulfide (Sb2S3) sensitized solar cells. Phenomenologically, exposing the Sb2S3 surface of sensitised solar cells to air at elevated temperatures is known to improve device performance. Here, we have investigated the detailed origins of this improvement. To this end, samples were annealed in air for different time periods and the build-up of an antimony oxide layer was monitored by XPS. A very short heat treatment resulted in an increase in power conversion efficiency from η = 1.4% to η = 2.4%, while longer annealing decreased the device performance. This improvement was linked to a reduction in charge carrier recombination at the interface of Sb2S3 with the organic hole conductor, arising from the oxide barrier layer, as demonstrated by intensity modulated photovoltage spectroscopy (IMVS).

Flexible transparent barrier film and preparation method thereof

Abstract: The invention relates to an optical thin film, and particularly relates to a flexible transparent barrier film and a preparation method thereof, so as to solve the problems that low transmittance is likely to happen to a composite barrier film and barrier performance generated after rolling drops. The barrier film comprises a flexible substrate; a barrier layer is arranged on the flexible substrate; a protection layer is arranged on the barrier layer; the flexible substrate is a transparent thin film; the barrier layer comprises at least two organic layers and at least two inorganic layers; the organic layers and the inorganic layers are arranged alternately; and the flexible substrate is connected with the organic layers in the barrier layer. The flexible transparent barrier film has good transmittance, and the barrier performance is still excellent after multiple times of rolling.

Packaging structure of OLED device and preparation method for packaging structure, and metal mask plate

Abstract: The invention discloses a packaging structure of an OLED device and a preparation method for the packaging structure, and a metal mask plate. The packaging structure of the OLED device comprises a plurality of alternate barrier layers and buffer layers above the OLED device; at least one barrier layer adopts a patterned structure; and a patterned region of the barrier layer is filled with the corresponding buffer layer. By setting the barrier layer into the pattered structure and by filling the patterned region of the barrier layer with the corresponding buffer layer, when the OLED device is bent, the bending stress on the barrier layer can be released by the buffer layer is which is arranged in the patterned region of the barrier layer in a filling way, so that bending stress on the barrier layer can be lowered, the OLED device can be bent for a higher amplitude, and the bending performance of the OLED device is further improved.