Showing papers on "BCH code published in 1980"

Determining the burst-correcting limit of cyclic codes

Abstract: Two new computationally efficient algorithms are developed for finding the exact burst-correcting limit of a cyclic code. The first algorithm is based on testing the colmn rank of certain submatrices of the parity-check matrix of the code. An auxiliary result is a proof that every cyclic (n,k) codes with a minimum distance of at least three, corrects at least all bursts of length \lfloor (n - 2k + 1)/2 \rfloor or less. The second algorithm, which requires somewhat less computation, is based on finding the length of the shortest linear feedback shift-register that generates the subsequences of length n - k of the sequence formed by the coefficients of the parity-check polynomial h(x) , augmented with \lfloor (n-k)/2 \rfloor -1 leading zeros and trailing zeros. Tables of the burst-correcting limit for a large number of binary cyclic codes are included.

Two applications of cyclotomic cosets to certain BCH codes (Corresp.)

Abstract: A more accurate designed distance bound is given for a subclass of narrow-sense primitive Bose-Chaudhuri-Hocquenghem (BCH) codes for which Mann has found the number of information digits. It is also determined when two consecutive odd integers are in the same cyclotomic coset.

On the minimum distance of some BCH codes (Corresp.)

Abstract: Some new examples of binary Bose-Chaudhuri-Hocquanghen (BCH) codes of length 255 are found for which the minimum distance and designed distance agree.

Superimposed concatenated codes (Corresp.)

Abstract: A family of codes of length n=q^{s+l} over GF( q ), with 2s \leq q are presented which are constructed by superimposing concatenated codes on a concatenated code. The rate r and the distance ratio \delta of the new codes satisfy the relation r=1-\delta+\delta \ln (\delta) for sufficiently large values of n and q/s . The new codes are superior to the comparable Bose-Chaudhuri-Hocquenghem (BCH) codes, for s\geq 3 , in the sense that they contain more codewords. An asymptotically good code constructed using these new codes has a distance ratio greater than those of other asymptotically good codes known to the authors for rates smaller than 0.007.

B.S.T.J. brief: Serial coding for cyclic block codes

Abstract: In 1972 the concept of seriol encoding and decoding for single, error correcting BCH codes was introduced.1,2 In this note, the concept of serial encoding and decoding is generolized and the timing diagrams are presented for a typical (n, k) cyclic block code. The implementation in conventional tecnology uses only one exclusive-OR gate and is presented for all (n - k) order generator polynomials for any code n bits long. The implementations presented are valid for all eyclic block encoders and for all decoders with single error correction with multiple error detection capability.

Decoder circuit for bch code

Abstract: PURPOSE:To shorten a decoding processing time by composing a circuit for the polynominal calculation of the number of error locations and error-bit-position calculation of a conversion table between vector expression codes of elements in a Galois field and powers, adder-subtracter circuit and register. CONSTITUTION:To decode a two-element BCH code, syndrome Sj is calculated by received code polynominal expression r(X). Syndrome Sj is inputted to the calculation circuit for coefficient (sigmaj) of the polynominal expression of error location composed of registers REG1 to REG7, adder circuit ADD, and exclusive-OR circuit EXOR. This circuit is provided with both-way conversion tables TB1 and TB2 between vector expression code (a ) of element (a) in the Galois field and power (k), and multiplication is substituted by addition. Similarly, coefficient (sigmaj) is inputted to the error-bit-position calculation circuit consisting of registers REG8 to REG11, ADD, EXOR, and conversion tables TB1 and TB2; error bit position (k) is calculated and after it is discriminated by decision circuit CHK, the code error of a received-code sequence r(X) stored in REG11 is corrected, thereby outputting decoding output s(X).

A robust, adaptive transform coder for 9.6 kb/s speech transmission

Abstract: This paper will describe the design of a robust 9.6 kb/s speech transmission system which degrades slowly under high error rate conditions. The system is based upon a combination of adaptive transform coding (ATC) principles and a vocoder-driven strategy (VDS) proposed by previous authors and operates in real-time on a commercially available array processor (1), (3). The channel error protection process utilizes a fixed block length BCH code on a rank ordered message list composed of discrete cosine transform (DCT) coefficients and side band information. The resultant system exhibits little degradation at 1 percent channel error rates and is not degraded perceptually by inaccurate pitch estimation.