Showing papers on "BCH code published in 1982"

Introduction to the Theory of Error-Correcting Codes

Abstract: Introductory Concepts. Useful Background. A Double--Error--Correcting BCH Code and a Finite Field of 16 Elements. Finite Fields. Cyclic Codes. Group of a Code and Quadratic Residue (QR) Codes. Bose--Chaudhuri--Hocquenghem (BCH) Codes. Weight Distributions. Designs and Games. Some Codes Are Unique. Appendix. References. Index.

On the Probability of Undetected Error for Linear Block Codes

Abstract: The problem of computing the probability of undetected error is considered for linear block codes used for error detection. The recent literature is first reviewed and several results are extended. It is pointed out that an exact calculation can be based on either the weight distribution of a code or its dual. Using the dual code formulation, the probability of undetected error for the ensemble of all nonbinary linear block codes is derived as well as a theorem that shows why the probability of undetected error may not be a monotonic function of channel error rate for some poor codes. Several bounds on the undetected error probability are then presented. We conclude with detailed examples of binary and nonbinary codes for which exact results can be obtained. An efficient technique for measuring an unknown weight distribution is suggested and exact results are compared with experimental results.

Error correcting system

Abstract: An error correcting system uses an error location polynominal defined by double correction BCH codes each consisting of the elements of Galois field GF(2m), thereby to generate error locations σ1 and σ2 and error patterns e, and e2. The system has a first data processing system (401) for performing only additions and multiplications to generate error locations σ1 and σ2 and a second data processing system (402) for performing only additions and mutiplica- tions to generate error patterns e1 and e2. The first data processing system (401) comprises a syndrome generator (41), a memory (43), an arithmetic logic unit (44), registers (45A) to (45C), latch circuits (46A) to (46F), registers (47A) to (47F), adder circuits (48A) and (48B) and a zero detector (49). The second data processing system (402) comprises a gate circuit (50), latch circuits (46H) and (46G), an arithmetic logic unit (44), registers (45A) to (45C) and a memory (43).

A Comparison of Block and Convolutional Codes in ARQ Error Control Schemes

Abstract: ARQ methods of error control can considerably improve the reliablity of data transmission in such areas as satellite communications, computer networks, etc. A number of ARQ schemes using both block and convolutional codes have appeared in the literature. In this paper, the following problem is addressed. Given two different implementations of an ARQ scheme, one using a block code and the other using a convolutional code, such that the bit error probability of both implementations does not exceed some specific value, which implementation has the higher throughput and under what conditions will it be attained? The comparison is made for three basic retransmission schemes using both hybrid and pure ARQ: stop-and-wait, go-back- N , and selective repeat. Numerical estimates of the throughput were obtained using approximate theoretical expressions for BCH codes and simulation results for sequential decoding of rate 1/2 convolutional codes. Parameters optimizing the performance of both block and convolutional codes for different channel conditions and round trip delays were found and were used to obtain these numerical estimates. Comparison of the quantitative results indicates a trend toward preferring convolutional codes as delay and/or block length increases. A binary symmetric channel with noiseless feedback was assumed. Possible implications for the Gaussian channel are also discussed.

System for the transmission of digital information signals

Abstract: 1. System for the transmission of digital information signals, especially for digital sound transmission by satellites, having an encoder at the sending side and a decoder at the receiving side, in which the information signals to be transmitted are combined with a generator polynomial at the sending side in such a way that check places are associated with the information signals to be transmitted which are established from an arithmetical combination of the information signal with the generator polynomial, characterized in that a primitive BCH - code is used having the block length of 63 bits an 18 check places, of which the generator polynomial x**18 + x**17 + x**16 + x**15 + x**9 + x**7 + x**6 + x**3 + x**2 + x**1 + 1 is multiplicatively combined with the further generator polynomial x + 1, so that a generator polynomial for the encoder x**19 + x**15 + x**10 + x**9 + x**8 + x**6 + x**4 + 1 arises having a block length of 63 bits and 19 check places, so that at the receiving side as a result of the use of different decoding strategies there is carried out the correction of three errors and the recognition of four errors or the correction of two errors and the recognition of five errors or the correction of one error and the recognition of six errors or the recognition of seven errors, whereby the error recognition is used for the initiation of an error concealment measure.

Circuit for checking bit errors in a received bch code succession by the use of primitive and non-primitive polynomials

Abstract: For use in deciding whether a single or a t-tuple error (t being greater than unity) is present in each bit sequence given as a primitive BCH code in accordance with a generator polynomial comprising a primitive and a non-primitive polynomial, an error checking circuit comprises first and second dividers (16,17) for dividing each bit sequence by the primitive and the non-primitive polynomials to provide first and second signals, respectively. if the bit sequence includes only a single error, the first signal represents one of non-zero residues which result by the division when such single errors are present at the respective bit locations of the sequence. A memory (18) is preliminarily loaded with reference numbers corresponding to the respective non-zero residues and produces one of the reference numbers in response to the first signal only in the presence of a single error. A comparator (19) compares the produced reference number with a residue represented by the second signal to carry out the decision. Preferably, the memory is loaded also with the single error bit locations to locate the single error in a bit sequence being checked. The circuit may be a microcomputer operable in the above-described manner.

Error correcting system for correcting two or three simultaneous errors in a code

Abstract: An improved two or three error correcting system for BCH code (Bose, Chaudhuri, Hocquenghem code) has been found. In case of a two error correction system, a first syndrome A 1 and a second syndrome A 2 are obtained from a reception code C'=(a 1 ', a 2 ', . . . , a n '): ##EQU1## Then, S 1 =A 1 +α n-t , and S 2 =A 2 +α 3 (n-t) are obtained, for every value of t, where n is a code length, t is an integer equal to or less than n, and α is a primitive element of a Galois field. When A 1 ≠0, a t'th bit a t ' is corrected by inverting the same on the condition that the t'th bit of S 2 is equal to the t'th bit of S 1 3 . When A 1 =0, it is clear that no error exists, and no correction is performed. In case of a three error correction system, a third syndrome ##EQU2## and S 3 =A 3 +α 5 (n-t) are obtained further for every value of t, and a correction is performed by inverting the t'th bit according to the value of EL(t)=S 1 6 +S 2 2 +S 1 3 S 2 +S 1 S 3 when A 1 3 +A 2 ≠0, or the value of S 1 when A 1 3 +A 2 =0. The structure of the present system is simple since said values S 2 , S 3 and EL(t) are obtained merely by a ROM table and an exclusive-OR circuit.

Decoding method for triple or quadruple error correction bch code

Abstract: PURPOSE:To achieve decoding efficiently by obtaining a syndrome from a triple and a quadruple error BCH code, and finding a solution of an error position polynomial by using a table of roots of a Galois equation stored in an ROM. CONSTITUTION:A received BCH code is supplied to a syndrome generating circuit SGL to find a syndrome, and exponent display of vectors from an ROME.2 is performed. Syndromes S1, S3 and S5 are used to generate an error position polynominal containing an added constant term, and the polynominal is inputted to an ROM2.5 to find a root which corresponds to the constant by using a table of a quadratic equation; and it is inputted from the upper side of a switch SWA8 to an error correcting circuit ECC10, thereby correcting an error including <=2 bits. When a three-bit error is discriminated by the constant terms of a position polynomial, the switch SWA8 is placed on the lower side, and roots are found by a ROM3.6 stored with a table of roots of a cubic equation, an ROM4 for finding a square root, an ROMC.7 for finding a cubic root, etc., thus correcting a three-bit error.

Transform Decoding of Reed-Solomon Codes. Volume I. Algorithm and Signal Processing Structure

Abstract: : One of the continuing concerns of the Low Cost Electronics project is the application of new technology to the implementation of error-correcting codes for reliable data communication. Our interest stems from the need for low- cost hardware to implement error-correction codes that exhibit significant coding gain on interference-resistant communication channels. Previous studies of coding gain led us to concentrate work on the implementation of the Reed- Solomon class of generalized BCH codes. This class of codes, although well- suited to the correction of both isolated random errors and random error bursts because of its optimum distance properties, continues to be genuinely in need of efficient decoding algorithms implemented by low-cost hardware. This report discusses in detail a transform decoding algorithm and its hardware implications, for the Reed-Solomon codes, that offer major simplifications relative to the conventional BCH decoding algorithm. A fast algorithm for encoding and syndrome computation is described. Modification of the error location process to accommodate erasures is also described. Also discussed are hardware implementation issues with a summary of design features and parameters to be incorporated in a future set of programmable integrated circuits for decoding a large number of Reed-Solomon codes.

Time-division multiplex data transmitting method

Abstract: PURPOSE:To lower the cost of a receiver, by using a receiver that works on the clock of a low frequency when the transmitting data series is received. CONSTITUTION:A PCM data series is supplied to error correcting encoders 49- 60, and the coding of error correction is carried out for each channel. For instance, a block code obtained by combining a BCH code and a parity code is used for an error correction code. The output data series of encoders 49-60 are supplied to synchronism adding circuits 61-72, and the block synchronous signals are added. In such way, the redundant bits for the error correction and for the synchronism are added to 1-12 channels each and then supplied to a multiplexer 73 to receive the time-division multiplication. Accordingly an error correction is possible for the receiving data of a desired channel at the receiver side with a bit rate lower enough than the bit rate of the transmission mode.

Decoder of double error correction code

Abstract: PURPOSE:To realize the miniaturization of the titled decoder, by decreasing sufficiently the number of words of an ROM table and using a simple decoder to the double correction BCH code. CONSTITUTION:The 1st syndrome producing circuit 102 produces the 1st syndrome A1 from the received code; and the 2nd syndrome producing circuit 104 produces the 2nd syndrome A2. An error correction inhibiting circuit 113 detects the conditions by which the bit trains of the syndrome A1 are all 0. At the same time, a bit train 1 which shows the original alpha of a Galois master is produced to the subject of each inspection within a code word, and a bit train 2 showing the original[alpha ]of a cube of the train 1 is produced. In addition, the following circuits are provided: a circuit produces a bit train 3 showing the original (S1=A1+alpha of the Galois matter; a circuit that produces a bit train 4 showing the original cube (S3=S1 ) of the Galois matter; and a circuit that produces a bit train 5 showing the original[S2=A2+alpha ]respectively. A comparator 112 compares the originals of the Galois matters between the trains 4 and 5 to perform a correction of error.

Compression system for intermediate tone signal

Abstract: PURPOSE:To minimize the deterioration of video quality due to compression, by compressing the combination of codes for 2 video elements' share of an intermediate tone signal in which one video element is represented with one tone out of a plurality of tones into a fixed length code shorter than the code length for two video elements' share. CONSTITUTION:An intermediate tone video signal read-in from an original is written in a random access memory 3 with a read-in circuit 1. The data from the random access memory 3 is transmitted to a code conversion circuit 4 and a microcomputer 5. The data in 8-bit inputted to the code conversion circuit 4 is compressed into data in 7-bit under the control of the microcomputer 5, inputted to a shift register 7, and a data in 7-bit is transmitted to a BCH processing circuit from the shift register 7 as a transmission data SD. In a code conversion circuit 4, the combination of codes for two video elements' share of intermediate tone signals in which one video element is represented with one tone out of a plurality of tones, is compressed into a fixed code length shorter than the code length for two video elements' share.