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Showing papers on "BCH code published in 1983"


Journal ArticleDOI
TL;DR: A new lower bound for the minimum distance of a linear code is derived and when applied to cyclic codes both the Bose-Chaudhuri-Hocquenghem (BCH) bound and the Hartmann-Tzeng (HT) bound are obtained as corollaries.
Abstract: A new lower bound for the minimum distance of a linear code is derived. When applied to cyclic codes both the Bose-Chaudhuri-Hocquenghem (BCH) bound and the Hartmann-Tzeng (HT) bound are obtained as corollaries. Examples for which the new bound is superior to these two bounds, as well as to the Carlitz-Uchiyama bound, are given.

96 citations


Journal ArticleDOI
TL;DR: A new algorithm for soft-decision decoding is presented, simplifying the correlation scheme by selecting certain codewords and decreasing decoding complexity by using erasure information.
Abstract: Correlation decoding is an optimal scheme of soft-decision decoding for error-correcting codes in the sense of minimum block-error probability. However, it is very difficult to apply the scheme when the number of information digits is large because of decoding complexity. A new algorithm for soft-decision decoding is presented, simplifying the correlation scheme by selecting certain codewords and decreasing decoding complexity by using erasure information. Any desired block-error probability between the error Probabilities of correlation and hard-decision decoding can be realized by setting up a suitable threshold value 0 for erasure decision. Computer simulation has been performed for Golay (23,12,7) code and BCH (15,7,5) code.

34 citations


Patent
15 Sep 1983
TL;DR: In this paper, the decoding of BCH multiple error correction code codewords with α as a primitive element of the finite field GF (2m) is accomplished by generating syndrome subvectors S1 from all column m-tuple αk positions and syndrome subvector S2 from all table m-touple α3K positions, and then selecting those bit positions K where S1 3 +S2 +QK=0 as the bit or bits in error.
Abstract: Decoding of BCH multiple error correction code codewords with α as a primitive element of the finite field GF (2m) is accomplished by generating syndrome subvectors S1 from all column m-tuple αk positions and syndrome subvectors S2 from all column m-tuple α3K positions, generating a permutation of syndrome subvector S1 for each bit position on the codeword and then selecting those bit positions K where S1 3 +S2 +QK=0 as the bit or bits in error.

32 citations


Journal ArticleDOI
TL;DR: A detailed description is given of a fast soft decision decoding procedure for high-rate block codes made possible by using the symmetries of the code to simplify the syndrome decoding by table look-up and by making the best use of the soft decision information.
Abstract: A detailed description is given of a fast soft decision decoding procedure for high-rate block codes. The high speed is made possible (in part) by using the symmetries of the code to simplify the syndrome decoding by table look-up and by making the best use of the soft decision information. The (128,106,8) BCH code is used as an example.

17 citations


Patent
28 Jan 1983
TL;DR: In this article, the 1st, 2nd and 3rd error detection circuits were used to simplify the constitution of a device and to decode a coded word in a short time, by using a shift register from the coded word of 3-error correction BCH and correcting the error with the primitive element of the Galois field.
Abstract: PURPOSE:To simplify the constitution of a device and to decode a coded word in a short time, by obtaining the 1st, 2nd and 3rd syndrome through the use of a shift register from the coded word of 3-error correction BCH and correcting the error with the primitive element of the Galois field of the element. CONSTITUTION:The 1st, 2nd and 3rd syndromes A1, A2 and A3 are outputted from the 1st, 2nd and 3rd syndrome producing circuits 102, 104 and 106 by using a data buffer 101 consisting of shift registers for an input data (a). Further, a correction condition discriminating circuit 108 discriminates if A1 +A2 is zero and a bit number (t) taking S1=A1+alpha as zero is applied to a selection circuit 117. The 1st and 2nd error detection circuits 115 and 116 discriminate if A1 +A2not equal to 0, bit trains S1, S2 and S3 are taken as equation 1, an input bit corresponding to values t1, t2, t3, up to three, of a bit number (t) giving EL(t) is inverted, the others are outputted as they are, and three errors are corrected at an error correction circuit 118.

4 citations


Proceedings ArticleDOI
01 Dec 1983
TL;DR: It is suggested that the availability of very high density integrated circuits will be changing the approach and emphasis to several problems in estimation and control, and the minimality of realizations will be less significant than their modularity, local interconnectedness, area time complexity measures, etc.
Abstract: : The theme of this lecture is that the availability of very high density integrated circuits will be changing our approach and emphasis to several problems in estimation and control. For example, the minimality of realizations will be less significant than their modularity, local interconnectedness, area time complexity measures, etc. Similarly, good algorithms for serial processing may be poor candidates for parallel implementation. While it is hard for me in mid-August to predict exactly what I shall say in the lecture in mid-December, I think it might be useful to provide in written form some of the background material on which a good part of may talk will be based. Thus, at this meeting at least, I plan to illustrate the above points by several examples, including: (1) description of a parallel architecture for the measurement update step (in triangular array form) of the Kalman filter; (2) development of the Schur algorithm as a better candidate than the Levinson algorithm for VLSI implementation of Toeplitz equation solvers; (3) comparison of the Berlekamp-Massey-Rissanen and Lanczos algorithms in the problems of partial realization and of the decoding of BCH codes; and (4) development of minimal, but pipelined and orthogonally-cascaded, implementations of time-invariant, finite-dimensional (ARMA) systems.

2 citations


Patent
03 Aug 1983
TL;DR: In this paper, a local call collator of ROMs and logical elements was proposed to eliminate the need for a flip-flop, shift register, etc., and to realize size reduction, mass-production, and low power consumption.
Abstract: PURPOSE:To eliminate the need for a flip-flop, shift register, etc., and to realize size reduction, mass-production, and low power consumption, by composing a local call collator of ROMs and logical elements while utilizing the nature of BHC codes. CONSTITUTION:A local selective call code consisting of a BHC code is stored in an external ROM2, and plural selective call codes E, F, and G consisting of the local selective call code A and BCH codes having a small number of different specific bits are stored in ROMs 5, 6, and 7. For the local selective call codes A, B, C, and D, a specific expression holds on the basis of the nature of the BCH code. The codes A, E, F, and G read out by address signals a1- a8 are supplied, bit by bit, to exclusive OR circuits 19-21 by clock signals b1-b4 to perform operations based upon the specific expression and when exclusive OR circuits 23-26 decide on coincidences between the codes B, C, and D from a code generator 3 and an input signal IN, a local code is allowed.

2 citations


Journal ArticleDOI
TL;DR: In this article, a new construction method of extended codes based on BCH code using a Fourier transform over a finite field is proposed, which applies encoding to a so-called "tail" which is added for extension and furthermore repeats similar encoding to the encoded tail.
Abstract: This paper proposes a new construction method of extended codes based on BCH code using a Fourier transform over a finite field. This method applies encoding to a so-called “tail” which is added for extension and, furthermore, repeats similar encoding to the encoded tail. the constructed codes based on primitive BCH codes generally are excellent in the point of code rate (= number of information symbols/code length) and it is clarified through examples that some of them improve the lower bounds of the maximum code rate. Since the extended codes constructed by this method can generally be considered over an extended field of one degree lower order compared with the shortened codes with the same code length, the number of multiplications needed for syndrome-calculation in decoding can be reduced to about a fourth. Moreover, it is shown that when the code is constructed by this method, the fast Fourier transform algorithm can be applied to a wider range of code lengths than before in syndrome-calculation.

Journal ArticleDOI
TL;DR: This paper presents a procedure for the construction of linear block codes derived from cyclic subspaces whose distance properties are determined indirectly by the BCH bound despite the fact that they are not cyclic.
Abstract: This paper presents a procedure for the construction of linear block codes derived from cyclic subspaces. The distance properties of these codes are determined indirectly by the BCH bound despite the fact that they are not cyclic.

Journal ArticleDOI
Kai-Ping Yiu1
01 Apr 1983
TL;DR: The proposed method for the root computation of a polynomial can be very useful to the high-speed BCH and Reed-Solomon decoding operations.
Abstract: A method is proposed to compute the roots of a polynomial with degree four or less over a finite field. This method requires less computations and memory requirements than other methods, and it can achieve high-speed root computation. The proposed method for the root computation of a polynomial can be very useful to the high-speed BCH and Reed-Solomon decoding operations.

01 Jun 1983
TL;DR: In this paper, some shortened BCH codes for possible applications to large IC random access memory systems are presented, which are given by their parity-check matrices, and the encoding and decoding of these codes are discussed.
Abstract: In this report some shortened BCH codes for possible applications to large IC random-access memory systems are presented. These codes are given by their parity-check matrices. Encoding and decoding of these codes are discussed.