Showing papers on "BCH code published in 1989"

Construction and decoding of a class of algebraic geometry codes

Abstract: A class of codes derived from algebraic plane curves is constructed. The concepts and results from algebraic geometry that were used are explained in detail; no further knowledge of algebraic geometry is needed. Parameters, generator and parity-check matrices are given. The main result is a decoding algorithm which turns out to be a generalization of the Peterson algorithm for decoding BCH decoder codes. >

An Introduction to Error Correcting Codes with Applications

Abstract: 1 Introduction and Fundamentals.- 2 Finite Fields.- 3 Linear Codes.- 4 Some Special Linear Codes.- Chapters 5 Cyclic Codes.- 6 BCH Codes and Bounds for Cyclic Codes.- 7 Error Correction Techniques and Digital Audio Recording.- A: Review of Vector Spaces.- B: The Division Algorithm and the Euclidean Algorithm.- C: The Chinese Remainder Theorem.- D: Field Representations and Zech's Log Tables.- References.

A generalized Euclidean algorithm for multisequence shift-register synthesis

Abstract: The problem of finding a linear-feedback shift register of shortest length capable of generating prescribed multiple sequences is considered. A generalized Euclidean algorithm, which is based on a generalized polynomial division algorithm, is presented. A necessary and sufficient condition for the uniqueness of the solution is given. When the solution is not unique, the set of all possible solutions is also derived. It is shown that the algorithm can be applied to the decoding of many cyclic codes for which multiple syndrome sequences are available. When it is applied to the case of a single sequence, the algorithm reduces to that introduced by Y. Sugiyama et al. (Inf. Control, vol.27, p.87-9, Feb. 1975) in the decoding of BCH codes. >

Shift correcting code for channel encoded data

Abstract: Channel encoded data (for example run length limited encoded data) is further encoded in accordance with a shift correction code prior to transmission. Upon reception, forward and backward shift errors present in the received channel encoded data are corrected by a shift correction decoder. The shift error correction is accomplished using a code, such as (for example) a BCH code over GF(p) or a negacyclic code, which treats each received symbol as a vector having p states. For a single shift error correction, p=3 and there are three states (forward shift, backward shift, no shift). In one embodiment, conventional error correction codewords which encode the user data may be interleaved within successive shift correction codewords prior to channel encoding, thereby enabling the error correction system to easily handle a high rate of randomly distributed shift errors (which otherwise would result in a high rate of short error bursts that exceed the capacity of the block error correction code).

High data rate BCH encoder

Abstract: An encoder for selected linear error correcting codes, such as a BCH code, uses relatively low-speed circuitry to generate parities for correcting the code. A parity matrix derived from the BCH generator matrix is provided as data to a generator vector whereby the generator vector is used as a logical shift function generator. When the logical shift function is applied to the rows of the parity matrix, columns of parity are shifted into an EXCLUSIVE-OR tree to produce the parity bit of the column. The parity bit of the column is then injected into a data stream forming the encoded symbol for transmission, attaching the parity word following the data word. The apparatus may be constructed making maximum use of the standard, commerically available, relatively low-cost integrated circuits, but it is nevertheless capable of operating at speeds in excess 1 GBPS.

Diversity selection using coding in a portable radio communications channel with frequency-selective fading

Abstract: It is shown that the degradation in the performance of wideband digital transmission systems due to intersymbol interference can be reduced by utilizing diversity selection using coding A BCH (31, 21, 5) double-error-correcting code and QPSK (quadrature-phase-shift-keying) modulation with coherent detection are used for this study The probability of word error is taken to be the measure of system performance Analytic expressions are derived for the word error probability; these expressions simplify the simulation processes It is found that a diversity selection algorithm using coding can reduce the floor of word error probability, and hence increase the dynamic range of received power before the word error probability reaches that floor >

High-speed hardware decoder for double-error-correcting binary BCH codes

Abstract: Presents a new hardware decoder for double-error-correcting binary BCH codes of primitive length, based on a modified step-by-step decoding algorithm. This decoding algorithm can be easily implemented with VLSI circuits. As the clock rate of the decoder is independent of block length and is only twice the data rate, the decoder is suitable for long block codes working at high data rates. The decoder comprises a syndrome calculation circuit, a comparison circuit and a decision circuit, which can be realised by linear feedback shift registers, ROMs and logical gates. The decoding algorithm, circuit design and data processing sequence are described in detail. The circuit complexity, decoding speed and data rate of the new decoder are also discussed and compared with other decoding methods.< >

Apparatus for detecting uncorrectable error patterns when using Euclid's algorithm to decode Reed-Solomon (BCH) codes

Abstract: A Reed-Solomon Galois Field Euclid algorithm decoder determines whether an error is uncorrectable by checking for: I. deg [Λ(x))]≦t II. deg [Ω(x)]

Error bounds in the averaging of hybrid systems

Abstract: The authors analyze the error introduced by the averaging of hybrid systems. These systems involve linear systems which can take a number of different realizations based on the state of an underlying finite state process. The averaging technique (based on a formula from Lie algebras known as the Backer-Campbell-Hausdorff (BCH) formula) provides a single system matrix as an approximation to the hybrid system. The two errors discussed are: (1) the error induced by the truncation of the BCH series expansion and (2) the error between the actual hybrid system and its average. A simple sufficient stability test is proposed to check the asymptotic behavior of this error. In addition, conditions are derived that allow the use of state feedback instead of averaging to arrive at a time-invariant system matrix. >

On the optimum processing gain of a block-coded direct-sequence spread-spectrum system

Abstract: The optimization between the processing gain and the coding gain of a constant-bandwidth direct-sequence spread-spectrum communication system operating in the presence of either a tone jammer or a Gaussian jammer such that the bit-error rate (BER) is minimized is presented. Both bipolar phase-shift keyed pseudo-noise (PN) modulation and quaternary phase-shift keyed PN modulation are considered. Binary BCH codes are used to illustrate the techniques for optimization. The exact BER and its Gaussian approximation are derived and compared. During the optimization, two different approaches are used to obtain the indicator functions of the optimum code. These indicators are tested and shown to yield good results. >

Apparatus for decoding bch code for correcting complex error

Abstract: An apparatus for decoding a received BCH code signal for correcting a combined complex error is disclosed which includes a syndrome generating circuit for generating two n-bit syndromes corresponding to the received signal, a syndrome converting circuit for converting the two n-bit syndromes to a 2n-bit syndrome, a random error correcting circuit, a burst error correcting circuit, two combining circuits and output selecting circuit. The random error correcting circuit receives input as the two n-bit syndromes and outputs a random error correction signal to one of the combining circuits and the burst error correcting circuit receives as input the 2n-bit syndrome and outputs a burst error correction signal to the other of the combining circuits. The combining circuits combine the correction signals with the received BCH code signal. The output selecting circuit selectively outputs one of the combined signals from the combining circuits in accordance with the decoding conditions of the error correcting circuits and the result of a comparison between the decoded and error-corrected signals from the combining circuits.

Optimum coding design for type-I hybrid ARQ error control schemes

Abstract: Crossover points in performance exist between plain ARQ, type-I and type-II hybrid ARQ as far as efficiency is concerned. To evaluate hybrid ARQ schemes, a new criterion called ‘overall throughput’ is proposed to measure performance capability. By numerical optimisation, the optimum system parameters are found for type-I hybrid ARQ with BCH error-correcting codes.

High‐speed decoding of BCH codes using a new error‐evaluation algorithm

Abstract: A new error-evaluation method for computing error values in decoding Reed-Solomon codes or nonbinary BCH codes using the Berle-kamp-Massey algorithm is proposed. Since the error-evaluator polynomial used in the new method is obtained as by-products of the computation for the error-locator polynomial, the new method is more efficient than Forney's method whose error-evaluator polynomial cannot be obtained as the by-products of the error-locator polynomial.

Apparatus for decoding bch code

Abstract: An apparatus for decoding BCH code having first, second and third circuits for generating a syndrome S1, a syndrome S3 and a parity P, respectively from a receiving sequence, a fourth circuit coupled to the first circuit for generating S1 2 from the syndrome S1, a fifth circuit coupled to the first circuit, second circuit and fourth circuit for generating (S1 3 +S3), a Chien search circuit which includes a first generating circuit supplied with the S1 and S1 2 for generating a first stage of error-location polynomial A, where A=S1α -2n +S1 2 α -n , and a second generating circuit supplied with the (S1 3 α+S3) and the A for generating a second stage of error-location polynomial B, wherein B=A+S1 3 +S3, and an error correction and detection logic circuit supplied with the S1, P, (S1 3 +S3), A and B and with a decode selection signal and a BCH code selection signal for generating an error correction or detection signal.

Effects of diversity reception on BCH-coded QPSK cellular land mobile radio

Abstract: Bit error rate performance of BCH-coded QPSK with coherent demodulation and multiple-branch selection diversity reception is calculated in the presence of fast Rayleigh fading and a cochannel interference environment. How diversity reception affects the optimum code rate and coding gain is investigated from power and spectrum efficiencies points of view.

Bit Level Soft Decision decoding reed-solomon codes

Abstract: In this paper we present a Reed-Solomon decoder that makes use of bit soft decision information. A Reed- Solomon generator matrix which possesses a certain inherent structure in GF(2) is derived. Using this structure representation of the code as a union of cosets, each coset being an interleaver of several binary BCH codes, is obtained. Such partition into cosets provides a clue for efficient bit level soft decision decoding. The proposed decoding algorithms are in many cases orders of magnitude more efficient than conventional techniques.

Performance evaluation of asynchronous random access CDMA with block FEC coding

Abstract: The authors present an analysis of asynchronous random access packet CDMA (code-division multiple-access) channels with block FEC (forward error correction) coding. A procedure for calculating the error probability of an L bit packet in the variable message length, multiuser CDMA environment is presented. This procedure is used in conjunction with appropriate flow equilibrium traffic models to compute performance measures such as throughput and delay. Using as an example a direct sequence spread-spectrum multiple-access system with BCH block coding for FEC, the analytical model is used to obtain throughput vs. channel traffic curves over a range of code rates, leading to an assessment of maximum achievable throughput and the associated optimum FEC code rate. The results show that the use of block FEC coding provides a significant improvement in the normalized net channel throughput, approach values which are competitive with those for nonspread-spectrum ALOHA-type random access channels. >

Comparison of the Motorola DSP56000 and the Texas Instruments TMS320C25 digital signal processors for implementing a four error correcting (127,99) BCH error control code decoder

Abstract: The Motorola DSP56000 and the Texas Instruments TMS320C25 digital signal processors are compared on the basis of their use in implementing a four error correcting (127,99) BCH code decoder. The code is being used as a basis for comparing various decoder implementations. Algorithms for efficient microprocessor implementations of a decoder are presented. The ability to implement time-critical steps in these algorithms is the basis for comparing the DSP56000 and the TMS320C25. The DSP56000's comparatively general-purpose architecture and certain unique features provide a higher bit rate decoder than can be implemented on the TMS320C25. Assembly language programs have been written and tested for performance and timing using IBM PC-based simulators of the processors. A complete decoder has been implemented on the DSP56000, achieving an average bit rate in excess of 1 million b/s. >

Comparison of the Motorola DSP56000 and the Texas Instruments TMS320C25 Digital Signal Processors for Implementing a Four Error Correcting (127,33) BCH Error Control Code Decoder

Abstract: This paper compares the Motorola DSP56000 and the Texas Instruments TMS320C25 digital signal processors based on their use in implementing a four error correcting (127,993 BCII code decoder. The code is being used as a basis for comparing various decoder implementations. This paper presents algorithms for efficient microprocessor implementations of a decoder. The ability to implement time critical steps in these algorithms is the basis for comparing the DSP5G000 and ThIS320C25. The DSP5G000’s comparatively general purpose architecture and certain unique features provide a higher bit rate decoder than can he in~plemented on the TMS320C25. Assembly language programs have been written and tested for performance and timing using IBM PCbased simulators of the processors. A complete decoder has been implemented on the DSP56000, achieving an average bit rate in excess of 1 million hits per second.

Performance of fast frequency hopped noncoherent MFSK with a fixed hop rate under worst case jamming

Abstract: The authors evaluate the throughput performance of FFH/MFSK (fast frequency hopping/M-ary frequency-shift keying) with a fixed hop rate for both uncoded and coded systems. The performance criterion used is a throughput measure, that is information rate sustained by a system for a given bit-error rate normalized by the hop rate. It is shown that the performance can be greatly improved through the use of coding. As with a fixed data rate, multitone jamming is more effective for M>2, and partial-band-noise jamming for M=2. However, the optimum M is a monotonic increasing function of E/sub h//J/sub O/. This affects the choice of a code if it is related to M, such as a dual-K code. The best convolutional codes are the rate 1/2 Trumpis code, the semiorthogonal code for K=3, and the dual-K codes. The best block codes are the (255,221) RS code, the (255,207) BCH code, and the (63,53) RS code, in that order. As with a fixed data rate, the best convolutional codes perform better than the best block codes. >

Circuit for solving error position polynomial

Abstract: PURPOSE:To obtain a solution circuit for an error position polynomial with a simple circuit constitution, by providing an addition means which outputs a root on the other side by adding the root on one side from a storage means and an inputted coefficient. CONSTITUTION:In a ROM11, the roots x2 corresponding to the coefficients delta1 and delta2 of the error position polynomial of a double error reed solomon or a BCH code expressed in equation are stored. By inputting the coefficient delta1 from an input terminal T1 and inputting the coefficient delta2 from an input terminal T2, the ROM11 outputs the roots x2 corresponding to the values of the coefficients delta1 and delta2 to an adder 12 and an output terminal T4. Meanwhile, the adder 12 performs addition on a Galois field GF2 setting the coefficient delta1 from the terminal T1 and root x2 that is the output of the ROM11 as input, and outputs the root x1 to a terminal 3. In such a way, it is possible to constitute the solution circuit for the error position polynomial by a storage device and an adder, and to simplify the circuit. In equation, (x) represents an error position and S1-S4, syndromes.

Error correcting circuit

Abstract: PURPOSE:To realize the function of an error position reference table by using a decoder which defines the residue signal of a division circuit as its input and switching the connections to secure the correspondence between the output of the decoder and a bit position where an error should be corrected CONSTITUTION:N and A are defined as a positive integer of >=2 and a positive integer of >=1 respectively The block bit length of a single block of a code is set at (2N-1-A) bits or (2N-A) bits together with the information bit length within said single block is set at (2N-1-A-N) bits Then the BCH code or the humming code that is encoded by means of an N-degree generating polynomial is defined as an input signal The residue signal consisting of N bits obtained by dividing said input signal by the frequency equal to said block bit length with use of said polynomial is supplied to a decoder 16 having its input of N bits and output of 2N bits or (2N-1) bits Then the output of this decoder is used as the error bit position data of said input signal

System devices and algorithm for the error correction in digital transmissions with "bch" coding/decoding

Abstract: For the error correction in digital transmissions using the so called "BCH" coding/decoding technics, the received data stream is processed by means of a modified version of the algo-rithm of BCH correction, represented by the iterative equations (1), (2) and (3') referred in the present description. The calculation of syndromes and of the error locator polynomial requires only multiplications by a constant factor or by a bit and addition. Hardware implementation is greatly symplified by eliminating the need of a two factor Galois field multiplier.

Efficient double asymmetric error correcting codes

Abstract: Two constructions for double-asymmetric-error-correcting codes are given. These codes offer some desirable properties for optical communication, where it is important that most codewords have small weights. The first construction gives a subset of a double-error-correcting BCH code. The code offers considerable improvement in the weight distribution at the expense of one extra bit of redundancy (in almost all cases) over the BCH code. The code is semisystematic and has the same degree of encoding/decoding complexity as the BCH code. The second construction is completely systematic and has twice the information rate as the BCH code in several cases. This code is easy to encode and decode and has fewer 1s than 0s. >

Performance of BCH and convolutional codes in direct sequence spread spectrum packet radio networks

Abstract: The authors examine the performance of BCH and convolutional codes in a direct-sequence spread-spectrum packet radio network. Packet errors are caused by a combination of noise at the receiver and interference between packet transmissions that overlap in time. The interference between packet transmissions produces dependent symbol errors at the output of the demodulator. The authors first compute an upper bound on the symbol error probability. Then they use this upper bound to calculate upper bounds on the packet error probability for both BCH and convolutional codes. The results make it possible to compare the performance of BCH and convolutional codes in the presence of multiple-access interference. >

Check method for data transmission

Abstract: PURPOSE:To improve the reliability of data transmission by adding a parity bit formed by exclusive OR of adjacent data among data of plural bits being source data and coding the result so as to apply error detection based on the value obtained through the combination of different parity bits and data at the reception side. CONSTITUTION:Data D1-D3 are source data and each consists of 8-bit. The parity bits P1-P3 in 8-bit formed by the exclusive OR of adjacent data are added among the data D1-D3. They are arranged as P1, D1, P2, D2, P3, D3 as shown in figure and they are coded and sent to the reception side. The reception side applies the decoding to them and checks the parity bit to discriminate the presence of an error. That is, when only one parity bit is correct and others are not correct, and when the value obtained from the different combination of the data and parity bit is equal, it is regarded as a correct data, which is used for the correction. Thus, after code correction is applied by BCH or Hargelburger, the code correction is applied newly among the parities and data.

Combined source-channel coding

Abstract: An approach to combined source-channel coding is presented. The method applies to a scalar source encoder designed using the Lloyd-Max algorithm and uses a family of binary primitive BCH codes. The channel model used is the binary symmetric channel. A variety of experimental results are presented which illustrate the average signal-to-noise ratio gain possible over no channel coding when different numbers of source encoder output bits are protected and the overall rate is held fixed. A number of interesting conclusions are drawn which can prove helpful in attempting to match existing source and channel coding techniques. >

A decoding method and apparatus for decoding code words that are wordwise protected by a non-binary BCH code against at least one symbol error

Abstract: There is described a decoding method and decoder apparatus for non-binary BCH-codes. Upon reception for an input word, first a syndrome information is generated. From this, the key equation is set up and solved to yield an error locator polynomial sig(z) and an error evaluator polynomial w(z). Next, on the basis of polynomial sig(z), its formal derivative polynomial sig′(z), Euclid's algorithm is used for calculating two accessory polynomials b(z), c(z), such that b(z)sig(z) + c(z)sig′(z) = 1. From these, a Lagrangian polynomial L(z) is calculated which for any inversed error location value has the associated error symbol value. The error data thereupon can be calculated by evaluating the error locator polynomial and the Lagrangian polynomial.

EfRcient Double hymmetric Error Correcting Codes

Abstract: We give two constructions for double asymmetric error correcting codes. These codes offer some desirable properties for optical communication, where it is important that most codewords have small weights. The first construction gives a subset of a double error correcting BCH code. The code offers considerable improvement in the weight distribution at the expense of one extra bit of redundancy (in almost all cases) over the BCH code. The code is semisystematic and has the same degree of encoding/decoding complexity as the BCH code. The second construction is completely systematic and has twice the information rate as the BCH code in several cases. This code is easy to encode and decode and has fewer 1’s than 0’s.