Showing papers on "BCH code published in 2004"

Coding Theory: A First Course

Abstract: Coding theory is concerned with successfully transmitting data through a noisy channel and correcting errors in corrupted messages. It is of central importance for many applications in computer science or engineering. This book gives a comprehensive introduction to coding theory whilst only assuming basic linear algebra. It contains a detailed and rigorous introduction to the theory of block codes and moves on to more advanced topics like BCH codes, Goppa codes and Sudan's algorithm for list decoding. The issues of bounds and decoding, essential to the design of good codes, features prominently. The authors of this book have, for several years, successfully taught a course on coding theory to students at the National University of Singapore. This book is based on their experiences and provides a thoroughly modern introduction to the subject. There are numerous examples and exercises, some of which introduce students to novel or more advanced material.

DVB‐S2 modem algorithms design and performance over typical satellite channels

Abstract: SUMMARY In this paper we propose a design of the main modulation and demodulation units of a modem compliant with the new DVB-S2 standard (Int. J. Satellite Commun. 2004; 22:249–268). A typical satellite channel model consistent with the targeted applications of the aforementioned standard is assumed. In particular, non-linear pre-compensation as well as synchronization techniques are described in detail and their performance assessed by means of analysis and computer simulations. The proposed algorithms are shown to provide a good trade-off between complexity and performance and they apply to both the broadcast and the unicast profiles, the latter allowing the exploitation of adaptive coding and modulation (ACM) (Proceedings of the 20th AIAA Satellite Communication Systems Conference, Montreal, AIAA-paper 2002-1863, May 2002). Finally, end-to-end system performances in term of BER versus the signal-to-noise ratio are shown as a result of extensive computer simulations. The whole communication chain is modelled in these simulations, including the BCH and LDPC coder, the modulator with the pre-distortion techniques, the satellite transponder model with its typical impairments, the downlink chain inclusive of the RF-front-end phase noise, the demodulator with the synchronization sub-system units and finally the LDPC and BCH decoders. Copyright # 2004 John Wiley & Sons, Ltd.

Small area parallel Chien search architectures for long BCH codes

Abstract: To implement parallel BCH (Bose-Chaudhuri-Hochquenghem) decoders in an area-efficient manner, this paper presents a novel group matching scheme to reduce the Chien search hardware complexity by 60% for BCH(2047, 1926, 23) code as opposed to only 26% if directly applying the iterative matching algorithm. The proposed scheme exploits the substructure sharing within a finite field multiplier (FFM) and among groups of FFMs.

Method and system for providing short block length low density parity check (ldpc) codes

Abstract: An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a short LDPC code by shortening longer mother codes. The short LDPC code has an outer Bose Chaudhuri Hocquenghem (BCH) code. According to another aspect, for an LDPC code with code rate of 3/5 utilizing 8-PSK (Phase Shift Keying) modulation, an interleaver provides for interleaving bits of the output LDPC code by serially writing data associated with the LDPC code column-wise into a table and reading the data row-wise from right to left. The above approach has particular application in digital video broadcast services over satellite.

High-speed architectures for parallel long BCH encoders

Abstract: Long BCH codes are used as the outer error-correcting code in the second generation of Digital Video Broadcasting Standard from the European Telecommunications Standard Institute. These codes can achieve around 0.6dB additional coding gain over Reed-Solomon codes with similar codeword length and code rate in long-haul optical communication systems. BCH encoders are conventionally implemented by a linear feedback shift register architecture. High-speed applications of BCH codes require parallel implementations of encoders. In addition, long BCH encoders suffer from the effect of large fanout. In this paper, novel architectures are proposed to reduce the achievable minimum clock period of long BCH encoders after the fanout bottleneck has been eliminated. For an (8191, 7684) BCH code, compared to the original 32-parallel BCH encoder architecture without fanout bottleneck, the proposed architectures can achieve a speedup of over 100%.

Forward error correction coding

Abstract: A Forward Error Correction coding method comprises a generalised concatenated code comprising a plurality of outer component codes (Ai) and a plurality of inner component codes (B’i ). The outer components codes comprise Reed-Solomon (RS) codes and a plurality of binary codes of equal length but varying rates. The inner component codes have a nested structure and are defined by the sum of disjoint BoseChaudhuri-Hocquenghem (BCH) codes. The component codes Ai and B’i are selected such that the product of the minimum Hamming distances of the inner and outer component codes, Did’i , are as equal as possible. Moreover the component codes are selected by matching cyclotomic cosets of inner BCH codes and type and multiplicity of outer codes.

Eliminating the fanout bottleneck in parallel long BCH encoders

Abstract: Long BCH codes can achieve about 0.6-dB additional coding gain over Reed-Solomon codes with similar code rate in long-haul optical communication systems. BCH encoders are conventionally implemented by a linear feedback shift register architecture. Encoders of long BCH codes may suffer from the effect of large fanout, which may reduce the achievable clock speed. The data rate requirement of optical applications require parallel implementations of the BCH encoders. In this paper, a novel scheme based on look-ahead computation and retiming is proposed to eliminate the effect of large fanout in parallel long BCH encoders. For a (2047, 1926) code, compared to the original parallel BCH encoder architecture, the modified architecture can achieve a speedup of 132%.

Method and apparatus for providing reduced memory low density parity check (LDPC) codes

Abstract: An approach is provided for generating Low Density Parity Check (LDPC) codes An LDPC encoder (203) generates a LDPC code with an outer Bose Chaudhuri Hocquenghem (BCH) code For a rate 315 code, the approach provides a degree profile that yields reduced memory requirements for storage of the edge values without significantly affecting the performance with respect to an "unmodified" rate 3/5 code The relevant parameters for the reduced memory LDPC codes are as follows: q= 72, n/dpc = 64800, k idpc = n BCH = 38880, k BCH = 38688 The above approach has particular application in digital video broadcast services over satellite

Area efficient parallel decoder architecture for long BCH codes

Abstract: Long BCH codes achieve additional coding gain of around 0.6 dB compared to Reed-Solomon codes with similar code rate used for long-haul optical communication systems. For our considered parallel decoder architecture, a novel group matching scheme is proposed to reduce the overall hardware complexity of both Chien search and syndrome generator units by 46% for BCH(2047, 1926, 23) code as opposed to only 22% if directly applying the iterative matching algorithm. The proposed scheme exploits the substructure sharing within a finite field multiplier (FFM) and among groups of FFMs.

Eliminating the fanout bottleneck in parallel long BCH encoders

Abstract: Long BCH codes can achieve about 0.6 dB additional coding gain over Reed-Solomon codes with a similar code rate in long-haul optical communication systems. BCH encoders are conventionally implemented by a linear feedback shift register architecture. Encoders of long BCH codes may suffer from the effect of large fanout, which may reduce the achievable clock speed. The data rate requirement of optical applications require parallel implementations of the BCH encoders. In this paper, a novel scheme based on look-ahead computation and retiming is proposed to eliminate the effect of large fanout in parallel long BCH encoders. For a (2047, 1926) code, compared to the original parallel BCH encoder architecture, the modified architecture can achieve a speedup of 132%.

Improving the payload of watermarking channels via LDPC coding

Abstract: The payload increase of watermarking channels via the use of low-density parity check (LDPC) codes is considered. The bit error rate and payload size problem is addressed in the light of the performance of typical transform-domain spread-spectrum watermarking techniques. Simulation results indicate that the information payload can be doubled via judicious use of LDPC codes vis-a/spl grave/-vis the performance of the Bose-Chaudhuri-Hochquenghem and repetition codes.

Low-complexity GEL codes for digital magnetic storage systems

Abstract: A class of concatenated block codes, called generalized error-locating (GEL) codes, is proposed for error correction in digital magnetic storage systems. GEL codes are suited for high code rate applications with low-complexity (hard input) decoding algorithms. They offer high flexibility and can be adjusted to a variety of different situations. In this paper, we use as an example a (precoded) PR4 channel and consider GEL codes with BCH and Reed-Solomon component codes. Simulation results give bit error rates with and without constrained codes.

Long nonbinary codes exceeding the Gilbert-Varshamov bound for any fixed distance

Abstract: Let A(q,n,d) denote the maximum size of a q-ary code of length n and distance d. We study the minimum asymptotic redundancy as n grows while q and d are fixed. For any d and q/spl ges/d-1, long algebraic codes are designed that improve on the Bose-Chaudhuri-Hocquenghem (BCH) codes and have the lowest asymptotic redundancy known to date. Prior to this work, codes of fixed distance that asymptotically surpass BCH codes and the Gilbert-Varshamov bound were designed only for distances 4,5, and 6.

Method and system for providing short block length low density parity check (LDPC) codes in support of broadband satellite applications

Abstract: An approach is provided for encoding short frame length Low Density Parity Check (LDPC) codes. An encoder generates a LDPC code having an outer Bose Chaudhuri Hocquenghem (BCH) code. Structure is imposed on the LDPC codes by restricting portion part of the parity check matrix to be lower triangular and/or satisfying other requirements such that the communication between bit nodes and check nodes of the decoder is simplified. Further, a cyclic redundancy check (CRC) encoder is supplied to encode the input signal according to a CRC code. This approach has particular application in digital video broadcast services over satellite.

Subspace algorithms for error localization with quantized DFT codes

Abstract: Recently, a class of real-number Bose-Chaudhuri-Hocquengem codes known as discrete Fourier transform (DFT) codes have been considered as joint source and channel codes for providing robustness to erasures and errors over wireless networks. We propose three subspace algorithms for error localization with quantized DFT codes. The algorithms are similar to the MUSIC, the minimum-norm, and the ESPRIT algorithms used in array signal processing for direction-of-arrival estimation. They provide different but related formulations of the error localizations by first partitioning a vector space into the channel error subspace and its orthogonal complement, the noise subspace. The locations of the errors are determined from either the error subspace eigenvectors or the noise subspace eigenvectors. We also present a brief performance analysis of the localization error in terms of the perturbation of the error subspace due to quantization. Simulation results show that their localization performances are similar, and they perform better than the coding-theoretic approach over a broad range of channel-error-to-quantization-noise ratios.

Low power decoding of BCH codes

Abstract: Low power decoding of error control codes is desirable not only for hand-held devices but also for central office equipments. Based on the studies of real-life ASICs, this paper first analyzes power consumption in each step of the popular syndrome-based decoding of BCH codes. It identifies Chien search, the most commonly used procedure in decoding, as the most power consuming operation. This paper further develops a low power decoding technique that tackles the power issues of the Chien search. The proposed technique is effective in power reduction and simple to implement.

Optimal Watermark Detection Based on Support Vector Machines

Abstract: In this paper, a novel optimal watermark detection scheme based on support vector machine and error correcting codes is proposed. To extract the watermark bits from a possibly corrupted marked image with a lower error probability, we apply both the good generalization ability of support vector machine and the error correction code BCH. Due to the good learning ability of support vector machine, it can learn the relationship between the embedded information and corresponding watermarked image; when the watermarked image is attacked by some intentional or unintentional attacks, the trained support vector machine can recover the right hidden information bits.

Efficient and robust distributed speech recognition (DSR) over wireless fading channels: 2D-DCT compression, iterative bit allocation, short BCH code and interleaving

Abstract: In this paper, a new framework for distributed speech recognition (DSR) over wireless fading channels is proposed. A 2D-DCT based compression method and an iterative bit allocation algorithm are developed for source coding, while short BCH code integrated with interleaving is proposed for channel coding. The high correlation among speech feature parameters in the temporal domain is well exploited in the 2D-DCT based compression, and a carefully designed iterative bit allocation algorithm can very efficiently make use of every bit transmitted. The very low bit rate provides planning space for strong error control. Short BCH code integrated with interleaving is initially proposed to efficiently handle the severe bursty errors usually encountered in wireless fading channels. Overall system simulation based on a GPRS wireless channel simulator indicated significant recognition performance improvement is achievable at a bit rate of 3.4 kbit/s as compared to the conventional SVQ compression approach (with bit rate 4.4 or 4.8 kbit/s). The low computation requirements for all processes involved make it easy to implement them in the mobile telephone clients with existing technology.

Error-correcting codes and B/sub h/-sequences

Abstract: We construct error-correcting (nonlinear) binary codes using a construction of Bose and Chowla in additive number theory. Our method extends a construction of Graham and Sloane for constant weight codes. The new codes improve 1028 of the 7168 best known h-error-correcting codes of word length /spl les/512 with 1/spl les/h/spl les/14. We give asymptotical comparisons to shortened Bose-Chaudhuri-Hocquenghem (BCH) codes.

Reliable and robust transmission and storage of medical images with patient information

Abstract: A new method for compact storage and transmission of medical images with concealed patient information in noisy environment is evinced. Digital watermarking is the technique adapted here for interleaving patient information with medical images. The patient information, which comprises of text data and signal graph, is encrypted to prevent unauthorized access of data. The latest encryption algorithm (Rijndael) is used for encrypting the text information. Signal graphs (ECG, EEG EMG etc.) are compressed using DPCM technique. To enhance the robustness of the embedded information, the patient information is coded by error correcting codes (ECC) such as (7,4) Hamming, Bose-Chaudhuri-Hocquenghem (BCH) and Reed Solomon (RS) codes .The noisy scenario is simulated by adding salt and pepper (S&P) noise to the embedded image. For different signal to noise ratio (SNR) of the image, bit error rate (BER) and number of character altered (NOCA) for text data and percentage distortion (PDIST) for the signal graph are evaluated. The performance comparison based on the above parameters is conducted for three types of ECC. It is elicited that coded systems can perform better than the uncoded systems.

Multi-level memory systems using error control codes

Abstract: In this paper, the multi-level memory system using error control codes has been proposed. As compared with other approaches for 2/sup m/-level memory cells, our proposal features an effective grouping of several q-level memory cells with q>2/sup m/ in order to create parity bits of error control codes. Therefore, the proposed methodology can enhance both the yield and reliability without area penalty for multilevel memory systems. The BCH (72,64) code of correcting single error is presented for 5-level memory cells. In contrast to 2/sup 2/-level memory cells, our proposal can improve yields from 61.58% to 99.92% for 16 Mbit and make the mass production of 1 Gbit memory practicable under the approximated model for StrataFlash/sup TM/. Since our work was motivated from the use of q-level cells in substitution for 2/sup m/-level cells, not only multi-level flash memory, but also multi-level DRAM systems, can both benefit from our proposed methodology.

Method and system for correcting errors in electronic memory devices

Abstract: The invention relates to a method and system for correcting errors in multilevel memories using binary BCH codes. The number of errors is estimated by analyzing the syndrome components (5). If the number of estimated errors is one, then simple decoding for a Hamming code is performed. Otherwise, conventional decoding of the BCH code is carried out (2,3). This avoids the computation of the error locator polynomial and its roots in the presence of only one error and, thus, reduces the average decoding complexity.

Reliable transmission with low complexity Reed-Solomon block turbo codes

Abstract: We show here that low complexity Reed-Solomon (RS) block turbo codes (BTC) based on Q-ary symbol and bit concatenation can both achieve reliable transmission at less than 1 dB from Shannon limit using quadrature phase shift keying (QPSK) over additive white Gaussian noise (AWGN) channel. These near Shannon performances are due to a proper choice of RS component codes in the construction of RS product codes. RS-BTC based on Q-ary symbol concatenation has a great advantage in terms of block size over those based on bit concatenation. Compared to Bose-Chaudhuri-Hocquenghem (BCH) BTC of similar code rate, its smaller memory size is worth noting from the practical point of view.

A peak power reduction scheme based on reversal of parity-bits for a block-coded OFDM signal

Abstract: We propose a peak power reduction (PPR) scheme based on the reversal of parity-bits for a block-coded OFDM signal. In our PPR scheme, the entire parity-check block of the codeword is adaptively reversed, symbol-by-symbol, so as to minimize the PAPR of the OFDM-signal. At the receiver, the original codeword can be restored with sufficient accuracy by checking the syndrome of the received codeword and protecting a significant-bit of the codeword from transmission error. When (7,4), (31,21) and (31,26) BCH codes are employed, the PAPR of the OFDM signal, at the CCDF (complementary cumulative distribution function) of 10/sup -4/, can be reduced by about 2.8, 2.5 and 2.0 dB, respectively, by applying the PPR scheme while achieving approximately the same BER performance as the case without PPR in an exponentially decaying 6-path Rayleigh fading condition.

Space – time block factorisation codes over Gaussian integers

Abstract: A solution for the design of space-time codes over a complex signal constellation is given. The Gaussian integer field is described and shown to produce a similar complex signal constellation as QAM for particular parameters. The mapping between the Galois field and the Gaussian integer field is shown to preserve the rank statistics of codeword matrices and thereby the diversity gain of the code. Factorisation space-time codes, which have similarities to BCH codes, are constructed over a Galois field and then mapped to a Gaussian integer constellation. This construction is one example of how classical coding theory can be directly applied to space-time code design. Statistical analysis of the Euclidean, geometric and rank metrics is performed. The codeword error performance for different dimensions is shown to give full rank and to perform marginally better than a similar delay diversity code for the parameters considered.

A BCH code-based Robust Audio Watermarking in Cepstrum Domain

Abstract: In this article, a BCH code-based audio watermarking approach performed in the cepstrum domain is proposed. The technique takes advantage of the attack-invariant feature of the cepstrum domain and the error-correction capability of BCH code to increase the robustness of audio watermarking. In addition, the watermarked audio has very high perceptual quality. A blind watermark detection technique is developed to identify the embedded watermark under various types of attacks. Experiment results demonstrate that the proposed technique outperforms the existing audio watermarking techniques against most of the asynchronous attacks.

Concatenated iterative forward error correction coding

Abstract: Techniques that may be used in communication systems include encoding (18, 20, 22) a stream of data using concatenated BCH codes, communicating the encoded data over a transmission medium (14), and decoding (24, 26, 28, 30) the encoded data using the BCH codes. The overhead of the concatenated BCH codes may substantially match the overhead of the Reed-Solomon RS(255/239) code. Examples of pairs of concatenated BCH codes include [BCH(2040,1952), BCH(3904, 3832)] and [BCH(2040, 1941), BCH(3882, 3834)].

Method and system for providing parity check (ldpc) code having low density of short block length

Abstract: PROBLEM TO BE SOLVED: To provide an approach generating a parity check (LDPC) code having a low density. SOLUTION: A short LDPC code is generated by shortening a longer mother code by an LDPC encoder (203). The short LDPC code has an outer Bose Chaudhuri Hocqenghem (BCH) code. The bit of an output LDPC code is interleaved, by writing data related in the LDPC-code row direction serially to a table by an interleaver and reading the data in serial in the line direction from the right to the left to the LDPC code, having a code rate of 3/5 using a 8-PSK from another viewpoint. The approach has a specific applications in digital video broadcast service through a satellite. COPYRIGHT: (C)2005,JPO&NCIPI

The mathematics of coding theory : information, compression, error correction, and finite fields

Abstract: 1. Probability. Counting. Preliminary Ideas of Probability. More Formal View of Probability. Random Variables, Expected Values, Variance. Markov Inequality, Chebycheff Inequality. Law of Large Numbers. 2. Information and Entropy. Uncertainty, Acquisition of Information. Entropy. Uniquely-Decipherable and Prefix Codes. Kraft and Macmillan Inequalities. 3. Noiseless Coding. Noiseless Coding Theorem. Huffman Coding. 4. Noisy Coding. Noisy channels. Example: Parity Checks. Decoding from a Noisy Channel. Channel Capacity. Noisy Coding Theorem. 5. Cyclic Redundancy Checks. The Finite Field GF(2) with 2 Elements. Polynomials over GF(2). Cyclic Redundancy Checks (CRC's). What Errors Does a CRC Catch? 6. The Integers. Reduction Algorithm. Divisibility. Factorization into Primes. Euclidean Algorithm. Integers Modulo M. The Finite Field Z/P for P Prime. Fermat's Little Theorem. Primitive Roots. Euler's Criterion. Fast Modular Exponentiation. 7. Finite Fields. Making Fields. Examples of Field Extensions. Addition Modulo P. Multiplication Modulo P. Multiplicative Inverses Modulo P. Primitive Roots. 8. Polynomials. Polynomials with Coefficients in a Field. Divisibility. Factoring and Irreducibility. Euclidean Algorithm. Unique Factorization. 9. Introduction to Linear Codes. An Ugly Example. The Hamming Binary [7,4] Code. Some Linear Algebra. A Review of Row Reduction. Definition: Linear Codes. Syndrome Decoding. Berlekamp's Algorithm. 10. Bounds for Codes. Hamming (Sphere-Packing) Bound. Gilbert-Varshamov Bound. Singleton Bound. 11. Cyclic Codes. Minimum Distance in Linear Codes. Cyclic Codes. 12. Primitive Roots. Characteristics of Fields. Multiple Factors in Polynomials. Cyclotomic Polynomials. Primitive Roots in Finite Fields. Primitive Roots Modulo Prime Powers. Counting Primitive Roots. Non-Existence. An Algorithm to Find Primitive Roots. 13. Primitive Polynomials. Definitions. Examples Modulo 2. Testing for Primitivity. Example: Periods of LFSR's. Example: Two-Bit Errors Detected by CRC's. 14. Basic Linear Codes. Vandermonde Determinants. More Check Matrices for Cyclic Codes. RS Codes. Hamming Codes (Again). BCH Codes. Decoding BCH Codes. 15. Concatenated Codes. Mirage Codes. Concatenated Codes. Justesen Codes. Some Explicit Irreducible Polynomials. 16. Curves and Codes. Plane Curves. Singularities of Curves. Projective Plane Curves. Curves in Higher Dimensions. Genus, Divisors, Linear Systems. Geometric Goppa Codes. Tsfasman-Vladut-Zink Bound. Appendices. Sets and functions. Equivalence Relations. Stirling's Formula. Bibliography. Index.