Showing papers on "Benchmark (computing) published in 1989"
08 May 1989
TL;DR: A set of 31 digital sequential circuits described at the gate level that extend the size and complexity of the ISCAS'85 set of combinational circuits and can serve as benchmarks for researchers interested in sequential test generation, scan-basedtest generation, and mixed sequential/scan-based test generation using partial scan techniques.
Abstract: A set of 31 digital sequential circuits described at the gate level is presented. These circuits extend the size and complexity of the ISCAS'85 set of combinational circuits and can serve as benchmarks for researchers interested in sequential test generation, scan-based test generation, and mixed sequential/scan-based test generation using partial scan techniques. Although all the benchmark circuits are sequential, synchronous, and use only D-type flip-flops, additional interior faults and asynchronous behavior can be introduced by substituting for some or all of the flip-flops their appropriate functional models. The standard functional model of the D flip-flop provides a reference point that is independent of the faults particular to the flip-flop implementation. A testability profile of the benchmarks in the full-scan-mode configuration is discussed. >
1,972 citations
01 Jun 1989
TL;DR: A dynamic programming procedure is introduced for the tightest of these conditions, the viability condition, and the integration of all four sensitization conditions in the LLLAMA timing environment is discussed.
Abstract: We consider the elimination of false paths in combinational circuits. We give the single generic algorithm that is used to solve this problem, and demonstrate that it is parameterized by a boolean function called the sensitization condition. We give two criteria which we argue that a valid sensitization condition must meet, and introduce four conditions that have appeared in the recent literature, of which two meet the criteria and two do not. We then introduce a dynamic programming procedure for the tightest of these conditions, the viability condition, and discuss the integration of all four sensitization conditions in the LLLAMA timing environment. We give results on the IWLS and ISCAS benchmark examples and on carry-bypass adders.
180 citations
29 Aug 1989
TL;DR: The authors describe a built-in self-test (BIST) technique where the on-chip test pattern generator is a binary counter with associated XOR gates that forms the basis for the synthesis of the binary counter and accompanying (combinational) logic using linear algebraic techniques.
Abstract: The authors describe a built-in self-test (BIST) technique where the on-chip test pattern generator is a binary counter with associated XOR gates. A precomputed set of tests (obtained through some test generation scheme) is required for this approach. A subset of this set of tests forms the basis for the synthesis of the binary counter and accompanying (combinational) logic using linear algebraic techniques. Simulation of this BIST technique on various benchmark circuits has given good results in terms of both coverage and hardware size. >
92 citations
08 May 1989
TL;DR: The authors report on the results of running a version of the Sequential Circuit Test Generator (STG3) on the ISCAS-89 sequential circuit benchmarks, which determines that faults are undetectable fairly quickly, taking only 0.98 s on a totally untestable circuit.
Abstract: The authors report on the results of running a version of the Sequential Circuit Test Generator (STG3) on the ISCAS-89 sequential circuit benchmarks. First, they present a brief history of STG and briefly describe the algorithms used. They then describe the conditions under which the experiments were run and give the benchmark results. No particular problems were encountered when running STG3 on the benchmark circuits, except for those circuits with many untestable faults. STG3 determines that faults are undetectable fairly quickly, taking only 0.98 s on a totally untestable circuit. The major problem with the circuits considered untestable was in initializing the circuit state. >
79 citations
01 May 1989
57 citations
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TL;DR: The author describes benchmarking and discusses some of the specific benchmark tests for computer systems that are in use today and points out how to avoid, or at least minimize the impact of, such problems.
Abstract: The author describes benchmarking and discusses some of the specific benchmark tests for computer systems that are in use today. He examines some of the pitfalls involved with benchmark comparison and analysis and points out how to avoid, or at least minimize the impact of, such problems. The goal is to learn how to gather and interpret meaningful comparison data. Benchmark test results are tabulated for the Dhrystone 1.1, Digital Review, Dodec, Khornerstone, Linpack, Livermore Fortran Kernel, SPICE, Stanford, and single-precision Whetstone benchmarks. >
57 citations
23 May 1989
TL;DR: A nominally 1000-word resource management database for continuous speech recognition was developed for use in the DARPA Speech Research Program and is expected to be made available to a wider community in the near future.
Abstract: A nominally 1000-word resource management database for continuous speech recognition was developed for use in the DARPA Speech Research Program. This database has now been used at several sites for benchmark tests, and the database is expected to be made available to a wider community in the near future. The author documents the structure of the benchmark tests, including the selection of test material and details of studies of scoring algorithms. >
34 citations
06 Feb 1989
TL;DR: The second version of F DS-R (functional disk system with relational database engine), FDS-RII, which is designed to handle large relations efficiently, is discussed and the performance of FDS -RII attained a high performance level for large relations as compared to other large database systems such as Gamma and Teradata.
Abstract: The second version of FDS-R (functional disk system with relational database engine), FDS-RII, which is designed to handle large relations efficiently, is discussed. On FDS-RII, the processing algorithm is selected at run time from two algorithms (nested loop algorithms, grace hash algorithm) by comparing their estimated I/O costs. The processing strategy is discussed in detail. The I/O cost formula is examined by measuring the execution time of a join query on the FDS-RII. With the expanded version of Wisconsin Benchmark, the performance of FDS-RII is measured. FDS-RII attained a high performance level for large relations as compared to other large database systems such as Gamma and Teradata. While FDS uses just one disk and three MC68020s, Teradata uses 40 disks and 20 AMPs and Gamma requires eight disks and 17 VAX 11/750s. >
33 citations
01 Jun 1989
TL;DR: A parallel test generation algorithm is proposed which tries to achieve a high fault coverage for HTD faults in a reasonable amount of time and exhibits superlinear speedups in some cases due to search anomalies.
Abstract: For circuits of VLSI complexity, test generation time can be prohibitive. Most of the time is consumed by hard-to-detect (HTD) faults which might remain undetected even after a large number of backtracks. We identify the problems inherent in a uniprocessor implementation of a test generation algorithm and propose a parallel test generation algorithm which tries to achieve a high fault coverage for HTD faults in a reasonable amount of time. A dynamic search space allocation strategy is used which ensures that the search spaces allocated to different processors are disjoint. The parallel test generation algorithm has been implemented on an Intel iPSC/2 hypercube. Results are presented using the ISCAS combinational benchmark circuits which conclusively prove that parallel processing of HTD faults does indeed result in high fault coverage which is otherwise not achievable by a uniprocessor algorithm in limited CPU time. The parallel algorithm exhibits superlinear speedups in some cases due to search anomalies.
29 citations
01 Jun 1989
TL;DR: Benchmark first principles calculations of the pure rotational and ro-vibrational transition frequencies and line strengths are presented, using two independent program suites and it is suggested they could provide a standard with which other groups working in this field can compare their calculations.
Abstract: Abstract Benchmark first principles calculations of the pure rotational and ro-vibrational transition frequencies and line strengths are presented, using two independent program suites. Both sets of calculations were performed using the same potential energy and dipole surfaces. Our example calculations use recently calculated surfaces for H 2 S which have been shown to give good agreement with experimental data. The results, which show perfect agreement for the energy levels, transition frequencies and line strengths, are used as an external check on the two program suites. It is suggested they could provide a standard with which other groups working in this field can compare their calculations.
26 citations
Proceedings Article•
01 Jan 1989
TL;DR: A modified WAM is described which optimises shallow backtracking in Prolog programs, showing that the speedup gained by this optimisation can be significant.
Abstract: The cost of backtracking has been identified as one of the bottlenecks in achieving peak performance in compiled Prolog programs. Much of the backtracking in Prolog programs is shallow, i.e. is caused by unification failures in the head of a clause when there are more alternatives for the same procedure, and so special treatment of this form of backtracking has been proposed as a significant optimisation. This paper describes a modified WAM which optimises shallow backtracking. Four different implementation approaches are compared. A number of benchmark results are presented, measuring the relative tradeoffs between compilation time, code size, and run time. The results show that the speedup gained by this optimisation can be significant.
Book•
13 Dec 1989
TL;DR: This work compiles and simulates the sequential execution of sequential Prolog on an abstract parallel Prolog machine and presents the occur-check problem and benchmark programs.
Abstract: Compilation of sequential Prolog.- Pipelined execution of sequential Prolog.- The occur-check problem.- The abstract parallel Prolog machine.- Simulation.- Conclusion.- Benchmark programs.- Compilation examples.
TL;DR: Prime proposes that IOBENCH and a standard spectrum of runs be adopted as an industry standard for measuring IO performance, which has proven to be a very good indicator of system IO performance.
Abstract: IOBENCH is an operating system and processor independent synthetic input/output (IO) benchmark designed to put a configurable IO and processor (CP) load on the system under test. It is meant to stress the system under test in a manner consistent with the way in which Oracle, Ingres, Prime INFORMATION or other data management products do IO. The IO and CP load is generated by background processes doing as many "transactions" as they can on a specified set of files during a specified time interval. By appropriately choosing and varying the benchmark parameters, IOBENCH can be configured to approximate the IO access patterns of real applications. IOBENCH can be used to compare different hardware platforms, different implementations of the operating system, different disk buffering mechanisms, and so forth. IOBENCH has proven to be a very good indicator of system IO performance. Use of IOBENCH has enabled us to pinpoint operating system bugs and bottlenecks.IOBENCH currently runs on PRIMOS and a number of UNIX systems; this paper discusses the UNIX versions. IOBENCH can be ported to a new platform in a few days. Prime proposes that IOBENCH and a standard spectrum of runs be adopted as an industry standard for measuring IO performance. Sources and documentation for IOBENCH will be made available free of charge.
TL;DR: Because it does a better job balancing work between processors, hyperquicksort proves to be uniformly superior to quickmerge.
Abstract: We analyze the computational and communication complexity of four sorting algorithms as implemented on a hypercube multicomputer: two variants of hyperquicksort and two variants of quickmerge. Based upon this analysis, machine-specific parameters can be used to determine when each algorithm requires less communication time than the others. We present benchmark results of the four algorithms on a 64-processor NCube/7. The benchmarking provides experimental evidence that hyperquicksort divides the values to be sorted more evenly among the processors than quickmerge. Because it does a better job balancing work between processors, hyperquicksort proves to be uniformly superior to quickmerge.
01 Jan 1989
TL;DR: The performance of the logic-probabilistic system is shown to be two orders of magnitude better than know back-error propagation techniques which have used this task as a benchmark.
Abstract: A universal node model is assumed in this general analysis of connectionist nets. It is based on a logic truth-table with a probabilistic element. It is argued that this covers other definitions. Algorithms are developed for training and testing techniques that involve reducing amounts of noise, giving a new perspective on annealing. The principle is further applied to ‘hard’ learning and shown to be achievable on the notorious parity-checking problem. The performance of the logic-probabilistic system is shown to be two orders of magnitude better than know back-error propagation techniques which have used this task as a benchmark.
22 May 1989
TL;DR: The authors outline a framework within which evaluation and comparison of sensor management systems should be performed and determination of the relative importance of each of these MOPs with respect to the mission goals.
Abstract: The authors outline a framework within which evaluation and comparison of sensor management systems should be performed. The four aspects of this framework are: (1) selection of numerical measures of performance (MOPs) which are relevant to the mission goals; (2) determination of the relative importance (weights) of each of these MOPs with respect to the mission goals; (3) definition of benchmark scenarios for evaluating the performance of the sensor management system with respect to these MOPs and mission goals; and (4) comparison of the performance of the sensor management system to the performances of several basic sensor management systems with respect to the benchmark scenarios. >
TL;DR: A simple diagnostic is proposed, CD, which measures the number of constant digits in a data set and which would detect highly ill-conditioned data sets before they are analyzed, and indicates that all three packages ignore ill- Conditioning that occurs when the data grows more nearly constant.
01 Nov 1989
TL;DR: This paper presents the results of an initial performance evaluation of the Gamma database machine based on an expanded version of the single-user Wisconsin benchmark, and analyzes and interpret the results based on understanding of the system hardware and software.
Abstract: This paper presents the results of an initial performance evaluation of the Gamma database machine based on an expanded version of the single-user Wisconsin benchmark. In our experiments we measured the effect of relation size and indices on response time for selection, join, and aggregation queries, and single-tuple updates. A Teradata DBC/1012 database machine of similar size is used as a basis for interpreting the results obtained. We analyze and interpret the results of these experiments based on our understanding of the system hardware and software, and conclude with an assessment of the strengths and weaknesses of the two machines.
27 Feb 1989
TL;DR: The authors describe and motivate the design of a scalable and portable benchmark for database systems, the AS/sup 3/AP benchmark (Ansi SQL Standard Scalable and Portable).
Abstract: The authors describe and motivate the design of a scalable and portable benchmark for database systems, the AS/sup 3/AP benchmark (Ansi SQL Standard Scalable and Portable). The benchmark is designed to provide meaningful measures of database processing power, to be portable between different architectures, and to be scalable to facilitate comparisons between systems with different capabilities. The authors introduce a performance metric, namely, the equivalent database ratio, to be used in comparing systems. >
01 Jan 1989
TL;DR: The need for benchmark problems for the evaluation of software for computer-aided control system analysis and design is discussed in this article, as well as the plans for future benchmark problems.
Abstract: The need for having benchmark problems for the evaluation of software for computer-aided control system analysis and design is discussed. The two benchmark problems that have been released to date by the Benchmark Working Group of the Technical Committee on Computer-aided Control System Design of the IEEE Control Systems Society are described, as are the plans for future problems. Information that has been learned about the preparation, distribution, and dissemination of results for this type of problem is included.
01 Aug 1989
TL;DR: It is suggested that limiting the flexibility of the retargetable VLIW architecture does not necessary reduce the application space, and the SCARCE framework, an approach for cost-effective design of application-specific processors which must exploit application-resident parallelism, is used.
Abstract: Increasing the performance of application-specific processors by exploiting application-resident parallelism is often prohibited by costs; especially in the case of low-volume productions. The flexibility of horizontal-microcoded machines allows these costs to be reduced, but the flexibility often reduces efficiency. VLIW is a new and promising concept for the design of low-cost, high-performance parallel computer systems. We suggest that the VLIW concept can also be used as a basis for cost-effective design of application-specific processors which must exploit application-resident parallelism.The SCARCE (SCalable ARChitecture Experiment) framework, an approach for cost-effective design of application-specific processors, provides features which allow the design of retargetable VLIW architectures. However, a retargetable VLIW architecture is only effective if there is a retargetable VLIW compiler. Since a VLIW compiler is an essential part of the VLIW architecture, tradeoffs must be made between the variety of VLIW architectures and the compiler complexity. We suggest that limiting the flexibility of the retargetable VLIW architecture does not necessary reduce the application space.This paper discusses the issues related to the design of a retargetable VLIW processor architecture and compiler within the SCARCE framework.
01 Dec 1989
23 May 1989
TL;DR: It is concluded that DSPs are better suited to embedded systems, but the transputer may offer the advantage in a research environment of general usefulness for supercomputing power.
Abstract: DPSs (digital signal processors), conventional microprocessors, and transputers are compared on the basis of their ability to perform image processing tasks, with a view to assessing their potential for implementation in real time systems. The study covers a selection of the more important instructions in use in image processing algorithms as well as a selection of the algorithms themselves as a simple benchmark, and includes a survey of multiprocessor systems implemented with some of these processors. It is concluded that DSPs are better suited to embedded systems, but the transputer may offer the advantage in a research environment of general usefulness for supercomputing power. Transputer systems are also more flexible in the sense of re-programmability, and a single system could be used for all processing levels, numeric and symbolic, in a computer vision system. >
Book•
01 Jan 1989
TL;DR: Step-by-step guidance through the stages of problem definition, modeling, and solution of dynamic and thermal analysis, substructuring, and linear statics, and how to calibrate the accuracy of finite.
Abstract: Step-by-step guidance through the stages of problem definition, modeling, and solution. Presents six example problems, as well as nine industry-standard benchmark problems. Covers dynamic and thermal analysis, substructuring, and linear statics, and discusses how to calibrate the accuracy of finite
01 Jan 1989
TL;DR: A metric based on pershapes is introduced that provides a quantitative way of measuring how similar two machines are in terms of their performance distributions and is related to the extent to which pairs of machines have varying relative performance levels depending on which benchmark is used.
Abstract: Runs of a benchmark or a suite of benchmarks are inadequate to either characterize a given machine or to predict the running time of some benchmark not included in the suite Further, the observed results are quite sensitive to the nature of the benchmarks and the relative performance of two machines can vary greatly depending on the benchmarks used In this paper, we report on a new approach to benchmarking and machine characterization The idea is to create and use a machine characterizer, which measures the performance of a given system and spotlight its strong and weak points; each parameter provides the execution time for some primitive operation in Fortran We present measurements for a large number of machines ranging from small workstations to supercomputers We then combine these measurements into groups of parameters which relate to specific aspects of the machine implementation, and use these groups to provide overall machine characterizations We also define the concept of pershapes, which represent the level of performance of a machine for different types of computation We introduce a metric based on pershapes that provide a quantitative way of measuring how similar two machines are in terms of their performance distributions This metric is related to the extent to which pairs of machines have varying relative performance levels depending on which benchmark is used
Journal Article•
03 Jan 1989
TL;DR: The resource measurement system (REMS) is a nonintrusive, hardware measurement tool used to obtain both trace measurement and resource utilization information that provides more detailed and extensive measurement information than alternative software or hybrid approaches without introducing artifacts into the test results.
Abstract: A hardware approach is presented for the design of performance measurement instrumentation for a shared-memory, tightly coupled MIMD multiprocessor. The resource measurement system (REMS) is a nonintrusive, hardware measurement tool used to obtain both trace measurement and resource utilization information. This approach provides more detailed and extensive measurement information than alternative software or hybrid approaches without introducing artifacts into the test results. This is accomplished at a significantly higher tool cost than the alternative software or hybrid approaches. Certain features of today's microprocessors limit the applicability of such a hardware tool. Measurements obtained using this hardware tool on two kernel (small benchmark) routines are presented. >
Patent•
15 Jun 1989
TL;DR: In this article, the authors propose to automatically execute a performance measurement by the benchmark job of a virtual machine to a full virtual machine and an object without worrying about measuring environment and to reduce man hour by using a communicating function between the virtual machine.
Abstract: PURPOSE:To automatically executing a performance measurement by the benchmark job of a virtual machine to a full virtual machine and an object without worrying about measuring environment and to reduce man hour by using a communicating function between the virtual machine. CONSTITUTION:By a performance measurement starting command from a console device 6, a communication processing part 5 of a virtual machine 4 opens a message log file 7 and indicates the starting of a processing to a virtual machine 15 of a user. The machine 15 outputs a text 18 to indicate the name of an operating system 17. A processing part 5 obtains an applicable benchmark job 14 from a corresponding table 11, and convert-inputs it through a spool file 12 to a benchmark job 14 of the machine 15. The machine 15 executes the job 14, outputs the data to the text 18, send them to a machine 4, stores them in the file 7 and outputs them as editing data 10 when the processing of the system 17 is completed, and the data are analyzed and evaluated.
TL;DR: A lid-driven cavity flow which is one of the most famous benchmark problems is examined and the 'CONDIF' approach is found that the CONDIF approach is very stable for the grid Peclet number condition and the time step is not sensitive to the Courant condition.
Abstract: Many benchmark problems for the numerical analysis of the fluid flow have been proposed. In this paper, a lid-driven cavity flow which is one of the most famous benchmark problems is examined. Four numerical schemes are compared with each other in terms of the grid dependency and accuracy of the solutions. From the viewpoint of the interaction between neighboring computational cells, we choose a 'CONDIF : Controlled Numerical Diffusion with Internal Feedback' approach developed by Runchal and we check this scheme for this cavity flow problem. Consequently, it is found that the CONDIF' approach is very stable for the grid Peclet number condition and the time step is not sensitive to the Courant condition.
01 Jun 1989
TL;DR: It is shown, with the aid of the analytic models, that the proposed architecture is preferable performance-wise over the existing conventional supercomputer architectures.
Abstract: Supercomputers run multiprogrammed time-sharing operating systems, so their facilities can be shared by many local and remote users. Therefore, it is important to be able to assess the performance of supercomputers in multiprogrammed environments. Analytic models based on Queueing Networks QNs and Stochastic Petri Nets SPNs are used in this paper with two purposes: to evaluate the performance of supercomputers in multi programmed environments, and to compare, perfor mance-wise, conventional supercomputer architectures with a novel architecture proposed here. It is shown, with the aid of the analytic models, that the proposed architecture is preferable performance-wise over the existing conventional supercomputer architectures. A three-level workload characterization model for super computers is presented. Input data for the numerical ex amples discussed here are extracted from the well- known Los Alamos benchmark, and the results are vali dated by simulation.