Showing papers on "Benchmark (computing) published in 1992"

Hard and easy distributions of SAT problems

Abstract: We report results from large-scale experiments in satisfiability testing. As has been observed by others, testing the satisfiability of random formulas often appears surprisingly easy. Here we show that by using the right distribution of instances, and appropriate parameter values, it is possible to generate random formulas that are hard, that is, for which satisfiability testing is quite difficult. Our results provide a benchmark for the evaluation of satisfiability-testing procedures.

Benchmark Handbook: For Database and Transaction Processing Systems

Abstract: A practical guide that offers the reader a comprehensive view of benchmarking for modern transaction processing and database systems. Much of the information is available for the first time. The handbook provides the tools to evaluate different systems, different software products on a single machine, and different machines within a single product family.

Improving the accuracy of dynamic branch prediction using branch correlation

Abstract: Long branch delay is a well–known problem in today’s high performance superscalar and supetpipeline processor designs. A common technique used to alleviate this problem is to predict the direction of branches during the instruction fetch. Counter-based branch prediction, in particular, has been reported as an effective scheme for predicting the direction of branches. However, its accuracy is generally limited by branches whose future behavior is also dependent upon the history of other branches. To enhance branch prediction accuracy with a minimum increase in hardware COSLwe propose a correlation-based scheme and show how the prediction accuracy can be improved by incorporating information, not only from the history of a specific brsncb but also from the history of other branches. Specifically, we use the information provided by a proper subhistory of a branch to predict the outcome of that branch. The proper subhistory is selected based on the outcomes of the most recently executed M branches. The new scheme is evaluated using traces collected from running the SPEC benchmark suite on an IBM RISC System/6000 workstation. The results show that, ascompared with the 2-bit counter-based prediction scheme, the correlation-based branch prediction achieves up to 11 ~0 additional accuracy at the extra hardware cost of one shift register. The results also show that the accuracy of the new scheme surpasses that of the counter–based branch predction at saturation.

Benchmark problems for robust control design

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Transient Stability Test Systems for Direct Stability Methods

Abstract: The aim of this paper is to present a standard set of power system data with benchmark results against which direct stability techniques to assess transient stability could be compared and tested. The test systems have been selected to display a wide range of dynamic characteristics to provide a robust test of the efficacy and accuracy of the various analytical techniques to analyze transient stability. Transient stability test system data and benchmark results obtained from two commercially available time domain stability analysis packages are presented in this paper.

Object operations benchmark

Abstract: Performance is a major issue in the acceptance of object-oriented and relational database systems aimed at engineering applications such as computer-aided software engineering (CASE) and computer-aided design (CAD). Because traditional database systems benchmarks are inapproriate to measure performance for operations on engineering objects, we designed a new benchmark Object Operations version 1 (OO1) to focus on important characteristics of these applications. OO1 is descended from an earlier benchmark for simple database operations and is based on several years experience with that benchmark. In this paper we describe the OO1 benchmark and results we obtained running it on a variety of database systems. We provide a careful specification of the benchmark, show how it can be implemented on database systems, and present evidence that more than an order of magnitude difference in performance can result from a DBMS implementation quite different from current products; minimizing overhead per database call, offloading database server functionality to workstations, taking advantage of large main memories, and using link-based methods.

The nofib Benchmark Suite of Haskell Programs

Abstract: This position paper describes the need for, make-up of, and “rules of the game” for a benchmark suite of Haskell programs. (It does not include results from running the suite.) Those of us working on the Glasgow Haskell compiler hope this suite will encourage sound, quantitative assessment of lazy functional programming systems. This version of this paper reflects the state of play at the initial pre-release of the suite.

Iterative and adaptive slack allocation for performance-driven layout and FPGA routing

Abstract: The authors gives a generalization, called the limit-bumping algorithm (LBA), of a procedure of H. Youssef et al. (1990) that transforms initial connection delays into upper limits on delay suitable for performance-driven layout. LBA is a simple way to distribute slacks using arbitrary allocation functions. It is shown that lower and upper bounds on connection delays can be used in the computation of upper limits for initial layout and for layout improvement. The methods have been integrated into a delay-sensitive router for field programmable gate arrays (FPGAs). In 22 standard benchmark designs, feasible system clock periods were reduced in every case by an average of 14% and as much as 32%. >

Method and system for automated network benchmark performance analysis

Abstract: A method and system for automated network benchmark performance analysis which providing a highly realistic benchmark test representative of actual operation of specific software applications, without requiring installation and/or operation of the software applications during testing. Selected software applications generally utilized within a specific network are identified and representative transactions within those applications are executed while tracing the operation of the software application to identify and record input/output operations which occur during those transactions. The recorded list of input/output operations is then utilized to create a benchmark script for utilization in testing which has a high degree of verisimilitude when compared with actual software application operations. Benchmark testing is then performed utilizing the scripted input/output operations and highly accurate performance parameters such as throughput, transactions per second and absolute minimum, maximum and average response times may be determined. Additionally, performance parameter statistics for performance of a selected sequence of input/output operations characteristic of representative transactions may be determined and utilized as a more accurate benchmark for performance than individual response times.

Verifying clock schedules

Abstract: Timing verification and optimization have been formulated as mathematical programming problems. The computational aspects of using such a formulation for verifying clock schedules are considered. The formulation can have multiple solutions, and these extraneous solutions can cause previously published algorithms to produce incorrect or misleading results. The conditions under which multiple solutions exist are characterized, and it is shown that even when the solution is unique, the running times of these previous algorithms can be unbounded. By contrast, a simple polynomial time algorithm for clock schedule verification is exhibited. The algorithm was implemented and used to check the timing of all the circuits in the ISCAS-89 benchmark suite. Observed running times are linear in circuit size and quite practical. >

E-PROOFS: A CMOS bridging fault simulator

Abstract: The problem of bridging fault simulation under the conventional voltage testing environment is considered. A method to provide electrical-level simulation accuracy, without paying the associated performance penalties, is proposed. A three-level simulation model is used, balancing the tradeoffs among gate-level, switch-level, and electrical-level simulation. Large memory overheads are avoided by localizing the fault, and by performing electrical-level simulation only in the area around the fault. This approach is sufficiently flexible to model feedback faults, BiCMOS circuits, stuck-open faults, and any fault that can be described with a circuit netlist. Tests were run on several ISCAS combinational and sequential benchmark circuits, using realistic cells and transistor parameters; results show that accurate simulations can be performed in reasonable time. >

A genetic approach to the truck backer upper problem and the inter-twined spiral problem

Abstract: The author describes a biologically motivated paradigm, genetic programming, which can solve a variety of problems. When genetic programming solves a problem, it produces a computer program that takes the state variables of the system as input and produces the actions required to solve the problem as output. Genetic programming is explained and applied to two well-known benchmark problems from the field of neural networks. The truck backer upper problem is a multidimensional control problem and the inter-twined spirals problem is a challenging classification problem. >

Efficient implementation of heuristics for the continuous network design problem

Abstract: In this paper, we present an efficient implementation of heuristic procedures for solving the continuous network design problem where network users behave according to Wardrop's first principle of traffic equilibrium. Numerical results involving a “standard” benchmark problem are given. Also, it is shown that the cost mapping arising in the Iterative-Optimization-Assignment algorithm is integrable if and only if the volume-delay function is of either the BPR or some logarithmic form.

Analysis of the generalized clock buffer replacement scheme for database transaction processing

Abstract: The CLOCK algorithm is a popular buffer replacement algorithm because of its simplicity and its ability to approximate the performance of the Least Recently Used (LRU) replacement policy. The Generalized Clock (GCLOCK) buffer replacement policy uses a circular buffer and a weight associated with each page brought in buffer to decide on which page to replace. We develop an approximate analysis for the GCLOCK policy under the Independent Reference Model (IRM) that applies to many database transaction processing workloads. We validate the analysis for various workloads with data access skew. Comparison with simulations shows that in all cases examined the error is extremely small (less than 1%). To show the usefulness of the model we apply it to a Transaction Processing Council benchmark A (TPC-A) like workload. If knowledge of the different data partitions in this workload is assumed, the analysis shows that, with appropriate choice of weights, the performance of the GCLOCK algorithm can be better than the LRU policy. Performance very close to that for optimal (static) buffer allocation can be achieved by assigning sufficiently high weights, and can be implemented with a reasonably low overhead. Finally, we outline how the model can be extended to capture the effect of page invalidation in a multinode system.

Test compaction for sequential circuits

Abstract: The authors describe a number of heuristic algorithms to compact a set of test sequences generated by a sequential circuit automatic test pattern generator (ATPG). A model has been developed and analyzed which shows that finding the optimal solution has an exponential worst-case complexity. To achieve an acceptable run time, some heuristics have been developed that yield good suboptimal solutions in a very short time. Three heuristic algorithms were developed. These algorithms were implemented in C and lex and applied to several of the ISCAS-89 benchmark sequential circuits. They reduce the test length by 17%-63% with a very small time overhead, while having little effect on the original fault overage. >

CPU performance evaluation and execution time prediction using narrow spectrum benchmarking

Abstract: Runs of a benchmark or a suite of benchmarks are inadequate either to characterize a given machine or to predict the running time of some benchmark not included in the suite. Further, the observed results are quite sensitive to the nature of the benchmarks, and the relative performance of two machines can vary greatly depending on the benchmarks used. In this dissertation we propose and investigate a new approach to CPU performance evaluation. The main idea is to represent machine performance and program execution in terms of a high level abstract machine model. The model is machine-independent and thus is valid on any uniprocessor. We have developed tools to measure the performance of a variety of machines, from workstations to supercomputers. We have also characterized the execution of many large applications, including the SPEC and Perfect benchmark suites. By merging these machine and program characterizations, we can estimate execution times quite accurately for arbitrary machine-program combinations. Another aspect of the research has consisted in characterizing the effectiveness of optimizing compilers. Another contribution of this dissertation is to propose and investigate new metrics for machine and program similarity and the information that can be derived from them. We define the concept of pershapes, which represent the level of performance of a machine for different types of computation. We introduce a metric based on pershapes that provides a quantitative way of measuring how similar two machines are in terms of their performance distributions. This metric is related to the extent to which pairs of machines have varying relative performance levels depending on which benchmark is used. A similar metric for programs allows us to compare and cluster them according to their dynamic behavior. All this information helps to identify those parameters in machines and programs which are the most important in determining their execution times. Further, it provides a way for designers and users to identify potential bottlenecks in machines, compilers, and applications.

Automatic synthesis of 3D asynchronous state machines

Abstract: An automatic synthesis tool (3D) for designing asynchronous controllers from burst-mode specifications, a class of specifications allowing multiple input change fundamental mode operation, is described. An algorithm for constructing a three-dimensional next-state table, a heuristic for encoding states, and a procedure for generating necessary constraints for exact logic minimization are presented. The effectiveness of the 3D implementation and the synthesis procedure on numerous designs including a large realistic example (asynchronous data transfer protocol of the SCSI bus controller) is demonstrated. The latency (input to output delay) and the cycle time (time required for the circuit to stabilize after the excitation) for all benchmark designs using a 0.8- mu m CMOS standard cell library are estimated. >

Behavioral synthesis for easy testability in data path scheduling

Abstract: A data path scheduling algorithm to improve testability without assuming any particular test strategy is presented. A scheduling heuristic for easy testability, based on previous work on data path allocation for testability, is introduced. A mobility path scheduling algorithm to implement this heuristic while also minimizing area is developed. Experimental results on benchmark and example circuits show high fault coverage, short test generation time, and little or no area overhead. >

Benchmarks for the 1992 high level synthesis workshop

Abstract: Author(s): Dutt, Nikil; Ramachandran, Champaka | Abstract: This report describes the current status of benchmarks for the 1992 High-Level Synthesis Workshop and suggests guidelines for benchmark submission. The benchmark set currently has 9 designs, where each benchmark includes a VHDL description of the design, documentation of the design's functionality, as well as a set of test vectors and expected outputs for simulation. Documentation of the testing strategy the test vectors are also provided with each benchmark. Although the benchmarks are currently written in VHDL, we have attempetd to organize the benchmarks in a language-independent format so that users can easily translate the benchmarks into their favorite HDL; the representative set of test vectors and expected outputs allow a user to ensure, with some level of confidence, that their HDL descriptions preserve the original behavior of the benchmarks. The current benchmark set contains designs that exercise different types of functionality (e.g., DSP, FSM-based, arithmetic, etc.), as well as different types of HDL behavioral constructs (e.g., nested loops and nested conditionals). We conclude with a suggested set of guidelines for benchmark submission.

Empirical measurements of six allocation-intensive C programs

Abstract: Dynamic memory management is an important part of a large class of computer programs and high-performance algorithms for dynamic memory management have been, and will continue to be, of considerable interest. This paper presents empirical data from a collection of six allocation-intensive C programs. Extensive statistics about the allocation behavior of the programs measured, including the distributions of object sizes, lifetimes, and interarrival times, are presented. This data is valuable for the following reasons: first, the data from these programs can be used to design high-performance algorithms for dynamic memory management. Second, these programs can be used as a benchmark test suite for evaluating and comparing the performance of different dynamic memory management algorithms. Finally, the data presented gives readers greater insight into the storage allocation patterns of a broad range of programs. The data presented in this paper is an abbreviated version of more extensive statistics that are publically available on the internet.

Low-latency message communication support for the AP1000

Abstract: Low-latency communication is the key to achieving a high-performance parallel computer. In using state-of-the-art processors, we must take cache memory into account. This paper presents an architecture for low-latency message comunication and implementation, and performance evaluation.We developed a message controller (MSC) to support low-latency message passing communication for the AP1000, to minimize message handling overhead. MSC sends messages directly from cache memory and automatically receives messages in the circular buffer. We designed communication functions between cells and evaluated communication performance by running benchmark programs such as the Pingpong benchmark, the LINPACK benchmark, the SLALOM benchmark, and a solver using the scaled conjugate gradient method.

Behavioral synthesis for easy testability in data path allocation

Abstract: The first behavioral synthesis scheme for improving testability in data path allocation independent of test strategy is presented. The authors propose two behavioral synthesis-for-test heuristics: improve observability and controllability of registers, and reduce sequential depth between registers. Also presented are algorithms that optimize a behavior-level design using these two criteria while minimizing area. Experimental results for benchmark circuits synthesized by the author's experimental system. PHITS, show that these methods give a high fault coverage in small amounts of CPU time at a low area overhead. >

New CPU benchmark suites from SPEC

Abstract: The author describes the new CPU benchmark suites from the Standard Performance Evaluation Corporation (SPEC). The author describes the reasons for the release, and analyzes and compares new suites with the SPEC Release 1 benchmark suite. The new benchmark CPU suites are CINT2.0 (integer) and CFP2.0 (floating-point). CINT2.0 and CFP2.0 replace the SPEC Release 1 benchmark suite. The new suites provide a wider 'SPECtrum' of performance characterization by adding new application benchmarks. >

Evaluating Benchmark Quality

Abstract: (1992). Evaluating Benchmark Quality. Financial Analysts Journal: Vol. 48, No. 3, pp. 33-39.

Auto-tuning of classical PID controllers using an advanced genetic algorithm

Abstract: Advanced genetic algorithms (GAs) are used to automatically carry out the fine-tuning of the parameter settings of classical PID (proportional plus integral plus derivative) controllers. The basic concept and working principle of GAs are introduced and compared with those of traditional optimization techniques. An advanced GA which can rapidly optimize the parameter auto-tuning process of classical PID controllers is designed based on the GA theory, the authors' experience, and different performance indices, including nonlinear or multiple criteria. The computer implementation of this GA has been accomplished and tested against some benchmark examples. Simulation results demonstrate the efficiency and effectiveness of the proposed tuning technique. >

Summary of results for benchmark problem 13 (3‐d nonlinear magnetostatic model)

Abstract: Benchmark problem 13 of the TEAM Workshop consists of steel plates around a coil (a nonlinear magnetostatic problem). Seventeen computer codes developed by twelve groups are applied, and twenty‐five solutions are compared with each other and with experimental results. In addition to the numerical calculations, two theoretical presentations are given in order to explain discrepancies between the calculations and the experiment.

Hierarchical yield estimation of large analog integrated circuits

Abstract: A hierarchical Monte Carlo methodology for parametric yield estimation of large analog integrated circuits is presented. The methodology exploits the natural functional hierarchy of a circuit and employs a combination of behavioral and regression modeling to replace device-level circuit simulation where possible. Two related techniques for hierarchical yield estimation are demonstrated on a reasonably large BiCMOS circuit combining discrete-time and continuous-time operation. The hierarchical yield estimates agree well with the benchmark of device-level circuit simulation of the complete circuit and are less computationally expensive. >

A practitioner's introduction to database performance benchmarks and measurements

Abstract: Database performance benchmark's provide an important measure for the comparison of database managment systems. This paper provides an introduction to performance benchmarks for centralised databases. The introduction includes benchamrks for transaction processing, such as DebitCredit, TPC-A and TPC-B, and benchmarks for decision support, such as the Wisconsin benchmark and its extension by bull to a vendor benchmark, known as the Single-User Decision Support benchmark