Showing papers on "Biasing published in 1974"

A simple three-terminal IC bandgap reference

Abstract: A new configuration for realization of a stabilized bandgap voltage is described. The new two-transistor circuit uses collector current sensing to eliminate errors due to base current. Because the stabilized voltage appears at a high impedance point, the application to circuits with higher output voltage is simplified. Incorporation of the new two-transistor cell in a three-terminal 2.5-V monolithic reference is described. The complete circuit is outlined in functional detail together with analytical methods used in the design. The analytical results include sensitivity coefficients, gain and frequency response parameters, and biasing for optimum temperature performance. The performance of the monolithic circuit, which includes temperature coefficients of 5 ppm//spl deg/C over the military temperature range, is reported.

Properties of Au, Pt, Pd and Rh levels in silicon measured with a constant capacitance technique

Abstract: Measurements of emission rates and majority carrier capture cross-sections of Au, Pt, Pd and Rh centres in silicon are reported, and the activation energies associated with the different levels of these centres are determined. Where appropriate, our results are compared with values reported in the literature; other results have not been previously reported. The measurement depends on the emission and capture of majority carriers on the centres in the depletion layer of a p-n junction or Schottky barrier. The change in charge state of the centres is monitored by measuring the change in reverse bias applied to the junction necessary to keep the junction capacitance constant. The advantage of this technique, compared with the usual method of keeping the bias voltage constant and measuring the change in capacitance, is demonstrated.

Polarization Phenomena in CdTe Nuclear Radiation Detectors

Abstract: Nuclear radiation detectors made from high resistivity chlorine doped cadmium telluride grown by the travelling heater method were evaluated. Short term performance for ?, s, and ? radiations was good but the long term performance (>1 min) was degraded by a decrease in the full energy pulse height and ?-ray efficiency with time after the bias voltage was applied. A model which considers the effects of deep acceptors which slowly ionize (~103 s) to an equilibrium concentration ~5 × 1011/cm3 can explain the experimental findings on the changes of pulse shape, pulse amplitude, capacitance, energy resolution, and ?-ray efficiency with time. The operating conditions required for satisfactory stability in these detectors may be inconvenient to the user.

Interface and doping profile characteristics with molecular‐beam epitaxy of GaAs: GaAs voltage varactor

Abstract: Studies of the doping profile characteristics of molecular‐beam epitaxy (MBE) of GaAs on GaAs substrates are reported. Highly resistive regions at the substrate—epitaxial‐layer interface, and within the epitaxial layer, may occur if the growth is interrupted. It is shown that almost any arbitrary voltage dependence of the capacitance of such structures can be achieved by varying the dopant deposition rate during epitaxy. To illustrate the versatility of this growth technique, voltage‐variable capacitors have been prepared with Schottky barriers on MBE GaAs layers with precisely controlled doping profiles. Low‐frequency measurements (up to 100 MHz) demonstrate that capacitance variations in excess of a factor of 10 have been achieved by varying the applied bias voltage V from 0.3 V (with no significant forward conduction) to −1.0 V. The feasibility of frequency tuning diodes with C−1/2[sine wave]φ−V, where φ is the effective barrier height, is shown. At ‐3 V bias, cutoff frequencies >40 GHz have been measu...

Semi-conductor non-volatile optical memory device

Abstract: A semiconductor non-volatile optical memory device is constructed by providing light-permeable charge retention means in an insulating layer on a first semiconductor surface into which photo-generated carriers in the surface of the first semiconductor region are injected over the semiconductor-insulator potential barrier by applying reverse bias between the first semiconductor region and a second region forming a rectifying junction with the first semiconductor region. Also disclosed in a non-volatile memory integrated circuit employing one or more of said devices together with light source in the same package. The non-volatile memory integrated circuit operates under low bias voltage and is compatible with a high speed integrated logic circuits.

Mechanism and properties of point‐contact metal‐insulator‐metal diode detectors at 10.6 μ

Abstract: Detection mechanisms of point‐contact MIM diodes at 106 μ wavelength have been studied Detailed measurements of the static current‐voltage characteristic and its first and second derivatives as functions of bias voltage were made simultaneously with infrared sensitivity measurements The results indicate that the static current‐voltage characteristics extend to infrared frequencies We find that thermal effects do not contribute significantly to detection at this wavelength, and that the tungsten whisker acts as a rather efficient receiving antenna The antenna and its shunting capacitance apply a 3×1013‐Hz ac voltage to the diode which in our experiment has amplitude 124 mV, through an impedance which is much less than the junction impedance The diode nonlinearity d2I/dV2 varies from 65×10−5 to 67×10−3 A/V2 as dc bias increases from 0 to 300 mV None of these conclusions apply to detection at 6328 A; it is found that detection in the visible is dominated by thermal or photoconductive effects

Phase control of the voltages applied to opposite electrodes for a cholesteric to nematic phase transition display

Abstract: An electro-optical device employing liquid crystal cell, which consists of a first electrode and a second electrode opposed to the first electrode, at least one of which being light-transparent, and a liquid crystal sandwiched between the first and second electrodes, is driven by voltage pulses with special wave form and changes in its optical transmission or reflection. The liquid crystal is cholesteric liquid crystal having positive dielectric anisotropy. A first circuit connected to the first electrode generates a.c. voltage pulse having phase phi 1 for time duration T1 and a d.c. bias voltage of the same amplitude as that of the a.c. voltage pulse. A second circuit connected to the second electrode generates a.c. voltage having the same amplitude, the same bias as that of the a.c. voltage pulse and phase phi 1 switchable to another phase phi 2 for time interval T2 which is varied with the change of a signal such as image signal. This technique is extended to an X-Y matrix display device which has plural display elements formed at intersections of plural X-electrodes and plural Y-electrodes opposing to and crossing the X-electrodes with a gap.

Monolithic dual mode emitter-detector terminal for optical waveguide transmission lines

Abstract: There is disclosed a monolithic dual mode emitter-detector terminal for optical waveguide transmission lines such as optical data busses or links which terminal serves in one mode to introduce an optical signal onto the line for transmission from one point and in its other mode to read a signal off of the line at the same point. The line includes a plurality of such terminals each of which is a monolithic device having the dual functions or dual modes of sending and receiving. Each terminal comprises a P-N junction diode positioned in optical signal transmissive relationship to the waveguide element. Associated with the diode are switching means to selectively D-C bias the diode in the forward direction for the emitter mode of operation and in the reverse direction for the detector mode of operation. The diode is formed in a direct bandgap semiconductor having overlapping absorption and emission spectra and being doped to produce maximum emission at the shorter wavelengths of the absorption spectrum to increase the efficiency of the diode as an emitter at the expense of its efficiency as a detector which detector efficiency is increased by the Franz-Keldysh effect which shifts the edge of the absorption spectrum to longer wavelengths in the presence of an electric field such as that produced by reverse biasing the diode.

Determination of the energy distribution of interface traps in MIS systems using non-steady-state techniques

Abstract: Experimental techniques are described for determining the energy distribution of interface traps at the semiconductor-insulator interface of MIS devices The device used here was an MNOS capacitor in which the semiconductor was n -type The first technique which is described is that of measuring the thermally stimulated currents The method consists of biasing the capacitor into the accumulation mode at a low temperature thereby filling the traps at the semiconductor oxide interface The device is then biased into the deep-depletion mode in which state the traps remain filled because the temperature is too low to allow the electrons to be thermally excited out of the traps The temperature of the device is then raised at a uniform rate, and the current associated with the release of electrons from the trap is monitored The shape of the I−T characteristic is a direct image of the interface trap distribution is a broad peak with a maximum at 0·35 eV below the bottom of the conduction band, and of height approximately 6 × 10 13 cm −2 eV −1 The experiments were carried out at two heating rates (0·1°K/sec and 0·01°K/sec), and the trap densities so obtained were identical The second method consists of biasing the device into the accumulation mode at a fixed temperature thereby filling the traps at the silicon-silicon oxide interface It is then short-circuited and the non-steady state transient current associated with the release of electrons from the interface traps is monitored The energy distribution of the interface traps in the upper half of the forbidden gap is shown to be readily obtained from the transient currents, and is found to be identical to that obtained using the thermal technique

Method of driving liquid crystal matrix display device

Abstract: In a method of driving with a one-line-at-a-time scanning system a liquid crystal matrix display device in which the picture elements are defined by liquid crystal cell portions formed between the scanning and the signal electrodes arranged in the form of a matrix, the amplitude of the voltage applied to non-selected cells along a selected scanning electrode is made different from the amplitude of the voltage applied to non-selected cells along a selected signal electrode; the amplitude of the voltage (bias voltage) applied to non-selected cells along the selected signal electrode is made equal to the amplitude of the voltage applied to the remaining non-selected cells; and the bias voltage is determined depending on the number of the scanning electrodes, so that the operation margin is further improved.

Automatic development electrode bias control system

Abstract: Title of the Invention AUTOMATIC DEVELOPMENT ELECTRODE BIAS CONTROL SYSTEM Abstract of the Disclosure An automatic control system for the bias on a development electrode in which a plurality of ground-insulated, narrow floating electrodes are spaced along a line adjacent the entrance of a liquid developer applicator unit. the floating electrodes relatively scan image areas of the surface of an organic photoconductor carried by a conductive support moving through the developer unit.Owing to conduction of a charge from the photoconductive surface through the developer liquid to the floating electrodes, they assume potentials each of which is a function of the average potential of the image area subtended by the floating electrode. The potential of each floating electrode is sensed by a high input impedance measuring circuit which selects the potential of the low-est value, amplifies the selected potential and applies the amplified voltage to the biasing electrode or electrodes of the developer system. A fully charged and unexposed area of the surface following the image area produces a reverse bias which cleans the biasing electrodes as the fully charged area passes through the developer system.

An Improved Method of Determining Deep Impurity Levels and Profiles in Semiconductors

Abstract: An improvement is made on the technique of determining the impurity density in a semiconductor from C-V measurements. It is shown that the average impurity density inside the depletion region plays a major part in precise determination of shallow and deep impurity profiles. Measurements of time variation of the bias voltage with the capacitance unchanged are useful for deep levels, and make it feasible to gain knowledge of their energy levels and density profiles simultaneously. These techniques are successfully applied to n-type VPE GaAs on Cr-doped semi-insulating substrates.

Trapping, emission and generation in MNOS memory devices

Abstract: This study is concerned with trapping phenomena occuring at the semiconductor-oxide interface and in the nitride layer of variable-threshold metal-nitride-oxide-semiconductor (MNOS) memory devices. The technique consits of biasing the device in such a manner as to charge or discharge either the interface traps or the nitride traps, or both sets of traps simultaneously. The device is then cooled to low temperature with the bias still applied, and at the low temperature the biasing condition is changed, in order to induce the device into a non-steady mode that is quasi-stable at the low temperature. The temperature of the device is then raised at a constant rate, and the resulting current vs temperature (I-T) characteristics is found to be rich in structure. By means of a series of systematic experiments the various portions of the I-T characteristic are identified with emission of electrons from interface states and the nitride traps, and surface generation. From this data the energy distribution of interface states is determied. It is shown that the memory charge in the nitride is distributed throughout the nitride, and temporary memory charge and semi-permanent memory charge are distinguished.

Characterization of silver coatings deposited from a hollow cathode source

Abstract: Silver coatings of 15–50-μ thickness were deposited from a hollow cathode source with substrate bias voltage between 0 and −80 V, and deposition rates varied from 2 to 30 μ/min. A study of the relationship between the substrate bias voltage and the coating characteristics was made. The crystallographic orientation of the coating varied with bias voltage. The microstructure and microhardness of the coatings were also examined as a function of the bias voltage. The microstructure of the coatings resembled that of sputtered coatings; grain structure was changed from columnar to equiaxed by increasing the bias voltage. With the changes in the morphology of the microstructure, the microhardness of the coating also varied by a factor of 2. The coating fractured in a ductile mode and showed excellent adhesion to its substrate.

Active termination network for clamping a line signal

Abstract: An active termination network for clamping a line signal near the receiving end of a data path. The termination network comprises an NPN transistor, a PNP transistor, the emitter electrodes of the transistors being coupled together to form an input terminal which is connected to the data path, a first bias source for biasing the base of the NPN transistor such that the NPN transistor is caused to turn on when the line signal is below a low state, a second bias source for biasing the PNP transistor such that the PNP transistor is caused to turn on when the line signal is above a high state, a third bias source biasing the collector of the NPN transistor at ground, and a fourth bias source for biasing the collector of the PNP transistor with a negative voltage such that when the line signal fluctuates, the PNP and NPN transistors selectively turn on so as to appropriately clamp the line signal at the high and the low states so as to dissipate ringing energy and thus prevent the detrimental undershoot toward the threshold level. This network lends itself for usage in ECL circuits in which the logic states have a peak-to-peak amplitude of about one volt. In the preferred embodiment the first and second bias sources are developed from a temperature and voltage compensating network connected between the third and fourth bias sources.

Field effect transistor bias circuit

Abstract: A field effect transistor amplifier having a bootstrap bias voltage circuit which is isolated from the output. Isolation of the bootstrap bias voltage circuit allows a plurality of amplifiers to be connected in series to provide a higher bootstrap bias voltage than could be provided by a single bootstrap bias voltage circuit.

Protective circuit for field effect transistor amplifier

Abstract: A transistor amplifier which includes at least one field effect transistor for amplifying an input signal and supplying a corresponding output signal to a load, and a biasing circuit for supplying a predetermined biasing voltage to the field effect transistor so as to operate the latter with a suitable biasing current, is protected against overloading of such transistor by a detecting circuit for detecting an overload condition of the field effect transistor, and a switching circuit operative to maintain the biasing voltage at a predetermined value and to shunt the input signal to the load when an output signal of the detecting circuit exceeds a predetermined value. In a preferred embodiment, the output stage of the amplifier is constituted by a push-pull amplifier having at least a pair of field effect transistors with triode characteristics so as to have excellent characteristics, such as, low switching distortion, high linearity and low output impedance, and thereby be particularly suited for use as an audio power amplifier. Further, the detecting circuit is preferably of the load impedance detecting type, for example, responsive to both the load current and the load voltage, so as to avoid misoperation of the protective circuit, that is, unnecessary shunting of the input signal to the load, as when the latter is constituted by a condenser speaker.

Surface gate-induced conductivity modulated negative resistance semiconductor device

Abstract: A surface gate-induced semiconductor device is provided which exhibits conductivity modulated transient negative resistance. First and second base electrodes are spaced from each other and make ohmic contact to a semiconductor body adjacent a major surface thereof. An insulator layer with a gate electrode thereon is positioned on a major surface of the semiconductor body between the base electrodes. A gate bias voltage is applied to the gate electrode to form an inversion layer in the semiconductor body at the major surface adjacent the gate electrode. The modulation control signal is also applied to the gate electrode to inject minority carriers from the inversion layer into the semiconductor body and conductivity modulate an electric field applied across the body between the base electrodes by an interbase voltage source. The device is characterized by an operational parameter h 1 greater than 1 and preferably greater than 3. The semiconductor devices can be utilized in a spaced parallel array, preferably with common base electrodes, to form a neuristor device capable of propagating a minority carrier traveling wave without attenuation.

Non-linear amplifier

Abstract: A non-linear amplifier is disclosed including an amplifying transistor for amplifying an input signal, an output amplified signal being derived from the amplifying transistor. A series of PN junctions is provided to supply a determined bias voltage to the amplifying transistor. An emitter-follower stage, comprised of at least one emitter-follower transistor amplifier, is connected to an input of the amplifying transistor for compensating the bias voltage applied thereto. In one embodiment, the input signal is amplified by a power of n wherein n PN junctions are connected in parallel with (n-1) emitter-follower transistor amplifiers. The input signal is supplied through the (n-1) emitter-followers to the base electrode of the amplifying transistor. In an alternative embodiment, the input signal is amplified by a power of 1/n wherein (n-1) PN junctions are coupled to the emitter electrode of the amplifying transistor and (n-1) emitter-follower transistors are connected in cascade to the base electrode of the amplifying transistor. In this latter embodiment, an output transistor is connected to the output of the emitter-follower stage.

A useful modification of the technique for measuring capacitance as a function of voltage

Abstract: Measurements of small signal capacitance as a function of applied bias voltage are widely used for the determination of information about metal-insulator-semiconductor (MIS) capacitors. The information that can be derived from the measurements includes interface-state density and flat-band charge density at the insulator-semiconductor (IS) interface, semiconductor doping, and charge stability under bias-temperature stress. A limitation on the use of this measurement method which has until now prevented its even more general application is the requirement that in order to determine C s , the semiconductor space-charge capacitance, with reasonable accuracy the ratio of C s to C I , the insulating layer capacitance, must be ∼ 10. In the present work it is shown that a modification of the usual method can significantly relax this restriction and allow the accurate determination of C s when the ratio C s /C r is as large as 100 or more, In fact, the inherent limit is no longer directly dependent on this ratio but on the noise level in the capacitance measurement. In some cases C s /C I ≥ 1 due to a thick insulating layer, A very large bias voltage is then required to span the capacitance range of interest; commercially available capacitance meters which typically have applied bias capabilities of ±600 V or less may be inadequate. A simple circuit modification has been employed to allow much larger bias voltages (up to ± 7 kV in the present Work) to be applied to the sample without alteration of or damage to the capacitance meter.

Temperature compensating transistor bias device

Abstract: The base-to-emitter bias voltage and current of a high frequency transistor, operating class AB or class A, is derived from a semiconductive bias device consisting of a semiconductive diode junction fed with current from a constant current source to derive a V BE voltage thereacross which is the bias source voltage. This source voltage is applied across the base-to-emitter junction of the RF transistor via the intermediary of a positive temperature coefficient silicon resistor. The diode and silicon resistor are packaged together for mounting on a heat sink common to the transistor, whereby the transistor is compensated for temperature dependent changes in V BE and h FE .

The effect of substrate bias voltage on the bonding of evaporated silver coatings

Abstract: Tensile strengths of bonds between evaporated silver coatings have been found to be related to the bias voltage on the substrate during deposition. Silver coatings between 12 and 50 μ thick were deposited by using a hollow cathode evaporator on 304 stainless steel substrates at bias voltages from 0 to −80 V. Tensile strengths up to 3.85×109 dyn cm−2 (56 ksi) have been achieved at relatively low bonding pressures and temperatures.

Electronic scan methods for plasma displays

Abstract: Apparatus for changing a dimension of the light-producing area in a display element of the type which emits light from any portion of an interface zone across which a voltage exceeding a certain threshold is established, by varying this voltage. A bias voltage source provides a potential along one side of the interface zone, which increases from one end to the other, with respect to the other side. The apparatus is particularly well suited for an electronic bar graph type indicator. Gas discharge devices such as plasma tubes, and LED's are particularly suitable types of display elements.

Method of making a substrate striped planar laser

Abstract: A method of making a diode laser in which a pump current confining channel is formed on the n-side of the diode laser prior to the growth of the active region of the diode laser. The current confining channel is formed by providing two spaced regions in a substrate with the regions being highly resistive to current flow when the diode laser is forwarded biased. Preferably, the regions are formed by diffusion of an impurity into a substrate of a selected conductivity type so as to form secondary p-n junctions on both sides of an intermediate channel, with subsequent growth of other layers of the diode laser providing a primary p-n junction at the boundary of the active laser region. Forward biasing of the primary p-n junction results in reverse biasing of the secondary p-n junctions and pump current confinement to the channel.

Semiconductor light modulating optical wave guide

Abstract: A wave guide device for varying the polarization of a light beam comprises a diode formed of a film of a material such as a glassy amorphous material or a plastic of a first kind of electrical conductivity (P or N) disposed on a substrate of semiconductor material exhibiting the opposite kind of electrical conductivity (N or P), an input optical coupler for coupling a light beam into the glassy film of the diode so that the light will pass through the film by a series of internal reflections, an output optical coupler and means for applying a bias voltage to the diode. In operation, variation of the bias voltage varies the phase of the light beam as it passes therethrough. This change in phase can be detected as a change in the polarization of the light beam exiting from the output coupler.

Core memory with improved sense-inhibit recovery time

Abstract: A three wire 3D core memory which utilizes the same balanced pairs of sense-inhibit conductors to conduct both high energy common mode inhibit currents and low energy differential mode core switching signals includes pairs of antiparallel Schottky diodes interconnecting the conductor pairs at symmetrical positions therealong intermediate the cores of each memory mat. As high energy common mode inhibit currents are generated small deviations from perfect symmetry of electrical characteristics along the sense-inhibit conductors results in the appearance of differential voltages which are substantial in comparison to switching signal voltages. The sense-inhibit recovery time required for dissipation of these spurious differential voltage signals before a memory read cycle can proceed consumes a substantial portion of a memory cycle for large stacks. The Schottky diodes substantially reduce this recovery time to greatly improve memory cycle time by limiting the differential voltages to the low threshold forward conduction voltage thereof and by appearing as transmission line discontinuities to break up differential voltage signals which remain after termination of an inhibit current into higher frequency harmonic components which are more rapidly attenuated. The Schottky diodes have no substantial effect upon the sensed output switching signals because the threshold forward bias voltage of the Schottky diodes is greater than the peak switching signal voltage.

Semiconductor voltage transformer

Abstract: A semiconductor device for increasing voltage levels is disclosed. The device comprises an MIS structure formed over a pn junction. Suitable biasing of the metal electrode depletes the semiconductor surface of majority carriers and causes the accumulation of minority carriers from the bulk. At the same time a bending of the energy bands in the n and p regions is effected forming a potential barrier. When the electrode is switched to a reference potential, the minority carriers are raised to a higher potential and are prevented from returning to the bulk of the semiconductor by the potential barrier. An electrical path is provided for removing the minority carriers from the surface and combining the signal with the applied electrode potential.

Method and apparatus for measurement of trap density and energy distribution in dielectric films

Abstract: Trap densities in dielectric films can be determined by tunnel injection measurements when the film is incorporated in an insulated-gate field-effect transistor (IGFET). Under applied bias to the transistor gate, carriers (electrons or holes) tunnel into traps in the dielectric film. The resulting space charge tends to change channel conductance. By feeding back a signal from the source contact to the gate electrode, channel conductance is held constant, and by recording the gate voltage as a function of time, trap density can be determined as a function of distance from the dielectric-semiconductor interface. The process is repeated with the gate bias voltage at different levels in order to determine the energy distribution of traps as a function of distance from the interface.

Electron beam irradiation effects in thick-oxide MOS capacitors

Abstract: The capacitors were irradiated with an electron beam at doses of 1011 to 1017 electrons/cm2 and energies of 5 kV and 15 kV. C-V measurements were made to characterise the effects of irradiation. The C-V curves revealed a positive fixed charge accumulation in the oxide at dose levels above 1013 electrons/cm2. In the thicker oxide samples at 5 kV there was evidence of negative charge trapping at the lower dose levels changing to positive at the highest dose. In all cases, there was a reversal in the sense of the hysteresis effects in the C-V curves above 1015 electrons/cm2, implying slow surface states which could follow the d.c. bias voltage but not the a.c. test signal. There was also a marked increase in the magnitude of the turn-on voltage for strong inversion implying an increase in fast surface states or lateral ionic charge nonuniformities.