Showing papers on "Biasing published in 1993"

Increased linear dynamic range by low biasing the Mach-Zehnder modulator

Abstract: Operating a Mach-Zehnder modulator at an optical bias below the conventional 50% (quadrature) bias is investigated. Theoretical distortion curves as a function of bias have been calculated and experimentally verified. These curves show that (single octave) linear dynamic range increases as the bias is lowered, so long as optical power at the detector can be maintained just below the saturation level or laser noise limit. This method thus provides a way for very large optical power to be used to benefit linear dynamic range. Theoretically, 20 dB of excess optical power, attenuated through low biasing, can result in an increase in linear dynamic range of 15 dB. >

Semiconductor integrated circuit incorporated with substrate bias control circuit

Abstract: The semiconductor IC according to this invention comprises an internal circuit including a plurality of transistors formed on a P-type or an N-type substrate (or a well) which carries out a prescribed signal processing operation during the time of operation mode, a standby detection circuit which generates a standby detection signal of active level by detecting standby mode, a bias potential generating circuit which generates a forward bias potential from the substrate (well) of the transistor to the source electrode, and a switching circuit which supplies to the substrate (well) the potential of the source electrode and the bias potential in response to the active level and the inactive level, respectively, of the standby detection signal. At the time of the operation mode, a high speed operation is secured by bringing the transistors to a low threshold voltage by receiving the supply of the bias potential, while at the time of the standby mode, the generation of malfunctions and defective data holding are prevented and the power consumption is saved by raising the threshold voltage of the transistors through a halt of supply of the bias voltage to the substrate (well).

An ultrasonic surgical handpiece and an energy initiator to maintain the vibration and linear dynamics

Abstract: An ultrasonic oscillator (46) drives a tool at a set frequency. An amplitude control runs the oscillator (46) to set the vibration level. A frequency regulator joins the amplitude and the oscillator (46). A control feedback loop (49), in the frequency regulator, keeps handpiece linear dynamics. An operational transconductance amplifier (52), in the oscillator (46), governs gain of the loop (49). A circuit (55) connects to the control to retard the rate of current application over time to the amplifier (52). The circuit (55) has switching to either retard the rate or reset for start up. The amplifier (54) is a current output device with current directly proportional to the bias current and input voltage with bias as gain change for the loop (49). The circuit (55) limits the bias to the amplifier (54) to modify frequency response and output current. A capacitor delays application of the bias to the amplifier (54). Replaceable tools of various lengths or shapes positioned along an axis vibrate for surgery at the frequency and a wave length. Tools longer than one wavelength and of configurations tuned to oscillate around the frequency resonate as a function of their material, length and configuration. A flue (17) surrounds the tool and has a hollow elongate semi rigid central body (28) about an axis with a funnel (29), at one end thereof and a nozzle (30), at the other to direct annular irrigant/coolant flow therethrough. The funnel (29) and nozzle (30) are resilient. Reinforcing ridges (32), inside the nozzle (30), act to maintain concentricity between the flue (17) and nozzle tip and channel irrigant thereabout.

High-efficient class F GaAs FET amplifiers operating with very low bias voltages for use in mobile telephones at 1.75 GHz

Abstract: High-efficiency class F GaAs power FET amplifiers working with a very low drain bias voltage of 3 V, for use in portable telephones, are reported. The transistor used has an optimized gate periphery of 2000 mm and a gate length of 0.7 mu m. Under class F operation with a drain voltage of 3 V, it has demonstrated an output power of 24.5 dBm with 71% of power-added efficiency at the operating frequency of 1.75 GHz. Output harmonic levels lower than -25 dBc have been measured. The results obtained present the state of the art as published for low-bias-voltage, low-power-consumption amplifiers for mobile telephone systems. >

Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs)

Abstract: Analytical expressions are presented for subthreshold current reduction in a decoded-driver by self-reverse biasing, which is inherently required for low-voltage, low-power, high-speed DRAM's for portable equipment. The scheme involves inserting a switching MOS transistor between the driver circuits and its power supply line. The subthreshold current of the decoded-driver is reduced to the order of 10/sup -3/ in the practical temperature range (250-350 K) with 254 mV of self-reverse biasing voltage, while the delay time is only 3% more than in conventional schemes. The transition time of 1 ms from the operating state to the low subthreshold current state is sufficient to reduce the subthreshold current. The rapid recovery time of 1 ns from the low subthreshold current state does not interrupt the start of normal operation. The subthreshold current reduction was confirmed experimentally using a test chip fabricated with 0.25- mu m technology. >

Guard ring design for high voltage operation of silicon detectors

Abstract: The termination of the depletion zone towards the non-depleted part of silicon affects the total device leakage current, the long term stability, the noise level and the radiation hardness of silicon detectors. This paper describes computer simulations and experiments to develop guard ring structures for use in silicon detectors requiring thick depletion layers, high operating voltages and biasing beyond depletion without increase in the leakage current and the noise. Computer simulation of a simplified structure is used to understand the influence from the oxide charges and the substrate doping concentration for a segmented guard structure with several floating diffusion strips. Results from the simulations are compared with measurements on devices. The numerical results are found to be in agreement with experimental data. It is found that segmented guard structures with floating diffusion strips have high breakdown voltages and low leakage currents. The effects of floating metal field plates over the oxide between the floating diffusion strips are studied on two different guard structures by measuring the potential on the diffusion strips and the leakage currents in the guard and active diode. The results show that floating intermediate field plates reduces the influence from oxide charges and stabilises the device against environmental influence.

Phase formation and microstructure changes in tantalum thin films induced by bias sputtering

Abstract: The effects of argon‐ion bombardment on the structure and properties of sputtered tantalum films have been studied. Applied substrate bias voltage was used to control the bombardment energy in a hollow‐cathode‐enhanced low‐pressure magnetron sputtering system. The films were characterized by x‐ray diffraction, electrical measurements, Rutherford backscattering spectrometry, and stress measurements. The findings concerning the effects of negative substrate bias on film resistivity and structure run counter to earlier work. In particular, as opposed to results found in many early studies, which primarily involved higher‐pressure discharges, at zero bias voltage the films have low resistivity and contain the bcc phase. Increasing the bias to −100 V, increases the resistivity dramatically, and induces formation of β‐Ta, with no significant change in film impurity levels. The difference from earlier work is attributed to the lower relative impurity flux, as well as more energetic substrate bombardment in low‐p...

Semiconductor integrated circuit.

Abstract: An LSI containing a voltage drop circuit for dropping an external power source voltage to obtain an internal power source voltage and a substrate biasing voltage generator circuit for applying a reverse biasing voltage to a semicondictor substrate thereof having one surface formed with an internal circuit is disclosed in which a delay of start of operation of the LSI and an increase of power consumption due to delay of increase of the internal power source voltage as an operating power source voltage of said substrate biasing voltage generator circuit after the application of the external power source voltage are avoided The LSI includes the voltage drop circuit for generating the internal power source voltage, the substrate biasing voltage generator circuit for generating the substrate biasing voltage and a power-on circuit for monitoring a voltage rising rate of the external power source after application thereof The substrate biasing voltage generator circuit includes a standby mode substrate biasing voltage generator circuit portion operable when the LSI is in a standby mode and an active mode substrate biasing voltage generator circuit portion operable at a time the external power source voltage is applied and when the LSI is in an active mode The active mode substrate biasing voltage generator circuit portion is responsive to a control signal generated by the power-on circuit according to a result of the monitor to switch its substrate current absorbing capability at the application of the external power source voltage to the LSI in two steps In the LSI according to the present invention, with the application of the external power source voltage, the power-on circuit causes the active mode substrate biasing voltage generator circuit to be operated with the external power source voltage and then with the internal power source voltage Therefore, even if there is a delay in rising of the internal power source voltage in an initial stage of the application of the external power source voltage, the substrate biasing voltage is lowered at a higher rate than when it operates with only the internal power source voltage, reliably following the rising of the external power source voltage, so that the biasing voltage reaches a predetermined voltage value reliably at a start of operation of the LSI Therefore, there is no increase of power consumption of the LSI after start of operation due to reduced threshold voltage of the MOS transistor which is caused by delay of reduction of the substrate biasing voltage due to delay of operation of the voltage drop circuit In the conventional 16 M bits DRAM, when the substrate biasing voltage generator circuit is operated with the internal power source voltage of 33 V obtained by dropping the external power source voltage of 5 V to apply a substrate biasing voltage of -22 V, there may be a case where the standby current in the standby mode is increased from 300 A to about 1 mA depending upon a delay of rising rate of the internal power source voltage There is no such increase of power consumption or damage of memory cell content in the 16 M bit DRAM to which the present invention is applied

Method of using source bias to increase threshold voltages and/or to correct for over-erasure of flash eproms

Abstract: The method of this invention allows use of a smaller wordline voltage Vp1 during programming In addition, the method results in a relatively narrow distribution of threshold voltages Vt when used to flash program an array of memory cells (10) The method of this invention increases compaction gate-current efficiency by reverse biasing the source (11)/substrate (23) junction of the cell being programmed The reverse biasing is accomplished, for example, by applying a bias voltage to the source (11 ) or by placing a diode (27), a resistor (29) or other impedance in series with the source (11) The reverse biasing limits the source current (Is) of cell being programmed and of the entire array during flash-programming compaction

Single-event current transients induced by high energy ion microbeams

Abstract: Focused high-energy ion microbeams were applied to the study of the basic mechanisms of single-event upset. Waveforms of the current transients induced by He-, C-, O- and Fe-ion strikes on silicon diodes were measured by applying extremely low beam currents of an order of 10 fA and a wide-bandwidth digitizing sampling technique. Total collected charges are evaluated from the transient currents as a function of LET (linear energy transfer), bias voltage, and doping level, and are compared with theoretical values calculated using conventional single-event models. It is found that irradiation effects on the total collected charges can be explained by the introduction of displacement atoms calculated using Coulomb potential and the Kinchin-Pease model. >

Emission spectroscopy during direct‐current‐biased, microwave‐plasma chemical vapor deposition of diamond

Abstract: Optical emission spectroscopy was used to investigate dc biasing during diamond film synthesis in a microwave plasma. These measurements show that biasing produces significant changes near the substrate (i.e., close to the sheath region). Increasing the negative bias voltage (Vb) from 0 to −180 V in a CH4/H2/Ar (4/496/30 sccm) mixture increases the intensities of the hydrogen Balmer α and β lines. The relative concentrations of neutral atomic hydrogen were estimated by using an Ar(750.4 nm) emission line as an actinometer. At 38 Torr, increasing Vb from 0 to −150 V increased the concentration of atomic hydrogen by more than 20%. In addition, increasing Vb also increased the electron temperature near the substrate. These effects are likely to play an important role in the enhanced diamond nucleation that has been observed after negative‐biased pretreatment.

Flexible radiation probe

Abstract: This invention describes a flexible radiation probe 2 which has a pair of insulated gate field effect transistors integrated into the same substrate each having a gate, source and drain. The transistors are mounted at the end of a flexible circuit board 6. The flexible circuit board has conductive tracks 16 which connect the gate, source and drains of each of the transistors to a connection at an opposite end of the flexible circuit board 6. This connection end may then be connected to a suitable differential biasing circuit for biasing the transistors, and a circuit for reading the differential threshold voltages of the transistors. This differential threshold voltage being indicative of radiation received by the transistors when exposed in the bias mode. The flexible circuit 6 allows the probe 2 to be used in catheters or similar medical equipment.

High radial confinement mode induced by dc limiter biasing in the HIEI tandem mirror.

Abstract: A transition from low to high radial confinement mode is triggered by biasing a limiter in the HIEI tandem mirror. Positive dc biasing gives rise to reduction of fluctuation level in density and potential in the periphery, drop of neutral line emission, and bifurcation in limiter current. After the transition, the plasma exhibits density rise in the bulk and steepening of the density gradient. Significant radial rotational shear is observed when the edge turbulence is suppressed by the biasing. The total feature shows similar characteristics of [ital L]- to [ital H]-mode transition observed in tokamak devices.

Effects of platinum content and substrate bias on the structure and magnetic properties of CoCrPt/Cr thin films

Abstract: The effects of the Pt content (0–40 at. %) and the developed dc substrate bias voltage (0 to −190 V) on the magnetic properties and structure of rf sputtered CoCrPt/Cr films with two different remanent magnetization‐thickness products Mrδ (0.7 and 2.3 memu/cm2) were studied. It was demonstrated that a wide range of in‐plane coercivities (500–3450 Oe) can be easily obtained in these films. The addition of Pt affected the magnetic properties of the films through changes of the lattice parameter, texture, and phase composition. A maximum in the in‐plane coercivity exists for moderate amounts of Pt. The saturation magnetization decreased monotonically with increasing Pt content. rf substrate bias increased the in‐plane coercivity and altered the character of the magnetic interactions through changes of the stress, texture and microstructure of the magnetic layer.

Influence of substrate bias on the properties of a-C:H films prepared by plasma CVD

Abstract: We have measured photoluminescence (PL) and Raman spectra for a series of amorphous carbon (a-C:H) films prepared in a RF-plasma CVD system. The negative bias voltage was varied between 0V and 950V. The samples seem to consist of two components. One polymeric component has a high band gap and gives strong luminesence above 2.1 eV with 0.6 eV band width. The second component shows the Raman spectrum that is typical for the sp 2 -clusters of hard carbon. We find that the hard carbon component seems to be absent for zero bias voltage. The PL for this sample, however, is strongest. We find a fatiguing of the luminescence during laser excitation. This fatiguing is weaker at 120 K, resulting in a higher PL-efficiency for this temperature.

Substrate bias generating circuit

Abstract: A substrate bias generating circuit (20) provides a substrate bias voltage to a substrate (50) of an integrated circuit. A voltage-to-current converter circuit (22) provides a constant current proportional to a bandgap generated reference voltage. P-channel transistors (34 and 35) then provide constant current sources for a voltage level sensing circuit (36) based on the bandgap generated reference voltage. The voltage level sensing circuit (36) monitors the level of the substrate bias voltage, and when the substrate bias voltage reaches a predetermined voltage level, provides a first control signal for activating an oscillator (47). A level converter (43) is provided to amplify, or level convert the first control signal for more reliable control of the oscillator. A substrate bias generating circuit (20) provides a precisely controlled substrate bias voltage to the substrate (50) that is independent of process, temperature, and power supply variations.

Hybrid photomultiplier tube with high sensitivity

Abstract: A focused electron/bombarded (FEB) ion detector comprising an MCP, focusing means, and a collection anode disposed in a detector body The collector anode includes a diode for receiving the focused output electron beam from the MCP The gain between the input ion current to the MCP and the detector output signal from the diode is on the order of 1-100 million, depending on the device configuration and applied biasing voltages A hybrid photomultiplier tube includes a photocathode, a photodiode for collecting and multiplying electrons emitted by the photocathode and providing an output signal and electrodes for focusing the electrons on the photodiode A vacuum envelope encloses a vacuum region between photocathode and the detector A conductor disposed on or adjacent to a sidewall of the vacuum envelope reduces the effect of electrical charges on the inside wall of the vacuum envelope on the trajectories of the electrons

Ferroelectric high Tc superconductor RF phase shifter

Abstract: The Ferroelectric high Tc superconductor RF Phase Shifter contains a ferroelectric medium and a film of a single crystal high Tc superconductor is used as the conductors. Between the ferroelectric medium and the input, there is a quarter-wave, dielectric or ferroelectric or the same material as used for the phase shifter, matching transformer. Between the ferroelectric medium and the output, there is a quarter-wave, dielectric, ferroelectric or the same material as used for the phase shifter, matching transformer. A bias field is connected across the top and bottom surfaces of the active ferroelectric medium. When a bias field is applied across the surfaces of the ferroelectric medium, the permittivity is reduced and as such the velocity of propagation is increased. This causes an increase in the effective electrical length of the phase shifter or a phase difference or time delay. Increasing the bias voltage increases the phase shift. The ferroelectric high temperature superconductor RF phase shifter may be embedded as a part of the monolithic integrated circuit. The ferroelectric high Tc superconductor RF phase shifter may be constructed of thin film and ferroelectric liquid crystal. The ferroelectric material is operated above its Curie temperature.

Scaling of terahertz radiation from large-aperture biased InP photoconductors.

Abstract: We present, for biased InP emitters, the dependence of the generated terahertz radiation on bias field and optical fluence for optical fluences of 0.01–1.0 mJ/cm2 and bias fields as high as 12 kV/cm. The radiated electric field scales linearly with the bias field up to 12 kV/cm and exhibits monotonic saturation behavior, radiating half the maximum field at an excitation fluence of 0.058 mJ/cm2.

Self-biased cascode current mirror having high voltage swing and low power consumption

Abstract: A self-biased cascode current mirror includes a current mirror (60), and a cascode bias generator (50). The cascode bias generator (50) includes a resistor (51) to provide a bias voltage for the current mirror (60). The current mirror (60) includes cascode transistor (64) and two mirror transistors (62, 63). The bias voltage is approximately equal to a minimum saturation voltage of the cascode transistor (64) plus a gate-source voltage of the transistor (63) of the current mirror (60). The self-biased cascode current mirror (60) has a high output impedance and high voltage swing while providing low power consumption and requiring a small layout area.

Femtosecond optical response of Y-Ba-Cu-O thin films: The dependence on optical frequency, excitation intensity, and electric current.

Abstract: We have performed a series of femtosecond reflectivity experiments on various Y-Ba-Cu-O thin films at temperatures ranging from 12 to 300 K. In particular, the dependence of the optical response on probing laser frequency, pumping laser intensity, and bias electric current has been measured. Results obtained at room temperature provide quantitative information on the position of the Fermi level in films with different oxygen content. Systematic analysis of the measurements performed in the superconducting state indicates that the optical response associated with nonequilibrium properties of Y-Ba-Cu-O depends strongly on excitation intensity, sample thickness, and bias current. The results cannot be satisfactorily interpreted as the relaxation dynamics of quasiparticles, and a simple two-fluid model is shown to fail to explain data obtained under low laser excitation. Several tentative explanations are proposed, which provide a more comprehensive understanding of the transient optical response of Y-Ba-Cu-O.

A temperature-stabilized SOI voltage reference based on threshold voltage difference between enhancement and depletion NMOSFET's

Abstract: A temperature-stabilized silicon-on-insulator (SOI) voltage reference is presented. It is based on the threshold voltage difference between enhancement and depletion SOI NMOSFETs that have the same channel doping concentration but of opposite type. The circuit has been realized on a SIMOX wafer using an n/sup +/-poly gate and a LOCOS isolation process. The threshold voltages of the enhancement and depletion SOI NMOSFETs show almost the same temperature dependence when a suitable back-gate bias is applied. Experimental results show a temperature coefficient of 33.8 p.p.m./ degrees C over the temperature range of -50 to 75 degrees C. The variation of threshold voltage difference with temperature is small, and this circuit becomes more advantageous as the front-gate oxide is scaled down or the bias current is reduced. >

Voltage-tunable, multicolor infrared detectors

Abstract: A tunable radiation detector comprises a superlattice structure having a rality of quantum well units each separated by a first potential barrier and each having at least two doped quantum wells separated by a second potential barrier. The wells each have a lower energy level and a higher energy level. The first potential barriers substantially impede electrons at the lower levels from tunneling therethrough. The second potential barriers permit electrons at the lower levels to tunnel therethrough and prevent energy-level coupling between adjacent ones of the doped quantum wells. A biasing circuit is connected across the semiconductor superlattice structure. A photocurrent sensor is provided for measuring the amount of radiation absorbed by the semiconductor superlattice structure. The superlattice structure is made a part of a hot-electron transistor for providing amplification.

Micromachined thermal switch

Abstract: A monolithic micromachined temperature switch obviates the necessity of assembling discrete components and also allows the temperature switch to be disposed in a relatively small package. In one embodiment of the invention, the temperature switch includes a bimetallic element operatively coupled to a pair of electrical contacts. In order to minimize contact wear due to contact arcing, a biasing force such as an electrostatic force is applied to the switch which provides snap action of the electrical contacts in both the opening and closing directions which enables the temperature set point to be adjusted by varying electrostatic force biasing voltage. In an alternate embodiment of the invention, the biasing force for providing the snap action effect can be eliminated by substituting the movable contacts with a field effect transistor with a movably mounted gate terminal. With such an arrangement since little or no current would normally flow through the gate terminal, the need to reduce contact arcing normally resulting from contact bounce would thus be eliminated. Thus, in such an embodiment, a biasing force such as an electrostatic biasing force is not necessary unless a snap action with hysteresis is desired. In alternate embodiments of the invention, the temperature switch may be formed with an integral power transistor for switching relatively large currents. The temperature switch may also be provided with an integrally formed capacitor for reducing the effects of switching inductive loads, such as relays and the like.

Current‐voltage characteristics and interface state density of GaAs Schottky barrier

Abstract: A density distribution of the interface states in GaAs Schottky barrier was derived for the first time from observed nonideal I‐V characteristics of a GaAs Schottky barrier with an oxidized interface. With increasing forward bias voltage, the ideality factor increases and then decreases after passing a maximum. Fermi level of the interface states shifts with the applied bias in the interfacial layer model adopted for the analysis. The obtained energy level of the interface states is in agreement with a previously reported value. However, the absolute magnitude of the state density is quite small compared with that obtained from the weak dependence of the barrier height on metal work functions. Implications of this result are discussed.

Dynamic random access memory device having power supply system appropriately biasing switching transistors and storage capacitors in burn-in testing process

Abstract: A power supply system (15) incorporated in a dynamic random access memory device distributes a step-down power voltage (Vint) and a boosted voltage (Vboot) to a sense amplifier unit (13a) and a word line driver (12a) for allowing switching transistors of the memory cells to transfer the step-down voltage level to the storage capacitor without any voltage drop in read-out and write-in modes, and the switching transistors and the storage capacitors are subjected to inspections through a burn-in testing process before delivery from the manufacturing factory so as to actualize potential failure; however, either switching transistors or storage capacitors are insufficiently stressed in the burn-in testing process, and the power supply system changes the ratio of the boosted voltage to the step-down power voltage between the read-out and write-in modes and the burn-in testing process so that the switching transistors and the storage capacitors are sufficiently stressed.

Dependence of timing jitter on bias level for single-mode semiconductor lasers under high speed operations

Abstract: The dependence on the bias level of some quantities characterizing optical pulse statistics, such as the turn-on time, pulsewidth, maximum output photon number, and average output power, of single-mode semiconductor lasers is numerically analyzed at frequencies in the gigahertz range. Periodic modulation and pseudorandom word modulation are considered. In the former regime, timing jitter is shown to be rather independent of the bias current. In the latter regime, timing jitter becomes larger when biasing above threshold than when biasing below threshold. This larger jitter is found to be associated with a bimodal probability distribution of the turn-on time, which yields undesirable pattern effects. A privileged bias, slightly below threshold, suppresses these pattern effects making the laser response almost independent of previous input bits. For such bias value the probability distribution functions of the turn-on time in the case of the periodic and pseudorandom word modulation coincide. >

Circuit for conversion from CMOS voltage levels to shifted ECL voltage levels with process compensation

Abstract: A CMOS level conversion circuit for converting voltage levels between CMOS levels and shifted ECL levels, where the shifted ECL levels are referenced to the VDD supply voltage of the CMOS circuit. The circuit contains a pFET connected between the VDD supply voltage and the output terminal and an nFET connected between the output terminal and circuit ground. The input signal is connected to the gate input of the nFET. A second pFET is connected in parallel to the nFET between the output terminal and ground. A bias voltage is supplied to the gate inputs of both pFETs, to cause the output terminal to have a shifted ECL logic one voltage when the gate to the nFET is low. The pFETs are fabricated within the integrated circuit to be located very close to each other to compensate for variations in the CMOS integrated circuit manufacturing process.