Biasing

About: Biasing is a research topic. Over the lifetime, 29422 publications have been published within this topic receiving 301035 citations.

First-principles theory of atom extraction by scanning tunneling microscopy.

Abstract: A new method to provide a self-consistent electronic structure, field, and current distribution for an atomistic bielectrode system with applied bias voltages is presented. In our method the scattering waves are calculated by a step-by-step recursion-matrix method and two different Fermi levels are assigned to each electrode in accord with a given applied bias voltage. The method is applied to the scanning tunneling microscope (STM) system around the contact region. The tip-surface chemical interaction induced by the electric fields is shown to be important for the extreme specificity of atom extraction by STM.

PLL Based on Self-Biased Techniques

Abstract: Delay-Iorked loop (DLL) and phase-Iorked loop (PLJ") designs based upon self-biased techniques are presented. The DLL and PLL designs achieve process technology inde­ pendence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancel­ lation, and, most importantly, low input tracking jitter. Both the damping factor and the bandwidth to operating frequency ratio areIetermined cmpletely by a ratio of capacitances, Self-biasing aVOids the necessity for external biasing, which can require special bandgap bias circuits, by generating all of the internal bias voltages and currents from each other so that the bias levels are eomJletely determined by the operating conditions. Fabricated in a 0.5-llm )V -well CMOS gate array process, the PLL achieves an operating frequency range of 0.0025 MHz to 550 MHz and input tracking jitter of 384 ps at 250 MHz with 500 m V of low frequency square wave supply noise.

Semiconductor integrated circuit.

Abstract: An LSI containing a voltage drop circuit for dropping an external power source voltage to obtain an internal power source voltage and a substrate biasing voltage generator circuit for applying a reverse biasing voltage to a semicondictor substrate thereof having one surface formed with an internal circuit is disclosed in which a delay of start of operation of the LSI and an increase of power consumption due to delay of increase of the internal power source voltage as an operating power source voltage of said substrate biasing voltage generator circuit after the application of the external power source voltage are avoided The LSI includes the voltage drop circuit for generating the internal power source voltage, the substrate biasing voltage generator circuit for generating the substrate biasing voltage and a power-on circuit for monitoring a voltage rising rate of the external power source after application thereof The substrate biasing voltage generator circuit includes a standby mode substrate biasing voltage generator circuit portion operable when the LSI is in a standby mode and an active mode substrate biasing voltage generator circuit portion operable at a time the external power source voltage is applied and when the LSI is in an active mode The active mode substrate biasing voltage generator circuit portion is responsive to a control signal generated by the power-on circuit according to a result of the monitor to switch its substrate current absorbing capability at the application of the external power source voltage to the LSI in two steps In the LSI according to the present invention, with the application of the external power source voltage, the power-on circuit causes the active mode substrate biasing voltage generator circuit to be operated with the external power source voltage and then with the internal power source voltage Therefore, even if there is a delay in rising of the internal power source voltage in an initial stage of the application of the external power source voltage, the substrate biasing voltage is lowered at a higher rate than when it operates with only the internal power source voltage, reliably following the rising of the external power source voltage, so that the biasing voltage reaches a predetermined voltage value reliably at a start of operation of the LSI Therefore, there is no increase of power consumption of the LSI after start of operation due to reduced threshold voltage of the MOS transistor which is caused by delay of reduction of the substrate biasing voltage due to delay of operation of the voltage drop circuit In the conventional 16 M bits DRAM, when the substrate biasing voltage generator circuit is operated with the internal power source voltage of 33 V obtained by dropping the external power source voltage of 5 V to apply a substrate biasing voltage of -22 V, there may be a case where the standby current in the standby mode is increased from 300 A to about 1 mA depending upon a delay of rising rate of the internal power source voltage There is no such increase of power consumption or damage of memory cell content in the 16 M bit DRAM to which the present invention is applied

Method of using source bias to increase threshold voltages and/or to correct for over-erasure of flash eproms

Abstract: The method of this invention allows use of a smaller wordline voltage Vp1 during programming In addition, the method results in a relatively narrow distribution of threshold voltages Vt when used to flash program an array of memory cells (10) The method of this invention increases compaction gate-current efficiency by reverse biasing the source (11)/substrate (23) junction of the cell being programmed The reverse biasing is accomplished, for example, by applying a bias voltage to the source (11 ) or by placing a diode (27), a resistor (29) or other impedance in series with the source (11) The reverse biasing limits the source current (Is) of cell being programmed and of the entire array during flash-programming compaction

Highly sensitive fast-response UV photodiode fabricated from rutile TiO2 nanorod array on silicon substrate

Abstract: An ultraviolet photodiode based on rutile TiO2 nanorods, which were grown on p-type Si substrate seeded with a TiO2 layer, was synthesized by radiofrequency reactive magnetron sputtering. Chemical bath deposition was performed to grow rutile TiO2 nanorods. X-ray diffraction and field emission-scanning electron microscopy were conducted to determine the structural and optical properties of the sample. The synthesized TiO2 nanorods exhibited tetragonal rutile structure. The device showed 3.79 × 102 sensitivity when it was exposed to 325 nm light (1.6 mW/cm) at 5 V bias voltage. In addition, the internal gain of the photosensor was 4.792 and the photoresponse peak was 460 mA/W. The photocurrent was 6.09 × 10−4 A. The response and recovery times of the PD were 50.8 and 57.8 ms, respectively, upon illumination of a pulsed UV light (325 nm, 1.6 mW/cm2) at 5 V bias voltage.