Biasing

About: Biasing is a research topic. Over the lifetime, 29422 publications have been published within this topic receiving 301035 citations.

Noise reduction output buffer

Abstract: A circuit for compensating for MOS device response to supply voltage variations, as well as temperature and process variations, in an integrated circuit device. The compensation circuit produces a reference voltage which modulates the gate bias voltage of a MOS transistor such that the gate-to-source bias of the MOS transistor is varied to compensate for variations in the supply voltage as well as for variations in the temperature and manufacturing process. The circuit pulls up the reference voltage toward the supply voltage as the supply increases, thereby increasing the gate drive on the MOS transistor. The circuit provides compensation for both AC and DC supply variations. The MOS transistor is used to modulate the available current sinking capability in an IC device output buffer, such that as the MOS gate drive increases, the current sinking capability is reduced, thereby slowing the output state transitions as the supply increases, and reducing noise caused by supply variations.

A 3.4 – 6.2 GHz Continuously tunable electrostatic MEMS resonator with quality factor of 460–530

Abstract: In this paper we present the first MEMS electrostatically-tunable loaded-cavity resonator that simultaneously achieves a very high continuous tuning range of 6.2 GHz:3.4 GHz (1.8:1) and quality factor of 460–530 in a volume of 18×30×4 mm3 including the actuation scheme and biasing lines. The operating principle relies on tuning the capacitance of the loaded-cavity by controlling the gap between an electrostatically-actuated membrane and the cavity post underneath it. Particular attention is paid on the fabrication of the tuning mechanism in order to avoid a) quality factor degradation due to the biasing lines and b) hysteresis and creep issues. A single-crystal silicon membrane coated with a thin gold layer is the key to the success of the design.

Temperature dependent negative capacitance behavior in (Ni/Au)/AlGaN/AlN/GaN heterostructures

Abstract: The temperature dependent capacitance–voltage (C–V) and conductance–voltage (G/x–V) characteristics of (Ni/Au)/Al0.22Ga0.78N/AlN/GaN heterostructures were investigated by considering the series resistance (Rs) effect in the temperature range of 80–390 K. The experimental results show that the values of C and G/x are strongly functioning of temperature and bias voltage. The values of C cross at a certain forward bias voltage point (�2.8 V) and then change to negative values for each temperature, which is known as negative capacitance (NC) behavior. In order to explain the NC behavior, we drawn the C vs I and G/x vs I plots for various temperatures at the same bias voltage. The negativity of the C decreases with increasing temperature at the forward bias voltage, and this decrement in the NC corresponds to the increment of the conductance. When the temperature was increased, the value of C decreased and the intersection point shifted towards the zero bias direction. This behavior of the C and G/x values can be attributed to an increase in the polarization and the introduction of more carriers in the structure. Rs values increase with increasing temperature. Such temperature dependence is in obvious disagreement with the negative temperature coefficient of R or G reported in the literature. The intersection behavior of C–V curves and the increase in Rs with temperature can be explained by the lack of free charge carriers, especially at low temperatures.

The behavior of the I‐V‐T characteristics of inhomogeneous (Ni∕Au)–Al0.3Ga0.7N∕AlN∕GaN heterostructures at high temperatures

Abstract: We investigated the behavior of the forward bias current-voltage-temperature I-V-T characteristics of inhomogeneous Ni/ Au –A l0.3Ga0.7N / AlN / GaN heterostructures in the temperature range of 295– 415 K. The experimental results show that all forward bias semilogarithmic I-V curves for the different temperatures have a nearly common cross point at a certain bias voltage, even with finite series resistance. At this cross point, the sample current is temperature independent. We also found that the values of series resistance Rs that were obtained from Cheung’s method are strongly dependent on temperature and the values abnormally increased with increasing temperature. Moreover, the ideality factor n, zero-bias barrier height B0 obtained from I-V curves, and Rs were found to be strongly temperature dependent and while B0 increases, n decreases with increasing temperature. Such behavior of B0 and n is attributed to Schottky barrier inhomogeneities by assuming a Gaussian distribution GD of the barrier heights BHs at the metal/semiconductor interface. We attempted to draw a B0 versus q /2 kT plot in order to obtain � +

SiO2 planarization technology with biasing and electron cyclotron resonance plasma deposition for submicron interconnections

Abstract: Bias electron cyclotron resonance (ECR) plasma deposition technology is proposed to planarize submicron interconnections with a high aspect ratio (height/space of interconnection) in which rf bias is applied to the substrate of the ECR plasma deposition system. The technology has the following advantages. First, the concave region of the narrow gap between submicron interconnections with a high aspect ratio above 1.0 can be planarized and formed at the same insulator thickness as that of the convex region. This is due to high directionality of ECR plasma particles. Second, both deposition and etching rates can be controlled by adjusting the gas flow rates as well as the rf and microwave power. Third, an rf bias can be applied from the initial stage of the planarization process. This is because of sputter‐etching with O2 ions without Ar, thus enabling a shorter planarization time. Using the bias‐ECR plasma deposition technology, the 0.5 μm line/space Al (0.5 μm thickness) interconnection surface can be perfectly planarized.