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Biasing

About: Biasing is a research topic. Over the lifetime, 29422 publications have been published within this topic receiving 301035 citations.


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Journal ArticleDOI
TL;DR: In this paper, the GaN epitaxial layers were grown on Si substrates by means of metalorganic chemical-vapor deposition and the response time of 4.8 ms was determined by measurements of photocurrent versus modulation frequency.
Abstract: GaN metal–semiconductor–metal photoconductive detectors have been fabricated on Si(111) substrates. The GaN epitaxial layers were grown on Si substrates by means of metalorganic chemical-vapor deposition. These detectors exhibited a sharp cutoff at the wavelength of 363 nm and a high responsivity at a wavelength from 360 to 250 nm. A maximum responsivity of 6.9 A/W was achieved at 357 nm with a 5 V bias. The relationship between the responsivity and the bias voltage was measured. The responsivity saturated when the bias voltage reached 5 V. The response time of 4.8 ms was determined by the measurements of photocurrent versus modulation frequency.

71 citations

Patent
Robert A. Blauschild1
16 Jun 1997
TL;DR: In this paper, the bias voltage of an FET is adjusted to a desired variation characteristic by applying a gate bias voltage having a predetermined variation in value with respect to temperature, which results in the drain current of the FET being substantially constant in terms of temperature.
Abstract: Mobility in an FET is used as a time standard to develop a resistance (or a transconductance or a current) reference which may be fully integrated and which is temperature stable to an arbitrary desired accuracy (or which varies with temperature in a desired fashion). The large temperature dependence of mobility is compensated (or adjusted to a desired variation characteristic) by applying a gate bias voltage having a predetermined variation in value with respect to temperature. In one embodiment the bias voltage of the FET is given a temperature dependence which results in the drain current of the FET being substantially constant with respect to temperature. This current is then used to charge or discharge a capacitor, yielding a precise R-C product which may be implemented fully in integrated form.

71 citations

Journal ArticleDOI
TL;DR: In this paper, the authors show that the presence of a buried oxide layer in silicon causes enhanced self-heating in Silicon-On-Insulator (SOI) n-channel MOSFETs.
Abstract: The presence of a buried oxide layer in silicon causes enhanced self-heating in Silicon-On-Insulator (SOI) n-channel MOSFETs The self-heating becomes more pronounced as device dimensions are reduced into the submicron regime because of increased electric field density and reduced silicon volume available for heat removal Two-dimensional numerical simulations are used to show that self-heating manifests itself in the form of degraded drive current due to mobility reduction and premature breakdown The heat flow equation was consistently solved with the classical semiconductor equations to study the effect of power dissipation on carrier transport The simulated temperature increases in the channel region are shown to be in close agreement with recently measured data Numerical simulation results also demonstrated accelerated turn-on of the parasitic bipolar transistor due to self-heating Simulation results were used to identify scaling constraints caused by the parasitic bipolar transistor turn-on effect in SOI CMOS ULSI For a quarter-micron n-channel SOI MOSFET, results suggest a maximum power supply of 18 V In the deep submicron regime, SOI devices exhibited a negative differential resistance due to increased self-heating with drain bias voltage Detailed comparison with bulk devices suggested significant reduction in the drain-source avalanche breakdown voltage due to increased carrier injection at the source-body junction >

71 citations

Journal ArticleDOI
TL;DR: In this paper, the frequency and voltage dependence of the dielectric constant (e'), e'' loss (e''), loss tangent (tan δ), electric modulus (M' and M'') and ac electrical conductivity (σac) of Al/TiO2/p-Si (MOS) structures has been investigated using the capacitance-voltage (C−V) and conductance-voltages (G/ω-V) characteristics.
Abstract: In this study, the frequency and voltage dependence of the dielectric constant (e'), dielectric loss (e''), loss tangent (tan δ), electric modulus (M' and M'') and ac electrical conductivity (σac) of Al/TiO2/p-Si (MOS) structures has been investigated using the capacitance–voltage (C–V) and conductance–voltage (G/ω–V) characteristics. A TiO2 thin film was deposited on the p-type Si substrate by using the sol–gel dip coating method. These C–V and G/ω–V characteristics were measured by applying a small ac signal of 50 mV amplitude in the frequency range 5 kHz–1 MHz, while the dc bias voltage was swept from (−4 V) to (4 V) at room temperature. Experimental results show that e', e'', tan δ and σac are strongly frequency and voltage dependent. Accordingly, it has been found that as the frequency increases, e' and e'' values decrease while an increase is observed in σac and the electric modulus. The results can be concluded to imply that the interfacial polarization can more easily occur at low frequencies consequently contributing to the deviation of dielectric properties and ac electrical conductivity of Al/TiO2/p-Si/p+ (MOS) structures.

71 citations

Journal ArticleDOI
TL;DR: This work has reported the occurrence of reversible resistance switching effects in simple metal nanogap junctions, which exhibits a non-volatile resistance hysteresis when the bias voltage is reduced very rapidly from a high level to around 0 V, and when the biases are reduced slowly.
Abstract: In recent years, several researchers have reported the occurrence of reversible resistance switching effects in simple metal nanogap junctions. A large negative resistance is observed in the I–V characteristics of such a junction when high-bias voltages are applied. This phenomenon is characteristic behaviour on the nanometre scale; it only occurs for gap widths slightly under 13 nm. Furthermore, such a junction exhibits a non-volatile resistance hysteresis when the bias voltage is reduced very rapidly from a high level to around 0 V, and when the bias voltage is reduced slowly. This non-volatile resistance change occurs as a result of changes in the gap width between the metal electrodes, brought about by the applied bias voltage.

71 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023256
2022488
2021480
2020923
2019946
2018977