Biasing

About: Biasing is a research topic. Over the lifetime, 29422 publications have been published within this topic receiving 301035 citations.

Method of depositing film by PEALD using negative bias

Abstract: A method of forming a film on a substrate by PEALD includes deposition cycles, each including (i) feeding a precursor in a pulse to a reaction space to adsorb a precursor on a surface of a substrate; (ii) after step (i), applying RF power to a second electrode to generate in the reaction space a plasma to which the precursor-adsorbed surface is exposed, thereby forming a sublayer on the surface; and (iii) applying a bias voltage to the second electrode while applying RF power in step (ii), which bias voltage is negative with reference to a potential on a surface of the first electrode, wherein the cycle is repeated to deposit multiple sublayers until a film constituted by the sublayers has a desired thickness.

Physically Unclonable Function Implemented Through Threshold Voltage Comparison

Abstract: Electronic devices and methods are disclosed to provide and to test a physically unclonable function (PUF) based on relative threshold voltages of one or more pairs of transistors. In a particular embodiment, an electronic device is operable to generate a response to a challenge. The electronic device includes a plurality of transistors, with each of the plurality of transistors having a threshold voltage substantially equal to an intended threshold voltage. The electronic device includes a challenge input configured to receive the challenge. The challenge input includes one or more bits that are used to individually select each of a pair of transistors of the plurality of transistors. The electronic device also includes a comparator to receive an output voltage from each of the pair of transistors and to generate a response indicating which of the pair of transistors has the higher output voltage. The output voltage of each of the pair of transistors varies based on the threshold voltage of each of the pair of transistors.

Bias-switchable negative and positive photoconductivity in 2D FePS3 ultraviolet photodetectors

Abstract: Metal-phosphorus-trichalcogenides (MPTs), represented by NiPS3, FePS3, etc, are newly developed 2D wide-bandgap semiconductors and have been proposed as excellent candidates for ultraviolet (UV) optoelectronics. In spite of having superior advantages for solar-blind UV photodetectors, including those free of surface trap states, being highly compatible with versatile integrations as well as having an appropriate band gap, to date relevant study is rare. In this work, the photoresponse characteristic of UV detectors based on few-layer FePS3 has been comprehensively investigated. The responsivity of the photodetector, which is observed to be determined by bias gate voltage, may achieve as high as 171.6 mAW-1 under the illumination of 254 nm weak light, which is comparable to most commercial UV detectors. Notably, both negative and positive photoconductivities exist in the FePS3 photodetectors and can be controllably switched with bias voltage. The eminent and novel photoresponse property paves the way for the further development and practical use of 2D MPTs in high-performance UV photodetections.

Performance of a new ohmic contact for GaAs particle detectors

Abstract: In recent papers, we have investigated, within the context of the RD-8 experiment, the behaviour as a function of bias of the active region of particle detectors made by Alenia SpA on semi-insulating liquid encapsulated Czochralski gallium arsenide: the active region width depends linearly on the bias voltage. The diodes were found to break down as soon as the field reached the back ohmic contact. This suggested that the ohmic contact was injecting holes into the diode, therefore we have decided to develop a new, non-injecting, non-alloyed ohmic contact. This new contact allows us to go far beyond, five times, the voltage bias necessary to have a fully active detector. The higher voltage reached by the detectors helps us improve the charge collection efficiency, up to more than 95% for alphas and more than 90% for beta (mips) particles and X-rays, giving a more stable operation of the detectors. For the first time we can explore the characteristics of a GaAs detector beyond the voltage needed for it to be completely active.

A 60 GOPS/W, −1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology

Abstract: Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human–Computer Interfaces. A promising approach to achieve up to one order of magnitude of improvement in energy efficiency over current generation of integrated circuits is near-threshold computing. However, frequency degradation due to aggressive voltage scaling may not be acceptable across all performance-constrained applications. Thread-level parallelism over multiple cores can be used to overcome the performance degradation at low voltage. Moreover, enabling the processors to operate on-demand and over a wide supply voltage and body bias ranges allows to achieve the best possible energy efficiency while satisfying a large spectrum of computational demands. In this work we present the first ever implementation of a 4-core cluster fabricated using conventional-well 28 nm UTBB FD-SOI technology. The multi-core architecture we present in this work is able to operate on a wide range of supply voltages starting from 0.44 V to 1.2 V. In addition, the architecture allows a wide range of body bias to be applied from −1.8 V to 0.9 V. The peak energy efficiency 60 GOPS/W is achieved at 0.5 V supply voltage and 0.5 V forward body bias. Thanks to the extended body bias range of conventional-well FD-SOI technology, high energy efficiency can be guaranteed for a wide range of process and environmental conditions. We demonstrate the ability to compensate for up to 99.7% of chips for process variation with only ±0.2 V of body biasing, and compensate temperature variation in the range −40 °C to 120 °C exploiting −1.1 V to 0.8 V body biasing. When compared to leading-edge near-threshold RISC processors optimized for extremely low power applications, the multi-core architecture we propose has 144× more performance at comparable energy efficiency levels. Even when compared to other low-power processors with comparable performance, including those implemented in 28 nm technology, our platform provides 1.4× to 3.7× better energy efficiency.