Biasing

About: Biasing is a research topic. Over the lifetime, 29422 publications have been published within this topic receiving 301035 citations.

Current recycling and SFQ signal transfer in large scale RSFQ circuits

Abstract: The practical implementation of RSFQ technology in most digital electronics application areas requires much more complexity than the presently developed circuits. There are two important issues in building large-scale RSFQ circuits: 1) the recycling of the bias currents and 2) the transfer of SFQ pulses between circuits located far apart. RSFQ circuits are well known to operate with DC current bias. Even though the DC current biasing is more forgiving than the problematic AC biasing, it can still be a big concern when the circuit size becomes large. Dramatic reduction of the total bias current can be achieved by biasing several RSFQ circuits in series, where each circuit is positioned on a separate ground plane. In this work, we have used magnetically coupled Josephson transmission lines as inputs and outputs of an isolated shift register to show the feasibility of using the concept of serial biasing in current recycling. The circuit was simulated, fabricated with Nb technology, and tested at a temperature of 4.2 K. Test results show that SFQ pulses were transferred into the shift register built on a separate ground plane, clocked through it, and sent out back to the circuit on the original ground plane. We also studied on how to transfer SFQ pulses over an extended length, an important issue in building large RSFQ circuits. We have designed the circuits to test our microstrip line and multichip module approaches. We designed, optimized, fabricated and tested the circuits. Test results show that SFQ pulses can be successfully transmitted over an extensive distance in a chip and between chips.

Arc Evaporation of Ti–Al–Ta–N Coatings: The Effect of Bias Voltage and Ta on High-temperature Tribological Properties

Abstract: Recently, titanium aluminium tantalum nitride (Ti–Al–Ta–N) coatings have been shown to exhibit beneficial properties for cutting applications. However, the reason for the improved behaviour of these coatings in comparison to unalloyed Ti–Al–N is not yet clear. Here, we report on the tribological mechanisms present in the temperature range between 25 and 900 °C for this coating system, and in particular on the effect of the bias voltage during deposition on the tribological response. Based on these results, we provide an explanation for the improved performance of Ta-alloyed coatings. An industrial-scale cathodic arc evaporation facility was used to deposit the coatings from powder metallurgically produced Ti40Al60 and Ti38Al57Ta5 targets at bias voltages ranging from −40 to −160 V. X-ray diffraction experiments displayed a change with increasing bias voltage from a dual-phase structure containing cubic and hexagonal phases to a single-phase cubic structure. Investigations of the wear behaviour at various temperatures showed different controlling effects in the respective temperature ranges. The results of dry sliding tests at room temperature were independent of bias voltage and Ta-alloying, where the atmosphere, i.e. moisture and oxygen, were the most important parameters during the test. At 500 °C, bias and droplet-generated surface roughness were identified to determine the tribological behaviour. At 700 and 900 °C, wear depended on the coating’s resistance to oxidation, which was also influenced by the bias voltage. In conclusion, Ta-alloyed coatings show a significantly higher resistance to oxidation than unalloyed Ti–Al–N which could be an important reason for the improved performance in cutting operations.

32-bit Configurable bias current generator with sub-off-current capability

Abstract: A fully configurable bias current reference is described. The output of the current reference is a gate voltage which produces a desired current. For each daisy-chained bias, 32 bits of configuration are divided into 22 bits of bias current, 6 bits of active-mirror buffer current, and 4 bits of other configuration. Configuration of each bias allows specifying the type of transistor (nfet or pfet), whether the bias is enabled or weakly pulled to the rail, whether the bias is for a cascode, and whether the bias transistor uses a shifted source (SS) voltage for sub-off-current biasing. In addition, the current reference integrates a pair of voltage regulators that generate stable voltage sources near the rails, suitable for the SS current references. Measurements from fabricated current references built in 180 nm CMOS show that the reference achieves at least 110 dB (22-bit) dynamic range and reaches 160dB when power-rail gate biasing is included. Generated bias currents reach at least 30x smaller current than the transistor off-current. Each current reference occupies an area of 620×50 urn2. The design kit schematics and layout are open-sourced.

Biasing circuit for reducing body effect in a bi-directional field effect transistor

Abstract: A field effect transistor (FET) includes a first source/drain terminal, a body terminal, and a second source/drain terminal. A bi-directional N-channel FET circuit includes a biasing circuit which couples the body terminal of the bi-directional FET to one of its first and second source/drain terminals having a lesser voltage when the first and second source/drain voltages differ by more than a threshold voltage. When the voltages differ by a threshold voltage or less, the body terminal floats at a voltage no higher than a diode drop above the lesser of the two source/drain voltages, and at a voltage no lower than a threshold voltage below the higher of the two source/drain voltages. An analogous bi-directional P-channel FET circuit is also described. Body effect is reduced because the body terminal of the FET is maintained at a voltage at or near the voltage of the effective source terminal at all times, irrespective of which of the two source/drain terminals is the effective source terminal. Consequently, the ON-resistance of the FET is reduced.