Biasing

About: Biasing is a research topic. Over the lifetime, 29422 publications have been published within this topic receiving 301035 citations.

Off-diagonal impedance in amorphous wires and application to linear magnetic sensors

Abstract: The magnetic-field behaviour of the off-diagonal impedance in Co-based amorphous wires is investigated under the condition of sinusoidal (50 MHz) and pulsed (5 ns rising time) current excitations. For comparison, the field characteristics of the diagonal impedance are measured as well. In general, when an alternating current is applied to a magnetic wire the voltage signal is generated not only across the wire but also in the coil mounted on it. These voltages are related with the diagonal and off-diagonal impedances, respectively. It is demonstrated that these impedances have a different behaviour as a function of axial magnetic field: the former is symmetrical and the latter is antisymmetrical with a near linear portion within a certain field interval. In the case of the off-diagonal response, the dc bias current eliminating circular domains is necessary. The pulsed excitation that combines both high and low frequency harmonics produces the off-diagonal voltage response without additional bias current or field. This suits ideal for a practical sensor circuit design. The principles of operation of a linear magnetic sensor based on C-MOS transistor circuit are discussed.

Detection of optical and infrared radiation with DC-biased electron-tunneling metal-barrier-metal diodes

Abstract: The voltage obtained from metal-barrier-metal (MBM) diodes by phase-sensitive detection when illuminated with optical and near-infrared radiation, modulated at 880 Hz, has been studied as a function of an applied dc bias. The detected voltage is a nonlinear function of the bias voltage for high junction impedances, and linear for low junction impedances. The nonlinearity in the junction has been shown to be consistent with electron tunneling theory.

Exchange biasing in MBE grown Fe3O4/CoO bilayers: The antiferromagnetic layer thickness dependence

Abstract: Exchange biasing has been studied for a series of [100] and [111] oriented, epitaxial Fe3O4/CoO bilayers grown by oxidic MBE. The low‐temperature exchange biasing versus CoO layer thickness is compared to theoretical models for exchange biasing. We argue that the Malozemoff random field model does not apply to this system. The exchange biasing calculated according to the Meiklejohn–Bean model, assuming nearest‐neighbor exchange coupling across a flat and magnetically uncompensated interface, differs for [100] oriented bilayers by a factor of ≂8 from the experimental value.

Single photon avalanche diode for CMOS circuits

Abstract: A single photon avalanche diode (400) is disclosed, for use in a CMOS integrated circuit, the single photon avalanche diode, SPAD, comprising: a deep n-well region (406) formed above a p-type substrate (402); an n-well region (408) formed above and in contact with the deep n-well region (406); a cathode contact (412) connected to the n-well region (408) via a heavily doped n-type implant (410); a lightly doped region (428) forming a guard ring around the n-well and deep n-well regions; a p-well region (416, 422) adjacent to the lightly doped region; and an anode contact (420, 426) connected to the p-well region via a heavily doped p-type implant (418, 424); the junction (414) between the bottom of the deep n-well region and the substrate forming a SPAD multiplication region when an appropriate bias voltage is applied between the anode and cathode and the guard ring breakdown voltage being controlled with appropriate control of the lateral doping concentration gradient such that the breakdown voltage is higher than that of the planar SPAD multiplication region.

Semiconductor integrated circuit incorporated with substrate bias control circuit

Abstract: The semiconductor IC according to this invention comprises an internal circuit including a plurality of transistors formed on a P-type or an N-type substrate (or a well) which carries out a prescribed signal processing operation during the time of operation mode, a standby detection circuit which generates a standby detection signal of active level by detecting standby mode, a bias potential generating circuit which generates a forward bias potential from the substrate (well) of the transistor to the source electrode, and a switching circuit which supplies to the substrate (well) the potential of the source electrode and the bias potential in response to the active level and the inactive level, respectively, of the standby detection signal. At the time of the operation mode, a high speed operation is secured by bringing the transistors to a low threshold voltage by receiving the supply of the bias potential, while at the time of the standby mode, the generation of malfunctions and defective data holding are prevented and the power consumption is saved by raising the threshold voltage of the transistors through a halt of supply of the bias voltage to the substrate (well).