Biasing

About: Biasing is a research topic. Over the lifetime, 29422 publications have been published within this topic receiving 301035 citations.

Modeling the dielectric response of incipient ferroelectrics

Abstract: Interest in incipient ferroelectrics has been renewed due to their promise for applications at cryogenic temperatures. The dependence of the dielectric constant of an incipient ferroelectric on temperature and the applied biasing field can be modeled correctly by solution of the Ginsburg–Devonshire equation. A set of simple and correct formulas is derived to provide simulation of the dielectric constant of an incipient ferroelectric as a function of temperature and the biasing field. As a typical representative of this, SrTiO3 is used. The inhomogeniety of the composition or/and structure of the material is quantitatively described by a specially introduced coefficient. The correlation effect is used to describe the size effect for a thin film capacitor. The boundary conditions for a ferroelectric polarization on the surface of electrodes are considered. The boundary conditions are specified for the interface between the ferroelectric and the metal or the high temperature superconductor. Comparison of the...

Adaptive power supply for avalanche photodiode

Abstract: An adaptive power supply for an avalanche photodiode (APD) is used to determine an optimum bias voltage. Without an optical signal input the adaptive power supply applies a swept voltage to the APD while monitoring the photodiode current. When breakdown occurs, the voltage is noted and the bias voltage from the adaptive power supply is set at a specified offset below the breakdown voltage. Where a source of optical digital data signal is present, it is coupled to the input of the APD via a programmable optical attenuator. The electrical digital signal output from the APD is input to a bit error rate counter, the output of which is monitored. For different optical power levels the APD bias voltage is swept by the adaptive power supply, determining a constant power level curve over which the bit error rate is virtually zero. This is repeated for a plurality of optical power levels, the resulting family of curves defining a region within the bit error rate is virtually zero. The adaptive power supply is set to a value that falls within the virtually zero bit error rate region for the expected optical power level input.

High-resolution CdTe detector and applications to imaging devices

Abstract: Using a high quality cadmium telluride (CdTe) wafer, we formed a Schottky junction and operated the detector as a diode (CdTe diode). The low leakage current of the CdTe diode allows us to apply a much higher bias voltage than was possible with the previous CdTe detectors. For a relatively thin detector of /spl sim/0.5 mm thick, the high bias voltage results in a high electric field in the device. Both the improved charge collection efficiency and the low-leakage current lead to an energy resolution of 1.1 keV FWHM at 60 keV for a 2/spl times/2 mm/sup 2/ device and 2 keV for a 10/spl times/10 mm/sup 2/ device at 5/spl deg/C without any charge-loss correction electronics. For astrophysical applications, we have developed a an initial prototype CdTe pixel detector based on the CdTe diode. The detector has 400 pixels with a pixel size of 625/spl times/625 /spl mu/m/sup 2/. Each pixel is gold-stud bonded to a fanout board and routed to a front end ASIC to measure pulse height information for each /spl gamma/-ray photon.

Ultrafast Electrically Tunable Polaritonic Metasurfaces

Abstract: Electrically tunable mid-infrared metasurfaces with nanosecond response time and broad tuning range are reported. Electrical tuning is achieved by employing strong polaritonic coupling of electromagnetic modes in metallic nanoresonators with voltage-tunable inter-subband transitions in semiconductor heterostructures, tailored for a giant quantum-confined Stark effect. Experimentally, a 220-nm-thick multi-quantum-well semiconductor layer is sandwiched between a ground plane and a metal layer patterned with plasmonic nanoresonators. Approximately 300 nm absorption peak tuning and over 30% absorption change are demonstrated at around 7 μm wavelength at normal incidence by changing the DC bias voltage from 0 to +5 V. Fast reflectivity modulation of the metasurface is shown with a response time less than ∼10 ns using bias voltage modulation between +2 V and +4 V. Since the bias affects the optical response at the individual nanoresonator level, this approach may be used to create metasurfaces for ultrafast electrical wavefront tuning and beam steering.

A highly threshold Voltage-controllable 4T FinFET with an 8.5-nm-thick Si-fin channel

Abstract: Highly threshold voltage (V/sub th/)-controllable four-terminal (4T) FinFETs with an aggressively thinned Si-fin thickness down to 8.5-nm have successfully been fabricated by using an orientation-dependent wet-etching technique, and the V/sub th/ controllability by gate biasing has systematically been confirmed. The V/sub th/ shift rate (/spl gamma/=-/spl delta/V/sub th///spl delta/V/sub g2/) dramatically increases with reducing Si-fin thickness (T/sub Si/), and the extremely high /spl gamma/=0.79 V/V is obtained at the static control gate bias mode for the 8.5-nm-thick Si-fin channel device with the 1.7-nm-thick gate oxide. By the synchronized control gate driving mode, /spl gamma/=0.46 V/V and almost ideal S-slope are achieved for the same device. These experimental results indicate that the optimum V/sub th/ tuning for the high performance and low-power consumption very large-scale integrations can be realized by a small gate bias voltage in the ultrathin Si-fin channel device and the orientation-dependent wet etching is the promising fabrication technique for the 4T FinFETs.