Showing papers on "Binary number published in 1969"

Fully iterative fast array for binary multiplication and addition

Abstract: A fast combinational circuit is described which can be used both as a multiplier and as an adder, either separately or together, giving a parallel binary output. The structure, which is completely iterative in terms of both cell logic and cell-interconnection pattern, is advantageous in large-scale integration.

Decimal Adder with Signed Digit Arithmetic

Abstract: Addition algorithm, decimal adder with signed digit arithmetic p presented here was designed to establish the following facts: the redundant representation of a decimal digit xi by a 5-bit binary number Xi=3xi leads to a logical design of extreme simplicty; it is possible to form an additional algorithm for the adder so that it can be used to transform numbers written in a conventional decinal form into a signed digit form, and vice versa.

Binary code suitable for line transmission

Abstract: A practical method is described for encoding an unrestricted binary signal into a form suitable for transmission through a binary regenerated signal path while incurring only a small increase in modulation rate

Parallel adder with distributed control to add a plurality of binary numbers

Abstract: Parallel addition of 2n-1 binary numbers is provided by storing the numbers to be added in registers such that bits of the same order are stored in the same register. The number of binary ones in a given register is determined asynchronously by shifting binary ones to one end of the register and detecting the boundary between ones and zeros. A code converter translates the detected number of ones in the given register into a binary-coded group of digital signals, such as a triad of binary-coded signals 2i.R, 2i 1.S and 2i 2.T(when n 3), where i is the order of the given register. A parallel adder adds the binary-coded signals of equal weight, such as a triadder when n 3. To add more numbers, it is simply necessary to expand the parallel adder, such as to a quadriadder when n 4. However, to add up to 27-1 numbers, a cascade arrangement is preferred in which registers and networks are expanded in an arrangement strictly analogous with that for generating triads when n 3, but with seven-bit code groups as inputs to the arrangement for adding 23-1 numbers. Thus, by adding just one unit to n, it is possible to add 2n 1-2n more numbers. The advantage increases with n, which can be increased without limit by further cascading.

High speed data transmission system utilizing nonbinary correlative techniques

Abstract: A digital data transmission system which significantly increases the transmission rate of a binary data signal over a band limited transmission channel employs correlative techniques utilizing novel precoding for converting a binary input signal into a multilevel nonbinary correlative signal which is transmitted. Each level of the transmitted signal, seven being required to achieve a factor of eight improvement in transmission rate, represents a particular combination of the original binary digits, and introduction of correlative properties at the transmitter permits the original binary data to be recovered at the receiver with standard logic circuits without reference to the past history of the waveform. The correlative properties of the transmitted signal also permit error detection without adding redundant digits at the transmitter end. The bit speed capability of the concept is not limited to eight times that of a binary system but, in general, is equal to 21og2Q per Hertz in carrier applications, where Q is equal to the number of levels of a noncorrelative nonbinary signal and is an integer greater than two.

Invariant random boolean fields

Abstract: In the set of finite binary sequences a Markov process is defined with discrete time in which each symbol of the binary sequence at time t+1 depends on the two neighboring symbols at time t. A proof is given of the existence and uniqueness of an invariant distribution, and its derivation is also given in a number of cases.

Binary Decoding Extended to Nonbinary Demodulation of Phase Shift Keying

Abstract: The required energy per information bit E_{B}/N_{o} to achieve a specified error probability with a binary error correcting code is reduced by retaining partial knowledge of digit amplitudes. Quantization to three or four levels is the minimum step of demodulator complexity beyond hard decisions. A simple extension of binary decoding is described which achieves a large part of the maximum improvement theoretically available with unquantized demodulation. The usual decoding process is modified only to the extent that two decoding operations are performed, rather than one. Also, storage is needed to compare the two resulting words to select the preferred one. With four-level demodulation, an improvement of more than one decibel is demonstrated even for small code word lengths over a nonfading phase shift keyed (PSK) coherent channel with white Gaussian noise.

Binary batch adder utilizing threshold counters

Abstract: Disclosed are counters for counting inputs in terms of a fewer number of outputs. The counters are useful in batch adders for simultaneously adding a plurality of multibit numbers. The counters include first and second binary threshold function generators which each receive a different group of inputs. The generators are in parallel with respect to the inputs and each generates a plurality of binary threshold functions. The binary threshold functions are selectively combined in first, second and third threshold combining circuits to form the counter outputs. The combining circuits are placed in parallel and each circuit logically combines one or more threshold function inputs derived from the function generators.

Asynchronous binary array divider

Abstract: This disclosure describes an asynchronous binary divider formed of an array of identical logic cells. Each cell includes a single bit binary subtractor and a selection gate. The array is connected to divisor, dividend, quotient and remainder registers. Divisor and dividend numbers are read into the divisor and dividend registers, respectively. The array of identical logic cells performs the division in parallel asynchronously and places the results of the division in the quotient and remainder registers for subsequent readout.

Binary to pulse waveform converter

Abstract: A sequence of binary data bits are transformed into a waveform consisting of a series of half-cycles of square waves of two different frequencies, the half-cycles being of alternating phase and each frequency corresponding to one of the two binary conditions. This sequence of half-cycle square waves then may be transmitted as a stream of exact half-cycles of audio tones.

Binary adder and/or subtraction using exclusive logic

Abstract: A logical operation circuit device includes a number of exclusive AND/OR logical elements derived from the logical formulas associated with a full added/subtractor The arrangement provides a full adder/subtractor for operating on one-bit binary digital signals

Fast decimal-binary conversion

Abstract: A fast combinational iterative array is described which may be used, with simple additional gating, to convert data in 8421 or 2421 binary-decimal code into binary code. The array cells, which have a simple interconnection pattern, are currently available as medium-scale integration devices.

Logic network with a low-power shift register

Abstract: A low-power binary shift register in which power consumption is a function of the binary content rather than the number of stages. Each stage includes a pair of transistors which are either in saturated conduction, representing a binary 1, or in a cutoff state of conduction, representing a binary 0. Two clockable gates are also included in each stage. One of these gates switches the transistors of an adjacent stage to conduction to store a 1 if the transistors of its stage store a 1, while the other gate resets the transistors of its stage to a cutoff state to thereby define the storing of a binary 0.

The Error Characteristics of the Binary Rate Multiplier

Abstract: The binary rate multiplier is a device which has been used for many years in hybrid computing (operational digital techniques) and control systems as a means for generating a pulse train of average frequency proportional to the value of a binary number stored in a register. In general, the pulse spacing is irregular and the number of pulses generated in a given time fluctuates above and below the number which would be produced by a perfectly regular pulse train at the same average frequency. These fluctuations constitute a short-term frequency error, the value of which is an important parameter in the design of pulse rate digital systems incorporating binary rate multipliers. This article analyzes the conditions under which maximum positive and negative errors occur, and expressions are derived from which the magnitude of such errors may be calculated.

Parameter estimation using pseudorandom binary sequences

Abstract: The instrumental-variable technique for parameter estimation is applied when the input is a pseudorandom binary sequence (p.r.b.s.). The instrumental variables proposed are time-weighted elements of a p.r.b.s., and this is shown to be equivalent to obtaining the mean value of several estimates obtained from noisy measurements. The estimates of the parameters are asymptotically unbiased.

Radix conversion circuits

Abstract: Data conversion circuits with optimized common hardware convert numbers expressed in a first radix C to other radices m1, m2, etc., with the mode of operation being controlled to establish a radix C to radix m1 conversion in one mode, a radix C to radix m2 conversion in another mode, etc., on a selective basis, as desired. In a first embodiment, numbers represented in a binary (base 2) radix C are converted to a base 10 (m1) or base 12(m2) representation. In a second embodiment, numbers stored in a ternary (base 3) radix C representation are converted to a base 12 (m1) or base 10 (m2) representation. The circuits are predicated upon recognition of the fact that a number represented in a first radix can be converted readily to a second radix using shared hardware if the following equation is satisfied: m =Cn (PC + 1) m =CnX In the equation, m represents the divisor, that is, the base or radix to which the existing data is to be converted. C represents the radix or base of the original data. The factors P and n are positive integers used in the equation for convenience. If any set of values for P and n satisfy the equation for m in the specified base C of the dividend, then division by m can be implemented. The determination that the equation is satisfied for any original source data is first made in order to develop the circuits appropriate for converting the source data to other radices.

A Study of the Structure of Rapidly Rotating Close-Binary Systems

Abstract: A polytropic theory for investigating the structure of rapidly rotating close binary systems is developed on the basis of the works of Chandrasekhar (1933) and Monaghan and Roxburgh (1965). In this method each component is divided into an inner and outer region; it is shown that the inner region is the interior of the Emden sphere. Solutions for the interior and exterior potentials and densities are found, consistent to the seventh power of the ratio of the undistorted radius (a) to the separation (R); i.e.(a/R)7.The surface, surface gravity and potential are found. These results are used to discuss the critical configurations and contact equipotentials, and the existence of semi-detached and contact binary systems. The theory is compared to previous work, in particular the case of rotation alone and the Roche model.

Fet binary to one out of n decoder

Abstract: A circuit is described in which eight field effect transistors are interconnected to translate a two-bit binary word into oneout-of-four logic. The description further includes an explanation of how to apply the principles taught herein to build circuits for translating any ''''N''''-bit binary coded word into one out of 2N logic.

Decimal to binary conversion

Abstract: Successive 4-bit numbers representing successive decimal digits in decreasing order of significance are inserted into one portion of a register means. During each period between the insertion of one 4-bit number and the next, the bits are shifted stage-tostage and an adder serially adds the bit stored in one stage of said one portion of the register means to bits stored in two other stages of the register means. The selection of stages is such as to cause to be added to each new decimal digit, the two multiple and the eight multiple of a binary number representing all previously applied decimal digits. The successive sum bits produced by the adder are returned, in serial fashion, to the register means and represent a new binary number equal to the digits inserted, to that point, of the decimal number.

Phase converter with a reflected binary code output

Abstract: A phase converter is disclosed in which a selected number of higher order even harmonics of each of two signals, whose phase difference is to be converted to digital form, are generated. Corresponding even harmonics are mixed in separated mixers and filtered to provide an output in binary digital form. The fundamental harmonics of the two signal are combined to provide two outputs in binary digital form which together with the outputs of the other harmonics represent an output in the form of a reflected binary code.

Bcd to binary converter

Abstract: Where Nbcd is the binary coded decimal number, i is the maximum decimal order of the decimal number, and b is the binary coded decimal signal and has a logic value of 1 or 0. A high-speed binary coded decimal to binary converter having a plurality of full adders and half adders arranged to add the binary coded decimal signals to provide the binary signals in accordance with the following equation:

Digital arithmetic system for computation of square roots and squares employing a rate multiplier

Abstract: Described is a digital system, employing only two binary counters and a rate multiplier, capable of extracting the square root of an unknown variable or raising the unknown variable to the power of two. The system is much simpler and less expensive than prior art systems for achieving the same function.

Control system for a machine tool

Abstract: A machine tool control system is described which includes an adder arranged to add a first binary number, representative of a sensed dimension of a workpiece, to the bit by ones complement of a second binary number, representative of a desired dimension of the workpiece. Whenever the first binary number is greater than the second binary number, at least one of the sum outputs from the adder represents a zero logic condition, and a one logic condition exists on the carry output from the adder. Whenever the first and second binary numbers are equal, the sum outputs from the adder results in all ones and the carry output is in a zero logic condition. The sum output connections from the adder are coupled to four inputs of a five-input AND circuit. The fifth input is connected to a lead providing a logical one output upon the match of the next preceding digit as determined by a preceding comparator. The carry output connection from the adder is coupled to one input of a two-input AND circuit which has its second input connected to a lead providing a match logical one output from the preceding comparator. The output from the fiveinput AND circuit provides a retract signal for the movement of a machine tool element, such as a grinding wheel, relative to a workpiece. The output from the two-input AND circuit provides a control signal for signalling an advance of the machine tool element relative to a workpiece.

Representation of binary systems by families of binary relations

Abstract: It is proved that an arbitrary binary multiplicative system can be represented by a family of binary relations, using the so called generalized multiplication of relations Transformations of such representations and existence of a ‘universal’ representation are studied

Unambiguous digital processing of dual binary three-valued codes

Abstract: This invention contemplates means for digital resolution of three-valued code ambiguities resulting from the combination in parallel of two signed binary sequences (O -, 1 +, or vice versa) offset from one another by one-half code element, their combination relating elements of the second to adjacent elements of the first and resulting in three-valued code elements+, 0 or , the first three-valued code sequence element being ambiguous due to the signed binary sequences'' offset, said first element three-valued ambiguity being resolved by combining the signed value of the final element in the second signed binary sequence with the signed value of the first element in the first binary sequence; and, the last three-valued code sequence also being ambiguous due to the signed binary sequences'' offset, said last element three-valued ambiguity being resolved by repeating the signed value of the final element in the second signed binary sequence as an appended final signed value in the resulting three-valued sequence, said appended final three-valued sequence element being called the LINK; the inherent nonredundant error detection feature of this class of three-valued codes being preserved; the LINK providing information and means for unambiguous decoding of the said three-valued sequence, zero value elements of which are ambiguous and all-zero value threevalued sequences being totally ambiguous in decode to the two component signed binary sequences, the said decode ambiguities being resolved by circuit means to place the signed value of the three-valued LINK element into the last element of the second signed binary sequence, in turn the last element of the second signed binary sequence being combined with the next to the last three-valued sequence thus defining the signed value of the last element in the first signed binary sequence, circuit operations being carried on sequentially to finally produce the first elements of the signed binary sequences and a FLAG signal element useful in clocking the signed bnary binary into their related circuit registers.

Computational analysis of the random components induced by a binary equivalence relation

Abstract: The problem of partitioning into classes by means of a binary equivalence relation is investigated. Several algorithms for determining the number of components in the graph associated with a particular set of elements are constructed and compared. When the classification process operates on independently drawn samples of n distinct elements from a population, the expected number of components is shown to be obtainable recursively for a class of problems called separable; in all cases, estimates are available to reach any desired level of accuracy. Clustering models in Euclidean space are analyzed in detail and asymptotic formulas obtained to complement experiments. Conjectures concerning the general behavior of the expected number of components are presented also. Finally, several computational tools of general interest are improved significantly.

Arrangement for converting a binary number into a decimal number in a computer

Abstract: A binary-to-decimal converter comprises a plurality of cascaded adding means having order numbers n 1,2,3... wherein the binary number is initially received by the adding means with order number 1 and proceeds serially through the adding means. The first adding means adding 1 to the binary number and each subsequent adding means multiplying the result from the previous adding means by Further means return the result from the last adding means to the input of the first adding means until such result is zero. For each such iteration certain bit positions of the result are stored, such bit positions representing the succession decimal digits of the conversion.