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Showing papers on "Binary number published in 1970"


Journal ArticleDOI
TL;DR: A parallel multiplier designed using the carry-save scheme and constructed from 74 series integrated circuits is described, which multiplies 10-bit by 12-bit binary numbers with a worst- case multiplication time of 520 ns.
Abstract: A number of schemes for implementing a fast multiplier are presented and compared on the basis of speed, complexity, and cost. A parallel multiplier designed using the carry-save scheme and constructed from 74 series integrated circuits is described. This multiplier multiplies 10-bit by 12-bit binary numbers with a worst- case multiplication time of 520 ns. The cost of the integrated circuits was less than $ 500.

139 citations


Journal ArticleDOI
TL;DR: Applications to digital filtering computations are considered which illustrate that log-antilog multiplication is not simpler than an array multiplier for computing single products, but is useful for parallel digital filter banks and multiplicative digital filters.
Abstract: An approximate method for rapid multiplication or division with relatively simple digital circuitry is described. The algorithm consists of computing approximate binary logarithms, adding or subtracting the logarithms, and computing the approximate anti- logarithm of the resultant. Using a criteria of minimum mean square error, coefficients for the approximations are developed. An error analysis is given for three cases in which the algorithm is useful. Finally, applications to digital filtering computations are considered which illustrate that log-antilog multiplication is not simpler than an array multiplier for computing single products, but is useful for parallel digital filter banks and multiplicative digital filters.

137 citations


Journal ArticleDOI
TL;DR: The generation of independent random binary digits with an extremely small difference between the probabilities for 0 and 1 is discussed and shown to be practicable by means of a scale-of-2 counter counting randomly timed input pulses for a fixed time interval.
Abstract: The generation of independent random binary digits with an extremely small difference between the probabilities for 0 and 1 is discussed and shown to be practicable by means of a scale-of-2 counter counting randomly timed input pulses for a fixed time interval. It is shown that such digits can be used to form other random numbers with appreciable advantages of speed and accuracy, in comparison with the direct generation of similar numbers by means of a scale-of-n counter, where n>4. The use of ternary digits, generated with a scale-of-3 counter, would give a slight further theoretical advantage, but would be less convenient to implement than binary.

60 citations


Journal ArticleDOI
TL;DR: An iterative array for nonrestoring division uses a logic cell which has been proposed for an array for binary square-root extraction and is fully iterative in terms of cell logic and in the interconnection pattern between the cells.
Abstract: An iterative array for nonrestoring division is described. It uses a logic cell which has been proposed for an array for binary square-root extraction. The array for binary division is fully iterative in terms of cell logic and in the interconnection pattern between the cells.

30 citations


Journal ArticleDOI
TL;DR: The process of converting arbitrary real numbers into a floating-point format is formalized as a mapping of the reals into a specified subset of real numbers, the set of n significant digit base β floating- point numbers, and properties of conversion mappings are determined.
Abstract: The process of converting arbitrary real numbers into a floating-point format is formalized as a mapping of the reals into a specified subset of real numbers. The structure of this subset, the set of n significant digit base β floating-point numbers, is analyzed and properties of conversion mappings are determined. For a restricted conversion mapping of the n significant digit base δ numbers to the m significant-digit base δ numbers, the one-to-one, onto, and order- preserving properties of the mapping are summarized. Multiple conversions consisting of a composition of individual conversion mappings are investigated and some results of the invariant points of such compound conversions are presented. The hardware and software implications of these results with regard to establishing goals and standards for floating-point formats and conversion procedures are considered.

30 citations


Journal ArticleDOI
TL;DR: An array containing controlled adder-subtractor cells is described and an alternative array is presented which uses 2's complement arithmetic to perform subtractions.
Abstract: An array containing controlled adder-subtractor cells is described. An alternative array is presented which uses 2's complement arithmetic to perform subtractions. The operating speeds of the arrays are considered in connection with the logical design of the cells. An application of cellular arrays in generating the Napierian logarithm of a binary number is outlined.

24 citations


Journal ArticleDOI
TL;DR: This paper relates previous analyses of the binary SRT division to the theory of multiplier recoding, and it is shown that the recoding is afunction of the divisor, and the method for determining the characteristic Boolean function of the recoded is presented.
Abstract: This paper relates previous analyses of the binary SRT division to the theory of multiplier recoding. Since each binary quotient digit has three possible values, the quotient resulting from the SRT division is in recoded form; in this paper it is shown that the recoding is a function of the divisor, and the method for determining the characteristic Boolean function of the recoding is presented. The relationship between the division and the recoding is established by scaling the division in such a way that the scaled "divisor" becomes a constant. Higher radix results are also discussed.

20 citations


Journal ArticleDOI
TL;DR: A general design procedure for formulating the conversion registers as a present-state/next-state counter problem is given, along with several examples of the application of the one-step algorithm, which includes low cost, faster operation, and hardware modularity.
Abstract: Over ten years ago, Couleur described a serial binary/ decimal conversion algorithm, the BIDEC method. This was a two-step process involving a shift followed by a parallel modification of the data being converted. With the integrated-circuit J-K flip-flop, the implementation of this two-step process requires an excessive amount of control logic. This paper presents a one-step conversion algorithm that is suitable for binary-to-decimal and decimal-to-binary conversion. A general design procedure for formulating the conversion registers as a present-state/next-state counter problem is given, along with several examples of the application of the one-step algorithm. The advantages of this new algorithm include low cost, faster operation, and hardware modularity.

20 citations


Journal ArticleDOI
TL;DR: This paper shows how to optimize simultaneously over all possible choices of coset leaders for the detection scheme.
Abstract: Crimmins et al. [1] showed how to minimize mean-square error over all 1 - 1 mappings of digital data into binary group code elements when the a priori probability of the data is uniform. This paper shows how to optimize simultaneously over all possible choices of coset leaders for the detection scheme.

17 citations


Journal ArticleDOI
TL;DR: The proposed organization of a residue number system using n pairwise relatively prime moduli is found to improve the operation times for sign detection and overflow detection operations, while rendering multiplication to be a difficult operation.
Abstract: We consider a residue number system using n pairwise relatively prime moduli m 1 ,⋯,m n to represent any integer X in the range M/ 2≤X>M/2, when M = ∏mi. The moduli m i are chosen to be of the 2-1 type, in order that the residue arithmetic can be implemented by means of binary registers and binary logic. Further, for each residue number X, a magnitude index P x is maintained for all arithmetic operations. We investigate the properties of such a system and derive the addition, subtraction, multiplication, sign determination, and overflow detection algorithms. The proposed organization is found to improve the operation times for sign detection and overflow detection operations, while rendering multiplication to be a difficult operation.

17 citations


Journal ArticleDOI
TL;DR: A multiplex technique is described that can be used in photoelectric observations of dispersed spectra and an application at the solar eclipse (Mexico, 1970) is described.
Abstract: A multiplex technique is described that can be used in photoelectric observations of dispersed spectra. The encoding pattern is a set of pseudo-random binary sequences. The data processing requires a minimum possible number of operations. A special purpose device could give the spectral intensity distribution on-line. An application at the solar eclipse (Mexico, 1970) is described.

Patent
31 Dec 1970
TL;DR: In this article, the correlation between a transmitted sequence of digital numbers with the same numbers locally generated is measured by counting the number of hits which occur during a transmission of a total number of digital number (hits plus misses).
Abstract: A circuit for providing a measure of the fidelity of a communication transmission (figure of merit) by determining the correlation between a transmitted sequence of digital numbers with the same numbers locally generated. The number of correlated digital numbers is counted (hits) which occur during a transmission of a total number of digital numbers (hits plus misses). The number of hits in binary form is converted to the number of hits minus misses by shifting the digit in the most significant bit position to that of the least significant bit. This binary number is a close approximation of the figure of merit (disregarding the decimal point).

Journal ArticleDOI

Patent
28 Jul 1970
TL;DR: In this paper, an asynchronous device for counting the number of consecutive leading zeros, starting with the most significant digit, in a digital word is presented. But this device is not suitable for counting in fixed-point digital computers.
Abstract: This invention relates to an asynchronous device for counting the number of consecutive leading zeros, starting with the most significant digit, in a digital word. Such a device is useful in generating shift and exponent modification information in floating-point digital computers and in generating information for overflow detection in fixed-point digital computers. The device comprises a plurality of gates, one for each digit in the binary word, which are so interconnected that they pass information only when the particular digit signal applied thereto is a zero and only when all of the higher order (more significant) digits are also zeros. The outputs of the gates are applied to a plurality of adders where they are counted, and the total is presented at the output. The total can than be used to control a shifter for properly locating the binary point in the word, and to provide information for exponent modification, or to provide information for overflow detection.

Patent
06 Jul 1970
TL;DR: In this article, a multiphase encoder translates the bits of a non-return-to-zero digital signal into a three-frequency self-clocking having a data transition at the center of a binary ONE bit and a transition between successive binary ZERO bits.
Abstract: A multiphase encoder translates the bits of a Non-Return-to-Zero digital signal into a three frequency self-clocking having a data transition at the center of a binary ONE bit and a data transition between successive binary ZERO bits.


Journal ArticleDOI
TL;DR: A design for a binary adder-checker system which employs residue codes to detect any error resulting from a single fixed fault is presented.
Abstract: A design for a binary adder-checker system which employs residue codes to detect any error resulting from a single fixed fault is presented. In an adder, special functional relationships must exist, regardless of the particular logical realization. Consequently, for adders with either serial or parallel carry propagation, the worst possible error can be described precisely. Certain residue codes may then be used to detect that error by means of a simple checking algorithm with a minimnum of extra circuitry.

Patent
16 Jul 1970
TL;DR: A method and apparatus for data encoding and decoding in which a quaternary logic system is used for processing binary data is described in this article, where two data channels are used to provide four combinations of data, two of which represent binary values, logic "'''0'''' and logic '''1,''''' a third of which provides a guard band between bits of information and the fourth of which is a special character.
Abstract: A method and apparatus for data encoding and decoding in which a quaternary logic system is used for processing binary data. Two data channels are used to provide four combinations of data, two of which represent binary values, logic ''''0'''' and logic ''''1,'''' a third of which provides a guard band between bits of information and the fourth of which is a special character.

Patent
Frank A Zurla1
16 Apr 1970
TL;DR: In this paper, a high-speed microprogrammed processor is used to select the time duration of each basic machine cycle as the current control word is being executed, and the result is processed a second time in the binary adder to correct the result if necessary.
Abstract: The present improvement makes use of a high-speed microprogrammed processor which has means for selecting the time duration of each basic machine cycle as the current control word is being executed. During a decimal add operation, the decimal operands are processed as normal binary values and the result is processed a second time in the binary adder to correct the result if necessary. The two ALU (arithmetic and logic unit) steps are executed during one machine cycle which is slightly longer than a normal binary add (or prior art decimal add) cycle; however, this arrangement improves overall processor performance by removing a stage of delay from the ALU input for all ALU operations. In addition, decimal error checking savings are effected.

Journal ArticleDOI
TL;DR: In this article, a method of calculating the critical properties of binary hydrocarbon systems is presented which is based upon the rigorous thermodynamic equations for the critical point of a binary mixture, by using these equations together with an equation of state, a completely analytical procedure was developed with the aid of a digital computer.
Abstract: A method of calculating the critical properties of binary hydrocarbon systems is presented which is based upon the rigorous thermodynamic equations for the critical point of a binary mixture. By using these equations together with an equation of state, a completely analytical procedure was developed with the aid of a digital computer. The Redlich-Kwong and the Dieterici equations of state were chosen for study. The Redlich-Kwong equation was found superior for predicting critical pressures and temperatures by this method, although the Dieterici equation was better for critical volumes. The two interaction parameters arising from the equation of state were calculated from combining rules or from available experimental critical data on binary systems. To facilitate the latter approach, a mathematical optimization routine was used to find the best values of the interaction parameters for twenty-one binary hydrocarbon systems for which critical data were experimentally determined. The optimum values of the interaction parameters were correlated as functions of the ratio of molecular weights of the components. These correlations enable one to predict quite precisely the critical properties of the binary systems from the pure component data alone.

Journal ArticleDOI
TL;DR: A shrinking algorithm that works in parallel has been implemented on an 8×8 matrix on which binary patterns are digitised and used for normalising and counting patterns preventing merging when some objects containing others are present.
Abstract: A shrinking algorithm that works in parallel has been implemented on an 8×8 matrix on which binary patterns are digitised. This shrinking technique has been used for normalising and counting patterns preventing merging when some objects containing others are present.


Journal ArticleDOI
TL;DR: A design of a cross correlator is proposed which takes advantage of the simplicity in handling random binary signals to be used for the identification of nonlinear systems.
Abstract: A class of random binary signals have statistical properties which can be considered a first approximation to the Gaussian ones. These binary signals are suggested to be used for the identification of nonlinear systems. For that a design of a cross correlator is proposed which takes advantage of the simplicity in handling these signals.

Journal ArticleDOI
TL;DR: An effective method is given for constructing bounds for unknowns in representations of numbers by binary forms based on bounds of linear forms in the logarithms of algebraic numbers in various metrics.
Abstract: An effective method is given for constructing bounds for unknowns in representations of numbers by binary forms. The arguments are based on bounds of linear forms in the logarithms of algebraic numbers in various metrics (archimedian and non-archimedian).

Journal ArticleDOI
TL;DR: This work has succeeded in deriving a theorem for the ternary case (radix = 3) somewhat along the lines of the Peterson's theorem as follows.
Abstract: Except for some elementary definitions and fundamentals, the theory of AN code is by and large the theory of binary (radix = 2) arithmetic codes. It is often believed (erroneously) that this theory can be readily generalized to any nonbinary radix. The very fundamental theorems of Brown and Peterson on single-error-correcting codes have been derived for the binary case only. Whereas a generalized version of Brown's theorem can be stated and proved relatively easily (as shown here), the one for Peterson's theorem is not forthcoming. However, we have succeeded in deriving a theorem for the ternary case (radix = 3) somewhat along the lines of the Peterson's theorem as follows. Let M_3 (A, d) denote the smallest positive integer such that the arithmetic weight of A M_3 (A, d) in ternary representation is less than d . Also ley A = 2p for some odd prime p . Then 3 is a primitive element of GF(p) if and only if \begin{equation} M_3 (A, 3)=(3^{(p-1)/2} + 1)/A. \end{equation}

Patent
12 May 1970
TL;DR: A decimal-to-binary encoder was proposed in this paper, which includes two sets of permanent magnets and associated reed switches, each switch having a binary value, and an individual coded shunt plate containing variously shaped apertures is interposed between each set of magnets and its switches for permitting patterns of magnetic fields through the plate.
Abstract: A decimal to binary encoder for generating both decimal point position and round-off information for instructing calculator memory register or printout logic. The encoder includes two sets of permanent magnets and associated reed switches, each switch having a binary value. An individual coded shunt plate containing variously shaped apertures is interposed between each set of magnets and its switches for permitting patterns of magnetic fields through the plate, thereby closing different combinations of switches depending on the position of each plate with respect to its set of magnets and switches. The positioning of the decimal point location shunt plate also positions the round-off shunt plate so that round-off is always made with respect to the decimal point location. The round-off setting is effected by positioning the round-off set of magnets and switches in relation to the previously positioned round-off shunt plate.


Patent
28 Apr 1970
TL;DR: In this article, a tens recognition system was used to obtain the tens digit corresponding to the value of the binary word, which was then converted to binary form and displayed as a tens digit and is also subtracted from portions of the original five-bit binary word.
Abstract: A five-bit binary word is displayed as an alpha-numeric tens digit and an alpha-numeric units digit on adjacent seven-segment display tubes. The five-bit binary word is processed by a tens recognition system in order to obtain the tens digit corresponding to the value of the binary word. The tens digit is then converted to binary form and is displayed as a tens digit and is also subtracted from portions of the original five-bit binary word in order to obtain the value of the units digit in binary form. This value is then displayed as the units segment.

Patent
18 Nov 1970
TL;DR: In this article, a binary-to-binary-coded-decimal (BCD) converter is described, where the binary number is held in a first register and is shifted bit by bit into a second register as the number is converted.
Abstract: A binary-to-binary-coded-decimal (BCD) converter wherein the binary number is held in a first register and is shifted bit by bit into a second register as the number is converted. A plurality of logic circuits connected to the second register examine four-bit segments of the second register and control an adder which increments the number when the binary values of the examined four-bit segments are equal to predetermined quantities.

Journal ArticleDOI
TL;DR: This correspondence describes a way to compare binary with ternary logic and shows how the former can be compared with other types of logic.
Abstract: This correspondence describes a way to compare binary with ternary logic.