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Showing papers on "Binary number published in 1975"


Journal ArticleDOI
TL;DR: Various topological properties of digital binary pictures are derived, using two newly introduced local features named connectivity number and coefficient of curvature, using a new approach employing arithmetical techniques.

153 citations


Journal ArticleDOI
TL;DR: Algorithms for reconstruction of a two-dimensional binary pattern Z from its row- projection vector A and column-projection vector B have been developed by Chang and characterization questions of binary patterns and their projections are posed.
Abstract: Algorithms for reconstruction of a two-dimensional binary pattern Z from its row-projection vector A and column-projection vector B have been developed by Chang. The projection set (A,B) is said to be unique, nonunique, or inconsistent if it determines one binary pattern, more than one binary pattern, or no binary pattern. A binary patern Z is said to be ambiguous if there exists another pattern with the same projections, otherwise it is unambiguous. Two characterization questions of binary patterns and their projections are posed. First, given Z what is the necessary and sufficient condition for Z to be ambiguous, or unambiguous? Second, given (A,B), what is the necessary and sufficient condition for (A,B) to be unique, nonunique, or inconsistent? These two combinational questions are discussed and efficient algorithms to answer them are derived from some ideas of Ryser.

39 citations


Patent
17 Jan 1975
TL;DR: A parallel shifter as discussed by the authors consists of a plurality of AND gates arranged in a skewed configuration to simulate the partial products of a multiplication of the binary number to be shifted with a second binary number representing 2 N where N is the number of shift steps.
Abstract: A parallel shifter consists of a plurality of AND gates arranged in a skewed configuration to simulate the partial products of a multiplication of the binary number to be shifted with a second binary number representing 2 N where N is the number of shift steps. Pseudo multiplication may be accomplished merely by ORing the outputs of the AND gates of any given binary weight since only one partial product of that weight will be non-zero. Left or right shift is accomplished by selection of the most significant or least significant half of the product. Rotation is accomplished by merging of the two halves.

34 citations


Journal ArticleDOI
TL;DR: In this article, it is shown how the test for positive definiteness of an arbitrary binary form can be expressed in terms of an inner algorithm, and an example is used to illustrate the computational aspects of the procedure.
Abstract: It is shown how the test for positive definiteness of an arbitrary binary form can be expressed in terms of an inner algorithm. An example is used to illustrate the computational aspects of the procedure.

27 citations


Patent
27 Jun 1975
TL;DR: In this article, a programmable memory is used to store values corresponding to sine and cosine functions for a vector or phasor, and the amplitude of the vector is determined by the use of the function P = Im(sinθ) + Re(cos) where Im and Re are the quadrature components.
Abstract: A circuit for transforming to polar coordinate form first and second binary number electrical signals representative of rectangular coordinates or quadrature components for a vector or phasor. The circuit utilizes a programmable memory in which values corresponding to the sine and cosine functions are stored. In the preferred form, the circuit utilizes binary number electrical signals of 10 bits. The most significant bit of the polar coordinate angle is found directly from the binary number representing one of the quadrature components, whereas the next two most significant bits of the angle are found using logic circuitry in association with the binary number signals representing the quadrature components. The remaining bits of the angle are found by use of a successive approximation technique in conjunction with the values stored in the memory. Once the angle is determined, the amplitude of the vector or phasor is determined by the use of the function P = Im(sinθ) + Re(cosθ) where Im and Re are the quadrature components. The coordinate transforming circuit is particularly useful in digital transmission and receiving systems in connection with modulation of transmitted signals and demodulation of received signals.

20 citations


Journal ArticleDOI
TL;DR: A theoretical basis for codes with radix r > 2 which are capable of correcting arbitrary arithmetic errors in any Radix r digit is presented, along with practical considerations regarding their applicability.
Abstract: This paper considers codes with radix r > 2 which are capable of correcting arbitrary arithmetic errors in any radix r digit. If each radix r digit represents a byte of b binary digits (e.g., r = 2b), these codes correct any combination of errors occurring in the b binary digits of any single byte. A theoretical basis for these codes is presented, along with practical considerations regarding their applicability.

19 citations


Patent
25 Sep 1975
TL;DR: In this paper, the immediate or current interval between pulse excursions, referred to as CT, and the immediately prior time between pulses, referred as PT, are compared and a series of logic steps are made with the following results: (1) when CT and PT are within a predetermined range of each other, then the current bit has the same binary sense as the prior bit; (2) when PT exceeds CT by at least a predetermined amount, then CT is a binary ONE; and (3) if CT exceeds PT by a certain amount, the current binary bit is
Abstract: The picture frames recorded on video magnetic tape are identified by serial binary numbers magnetically recorded along an edge of the tape. The sequential ONE and ZERO bits that form each number occur during equal successive intervals when the tape is transported at constant speed and these bits are detected as electrical pulse excursions, one pulse excursion during the interval for a ONE and no excursions during an interval for a ZERO. The pulses are detected even while the tape is not transported at constant speed as when it is accelerating or decelerating and so, the intervals for the successive binary bits may change rapidly and when that occurs, it is difficult to determine whether the successive excursions define a binary ZERO interval or the first half of a binary ONE interval and so, it cannot be determined whether they represent a binary ONE or a binary ZERO. In the present invention, the immediate or current interval between pulse excursions, herein called CT, and the immediately prior time between pulse excursions, referred to herein as PT, are compared and a series of logic steps are made with the following results: (1) when CT and PT are within a predetermined range of each other, then the current bit has the same binary sense as the prior bit; (2) when PT exceeds CT by at least a predetermined amount, then the current bit is a binary ONE; and (3) when CT exceeds PT by a predetermined amount, then the current binary bit is a ZERO.

19 citations


Patent
David N. Gooding1, Everett M. Shimp1
17 Jun 1975
TL;DR: In this article, a digital arithmetic unit for adding and subtracting multidigit binary coded decimal numbers having a zoned format is presented, which is done by means of a parallel binary adder of a type suitable for handling pure binary numbers and having no special provisions for accommodating zoned decimal numbers.
Abstract: A digital arithmetic unit for adding and subtracting multidigit binary coded decimal numbers having a zoned format. Such adding and subtracting is done by means of a parallel binary adder of a type suitable for handling pure binary numbers and having no special provisions for accommodating zoned decimal numbers. The two multidigit zoned decimal numbers to be added or subtracted at any given moment are supplied to the two input sides of such binary adder by way of input modifier circuits which precondition the zone and sign fields in such numbers to enable the proper propagation of digit carries across such zone and sign fields during the performance of the addition inside the binary adder. The resulting binary bit sequence appearing at the output side of the binary adder is passed to an output modifier or corrector which causes the bits in the zone and sign field positions therein to assume the proper zone and sign code values. The input modifier circuitry for one of the numbers also includes circuitry for increasing the value of each digit in such number by a factor of six for enabling the proper generation of digit carries inside the binary adder. The output corrector includes circuitry for reducing, when necessary, the value of one or more of the output digits by a factor of six to offset the increase in the input digits. Subtraction is accomplished by complementing one of the numbers before it is supplied to the binary adder. Sign handling circuitry detects the polarities or signs of the two input numbers as well as the status of an external add/subtract command and processes these three factors to develop a control signal for controlling the use of the complementing action for enabling the number appearing at the output of the output corrector to be in true magnitude form whenever possible. The input modifier circuitry, the output corrector and the sign handling circuitry are constructed so that packed binary coded decimal numbers and pure binary numbers can also be handled by the arithmetic unit.

17 citations


Journal ArticleDOI
TL;DR: Circuits for performing arithmetic operations using base –2 representations are considered, study of the counting process leads to a negative binary up-down counter and new simple methods for positive-negative base conversions.
Abstract: Circuits for performing arithmetic operations using base –2 representations are considered. Study of the counting process leads to a negative binary up-down counter and new simple methods for positive-negative base conversions. The advantage of employing carry-borrow rather than carry-only during additions is pointed out. Certain special features of negation, arithmetic shift, multiplication, and division in base –2 are described.

17 citations


Patent
Toshimasa Kihara1
20 Mar 1975
TL;DR: In this paper, an incrementer circuit, where a "1" is added to binary input information of n digits to provide binary output information, characterized in that output information of the lowest digit is produced as inverted input information by an inverter circuit, and that output of each of the second-lowest to nth digits is produced by passing either input information from a particular digit or its inverted signal from an inverted signal through a corresponding one of transfer gate transistor paths, which are controlled by the information of digits lower than the particular digit.
Abstract: An incrementer circuit, wherein a "1" is added to binary input information of n digits to provide binary output information, characterized in that output information of the lowest digit is produced as inverted input information by an inverter circuit, and that output information of each of the second-lowest to nth digits is produced by passing either input information of the particular digit or its inverted signal from an inverter circuit through a corresponding one of transfer gate transistor paths, which are controlled by the information of the digits lower than the particular digit.

16 citations


Journal ArticleDOI
Gideon Frieder1, C. Luk
TL;DR: A representation for binary coded ternary (BCT) numbers is proposed and a distinction is made between basic algorithms, i.e., those which are independent of the type of the arithmetic, and thoseWhich are dependent upon it.
Abstract: A representation for binary coded ternary (BCT) numbers is proposed. This representation is then used for the introduction of algorithms for ternary addition and subtraction on binary hardware. In the algorithm introduced, distinction is made between basic algorithms, i.e., those which are independent of the type of the arithmetic, and those which are dependent upon it. Some suggestions as to the significance of this approach for nonternary arithmetic are presented.

Patent
Miller Homer W1
09 May 1975
TL;DR: In this article, an arithmetic logic array employing soft-saturating current mode logic gates operates on pure binary data or binary coded decimal data, and two 4-bit data inputs are received along with a 5-bit Op code, a carry input, and decimal arithmetic operation signals.
Abstract: An arithmetic logic array employing soft-saturating current mode logic gates operates on pure binary data or binary coded decimal data. Two 4-bit data inputs are received along with a 5-bit Op code, a carry input, and decimal arithmetic operation signals. In response to a decimal add (DA) one data input is increased by a count of six, and in response to either a BCD add or a BCD subtract (DA + DS) the output is decreased by a count of six if no carry output is generated.

Patent
Miller Homer W1
26 Mar 1975
TL;DR: In this article, a carry look-ahead array is used with up to six 4-bit binary arithmetic/logic arrays to expeditiously process 24 bit binary data, and seven carry lookahead arrays may be used for processing 144 bit data.
Abstract: A carry look-ahead array is used with up to six 4 bit binary arithmetic/logic arrays to expeditiously process 24 bit binary data. Advantageously, two carry look-ahead arrays may be used in combination for processing 44 bit data, and seven carry lookahead arrays may be used for processing 144 bit data. Soft saturating current mode circuit elements are employed which provide an output voltage swing between 0 volt and -0.5 volt.

Patent
Miller Homer W1
26 Mar 1975
TL;DR: In this article, an arithmetic logic array employing soft-saturating current mode logic gates receives two binary input signals and a binary operation mode signal and includes a half-adder and logic function portion for generating half-sums of the input signals, a carry look-ahead component for generating carrys in response to half-sum and carry generate inputs, and a portion for combining the halfsums and carrys to produce a resultant binary output.
Abstract: An arithmetic logic array employing soft-saturating current mode logic gates receives two binary input signals and a binary operation mode signal and includes a half-adder and logic function portion for generating half-sums of the input signals and carry generate signals, a carry look-ahead portion for generating carrys in response to half-sum and carry generate inputs, and a portion for combining the half-sums and carrys to produce a resultant binary output. Another portion may be included to produce carry generate and propagate signals useful with a separate look-ahead carry array.

Journal ArticleDOI
TL;DR: In this article, a new method for treating the electronic structure of binary alloys is presented based on the study of a finite size cluster connected at its edges to a Bethe-lattice of the same coordination number.

Journal ArticleDOI
TL;DR: With this method the error correction capability of the decoder is extended for large signal-to-noise ratios (SNR's) and different decoding algorithms are used when the number of orthogonal parity-check sums are even and odd, respectively.
Abstract: A method of using reliability information in one-step majority-logic decoders is presented. The idea is, basically, that the received binary digits are corrected in an order such that the least reliable digit is first corrected. With this method the error correction capability of the decoder is extended for large signal-to-noise ratios (SNR's). Different decoding algorithms are used when the number of orthogonal parity-check sums are even and odd, respectively. Computer simulations are presented for some short codes with binary antipodal signals on the additive white Gaussian noise channel.

Patent
16 Sep 1975
TL;DR: In this article, the same binary adder can provide the binary sum of the operands supplied to it, or the binary coded decimal sum of bcd operands without the need to recycle the sum of operands through the adder.
Abstract: Disclosed is an integrated circuit microprocessor with a parallel binary adder whose output can be corrected on-the-fly to provide decimal results. The correction is by logical gating which operates selectively and on-the-fly, that is, while the sum from the output of the binary adder is being transferred to an accumulator. As a result, the same binary adder can provide the binary sum of the operands supplied to it, or the binary coded decimal sum of bcd operands, or the binary coded decimal difference of bcd operands, in a single operating cycle and without the need to recycle the sum of the operands through the adder. This single cycle correction significantly speeds up the operation of the invented microprocessor as compared to known prior art microprocessors which recycle the adder output when a binary coded decimal sum or difference is required.

Patent
22 Sep 1975
TL;DR: In this article, a logic circuit for converting a triple state input to a binary output having a single line ternary input and a two line binary output is presented, and means are provided for driving both of these output transistors, such that three different binary output states result from the input states of low, high and open (or floating) respectively.
Abstract: A logic circuit for converting a triple state input to a binary output having a single line ternary input and a two line binary output. A pair of output transistors provide the two line binary output, and means are provided for driving both of these output transistors, such that three different binary output states result from the ternary input states of low, high and open (or floating), respectively.

Patent
02 Jul 1975
TL;DR: In this article, a binary counting system for a display actuator for an electronic clock is presented. But it is not suitable for use in an actuator with an external display.
Abstract: A binary counting system applicable for a variety of applications, but particularly suitable for use in a display actuator for an electronic clock, includes circuit means for counting through a sequence of more than ten states which represent a sequence of consecutive decimal numbers in a manner that all the binary logic states representing decimal numbers with a common unit's digit are part of an exclusive sub-cube of a minterm map common only to that unit's digit.

Patent
Heinz-Juergen Lohmann1
15 May 1975
TL;DR: A comparator circuit for two multi-digit binary codes, particularly binary numbers, in which a series circuit is formed by n number of majority decision elements connected in series, each of which has three inputs, is described in this paper.
Abstract: A comparator circuit for two multi-digit binary codes, particularly binary numbers, in which a series circuit is formed by n number of majority decision elements connected in series, each of which has three inputs, the characteristic information of the first binary number being supplied to a respective input in a negated manner, and the information of the second binary number to another respective input in a non-negated manner. In one embodiment, an evaluation circuit for a qualitative comparison result utilizes a test pulse in conjunction with the binary numbers, which pulse is supplied to the last element of the series connected elements. Depending on the embodiment, the qualitative comparision result may be read out either in response to a test pulse or continuously.

Patent
27 Jun 1975
TL;DR: An apparatus for maintaining a constant surface speed of a rotating work piece being cut by a moving cutting tool, comprising means for storing a first signal representing a binary coded decimal number which is further representative of the product of the desired constant surface speeds of the work piece and a conversion constant, was described in this article.
Abstract: An apparatus for maintaining a constant surface speed of a rotating work piece being cut by a moving cutting tool, comprising means for storing a first signal representing a binary coded decimal number which is further representative of the product of the desired constant surface speed of the work piece and a conversion constant. The apparatus is further comprised of a shift register for receiving a second signal representing a binary coded decimal number which is further representative of the current radial dimension of the work piece being cut, and means for storing a third signal representing a binary coded decimal number initially representative of an assumed rotational speed of the work piece. Means for arithmetically multiplying the binary coded number representative of the radial dimension of the work piece by the binary coded number representative of the assumed rotational speed of the work piece is also provided, along with a means for storing a fourth signal representing a binary coded decimal number which is further representative of the product of the radial dimension of the work piece and the rotational speed of the work piece. Further provided is a means for comparing the first signal representing the binary coded decimal number which is representative of the product of the desired constant speed of the work piece and the conversion constant with the fourth signal representing the binary coded decimal number which is representative of the product of the radial dimension of the work piece and the assumed rotational speed of the work piece, and for providing a fifth signal to adjust the binary coded decimal number representative of the assumed rotational speed of the work piece until the compared first and fourth signals are made approximately equal, at which time a sixth signal representing a final binary coded decimal number representative of the required rotational speed of the work piece is generated to control the speed of a motor that drives a spindle which holds the work piece.

Patent
12 Nov 1975
TL;DR: In this article, a binary coded input signal is converted to binary coded decimal signal having N decades by employing N four-bit shift registers with a right shift-parallel load mode control input terminal.
Abstract: A binary coded input signal is converted to a binary coded decimal signal having N decades by employing N four bit shift registers. The bits of the input signal are sequentially supplied, in order, to the least significant position of the register for the units decade, with the most significant bit of the input signal being applied to the units register first. Each of the registers includes a right shift-parallel load mode control input terminal. In response to the sum of the values stored in each register and the binary value 0011 being less than the binary value 1000, the mode control input terminal is activated to shift the register contents one bit to the right. In response to the sum being greater than 1000, the mode control input terminal is activated to load the sum into the register. A binary one is loaded into the least significant bit position of the register for the adjacent higher decade in response to the sum being greater than 1000.

Patent
15 Dec 1975
TL;DR: In this paper, three modular arrays are connected together to form a binary quotient by successive approximations, or a second way to form binary product, most significant bit first, by successive approximation.
Abstract: Three modular arrays structured from a common module are connected together a first way to form a binary quotient by successive approximations, or a second way to form a binary product. Any one of the three modular arrays may be used to add or subtract two binary numbers. To divide, one array is utilized to effectively form the reciprocal of the binary divisor, most significant bit first, by successive approximation. Control circuitry, including a carry detector, dictates the formation of the shift and add sequence that effectively represents the reciprocal of the divisor by controlling the positioning of the divisor before each addition step so that the product is a series of binary ones. The add and shift sequence utilized to generate the series of binary ones, as it is evolving, is also being utilized to manipulate the dividend, thereby forming the quotient, most significant bit first. In effect, the dividend is being multiplied by the reciprocal of the divisor so as to form an approximate product of the dividend and reciprocal of the divisor, most significant bit first. This product is actually an increasingly precise approximation of the quotient of the dividend and divisor. The binary product of two numbers is formed, most significant bit first, by manipulating the multiplicand according to an add and shift sequence determined by use of the multiplier.


Patent
01 Aug 1975
TL;DR: In this paper, an error-checking scheme was proposed for use in digital data processing systems, e.g., computers, in which binary data is variously transmitted and/or stored and in which the data source or destination is designated by a binary address.
Abstract: The error-checking scheme disclosed herein is adapted for use in digital data processing systems, e.g. computers, in which binary data is variously transmitted and/or stored and in which the data source or destination is designated by a binary address. In a preferred embodiment, the data is divided into two fields and a respective parity bit is generated corresponding to each data field. Each data parity bit is then combined with a parity bit corresponding to the binary address to yield a respective combinational parity bit. Each of the resultant combinational parity bits is then sourced with the respective data field. Accordingly, a system sub-component receiving the sourced data with the combinational parity bits can detect any type of single error occurring in either the address or the data.

Patent
Miller Homer W1
26 Mar 1975
TL;DR: In this paper, a magnitude comparison circuit was proposed to compare two X-bit binary numbers and two Y-bit numbers when a mode control signal is in a first condition and generates outputs indicating the relative magnitudes of the X-bits binary numbers.
Abstract: A magnitude comparison circuit compares two X-bit binary numbers and two Y-bit binary numbers when a mode control signal is in a first condition and generates outputs indicating the relative magnitudes of the X-bit binary numbers and the Y-bit binary numbers. The magnitude comparison circuit compares two Z-bit binary numbers when the mode control signal is in a second condition and generates an output indicating the relative magnitude of the Z-bit binary numbers, where Z equals the sum of X and Y.

Journal ArticleDOI
TL;DR: Examination of Tinkler's use of a binary coefficient of association in the factor analysis of networks suggests that the method is unsatisfactory, but an alternative method is shown to be redundant, but to be a useful aid to the interpretation of results obtained by established methods.
Abstract: Examination of Tinkler's use of a binary coefficient of association in the factor analysis of networks suggests that the method is unsatisfactory. An alternative method is shown to be redundant, but to be a useful aid to the interpretation of results obtained by established methods. THE object of this note is to comment upon a result derived by Tinkler (I972, pp. 35-9) in the application of principal components analysis (P.C.A.) to binary matrices representing transport networks. Tinkler identified two methods: (i) the direct extraction of eigenfunctions of the binary matrix; (ii) the extraction of eigenfunctions of a covariance matrix using the coefficient Ca to correlate rows of the original C matrix. The derivation of Ca is given by: rr' Ca where r is the number of coincidences in the two binary rows, r' is the number of noncoincidences and n is the number of elements in each row. The results are given by Tinkler in map and table form (Table I and Figure i) to which the TABLE I The eigenvectors of the Ca matrixfor the Uganda road network, 1921

Patent
17 Jul 1975
TL;DR: In this article, an n-digit binary number is used to produce a grey-tone image having areas of different average density values which are given by a clock pattern, all the bits of the binary number being interrogated in parallel by clock patterns.
Abstract: Method and apparatus for producing a grey-tone image having areas of different average density values which are given by an n-digit binary number, all the bits of the binary number being interrogated in parallel by clock patterns. For the area to be printed an elemental area containing 2 n pulses is selected which is printed in a total cycle of 2 n - 1 clock pulses of the clock pattern. In this total cycle, at each clock pulse the drive of each pair of dots is determined in a manner such that the most-significant bit of the binary number is always used for driving while the remaining bits are used a number of times which depends upon their positional values. For this purpose, for each position of the binary number the clock pattern has a number of clock pulses which corresponds to the value of this position. The clock pulses for the individual positions are non-uniformly distributed in time, however, no clock pulses for the second and any further positions of the binary number coincide in time. Before each new print line the pattern will if required be shifted by additional clock pulses.

Patent
31 Jul 1975
TL;DR: In this paper, the presence of a non-coincidence signal is represented by binary digits and stored in a shift register, where the stored bits are translated into information indicating the location of a circuit trouble.
Abstract: Circuit testing apparatus includes a pulse oscillator providing clock pulses, a binary counter for counting the clock pulses to successively generate binary numbers, and a translator which translates the successive binary numbers into a series of test patterns. The test patterns include a series of input bit patterns used to energize the input leads of an electronic logic circuit under test and a series of output binary digits, each of which corresponds to the respective one of the input patterns. Each of the binary digits is compared with an output from the logic circuit under test. When the circuit tested is not functioning as prescribed for a particular set of input pattern, a noncoincidence signal will be produced to disable the binary counter in order to permit the test operator to register the test mode in which the trouble occurred. The binary counter may be enabled manually after registration to complete the prescribed number of tests. The presence of a noncoincidence signal is represented by binary digits and stored in a shift register. The stored bits are translated into information indicating the location of a circuit trouble, if any.