Showing papers on "Binary number published in 1977"

Digital filter structures described by distributed arithmetic

Abstract: This paper presents a new formulation of digital filters that combines the description of signal-processing and arithmetic operations. This is done by noting that multiplication is a form of convolution and therefore normal one-dimensional scalar convolution is in fact two-dimensional binary convolution. This is generalized to multidimensions and can be applied with table-look-up and transform techniques. The result is a unified description that describes a digital filter structure down to the bit level.

Correlation parameters of random binary sequences

Abstract: The asymptotic properties of aperiodic and related correlation parameters are investigated for random binary sequences. Performance parameters for synchronous and asynchronous multiple-access systems are comapared.

Single line propagation adder and method for binary addition

Abstract: A propagation line adder may be fabricated by replicating a unit circuit along a single sense propagation path. Each unit circuit corresponds to a bit of the same order of magnitude of the binary addends. Selected segments of the sense propagation path are set at a specified logical potential value and are coupled according to control signals generated within the unit circuit in response to the addend bits. A sense amplifier, coupled to each segment of the sense propagation paths, detects the state on corresponding segments of the sense propagation path. The propogation line adder implements an algorithm which produces the binary sum of two numbers by complementing the exclusive-or function of the addends according to a shifted product function. The shifted product function includes a carry-in bit as its lowest order bit.

Apparatus and method for generating a high-accuracy 7-level correlative signal

Abstract: Apparatus and method for generating a multilevel correlative signal wherein the multiple levels are digitally generated. A serial binary bit stream is first converted into two parallel binary bit streams each at half the bit rate of the original serial binary bit stream. The parallel bit streams are encoded in accordance with the relation B = C - Δ 2 C MOD 4; where B is the original waveform, C is the resultant waveform, and Δ 2 indicates two units delay or 2T seconds where 1/T is the parallel speed in digits per second. Next the binary encoded bit streams are digitally converted to a 7-level waveform; and, finally the 7-level waveform is transformed into an analog signal which retains the 7-levels and provides a band limited 7-level signal related on a one-to-one basis to the binary input signal.

Hardware realization of digital signal processing elements using the residue number system.

Abstract: In the past, hardware realization of digital signal processing elements have been based upon binary arithmetic concepts. Because of the dependence between digits in binary arithmetic operations, the hardware required to construct arithmetic elements is cumbersome. In the residue number system, arithmetic operations can be performed with complete independence between digits and a corresponding reduction in hardware complexity. In fact, using current technology, arithmetic operations can be carried out using arrays of look-up tables placed in high density ROMs. This paper discusses the application of the residue number system to realizing digital signal processing elements using such arrays and advantages and disadvantages over conventional realizations are discussed. Examples are given of recursive filter and FFT butterfly element realization.

Digital charge-coupled logic (DCCL)

Abstract: A new method of implementing digital logic functions is presented. The method is based on the use of charge-coupled devices in pipeline configurations and results in a very high functional density and an extremely low power dissipation. The authors show how various logic functions such as OR, AND, INVERT, and charge refresh are performed. The operation of a DCCL full-adder is compared with another configuration that uses cascaded dual half-adders and a carry-OR. A floating-gate is required as a binary switch in any function that requires binary inversion such as an exclusive-OR. The switching range of the floating-gate is derived as a function of the gate area, the size of the input charge packet and the extraneous capacitances. The implementation of DCCL pipeline arithmetic is discussed. An 8/spl times/8 multiplier and a 16+16 adder pipeline array now being produced are described. The power dissipation and package density of DCCL are compared with PMOS, NMOS, CMOS, and I/SUP 2/L devices in full-adder configurations and in various size arithmetic arrays. The authors conclude with a description of the present status of the technology and some projections for future uses.

Accurate estimation of the number of binary partitions

Abstract: Many authors have worked with the problem of binary partitions, but all estimates for the total number obtained so far are restricted to the exponential part only and hence very crude. The present paper is intended to give a final solution of the whole problem.

High speed binary and binary coded decimal adder

Abstract: A high speed binary and binary coded decimal adder which employs a plurality of partial adders and a carry look ahead circuit and is adapted to effect a binary coded decimal addition with only one processing of the adder. The partial adders are each composed of a half adder for generating a bit generate signal and a bit propagate signal, a binary mode carry look ahead input signal generator circuit part, a binary coded decimal mode carry look ahead input signal generator circuit part, an intermediate adder part and a full adder part. The high speed binary and binary coded decimal adder is capable of providing the result of an addition at a speed corresponding to six to seven logical stages.

Adaptive digital delta modulation for voice transmission

Abstract: An adaptive delta modulation system wherein the input analog signal is periodically sampled and a binary bit is generated for each period, the logic level of the binary bit being dependent on whether the sampled signal is greater or smaller than the approximate signal of the previous sample. Decoding apparatus converts the stream of binary bits to approximate the analog signal by periodically charging or discharging a capacitor integrator by predetermined variable steps. The charging or discharging of the integrator during each period is determined by the logic level of the binary bits, whereas the increase or decrease in step size for successive periods is determined by successive similar signal binary bits or successive dissimilar bits, respectively. The increase or decrease in step size is achieved by storing a binary step size number S in a register and adding or subtracting a fraction of the number to or from itself during each period, producing a new step size number for each period. In addition, each added fraction may be increased by a fixed least significant number to enhance step size recovery between a transmitter and a receiver. The charge on the capacitor integrator is controlled by a pulse having a width that is directly related to the value of the S number. The pulse controls the conduction time of constant current sources which are connected to the integrator to produce the analog output signal.

Amplitude generator for an electronic organ

Abstract: An amplitude curve generator for use with an electronic organ or the like to control the musical shape of an audible tone. The generator utilizes a simple binary down counter driven from a clock source to produce a sequence of decreasing binary numbers that approximate the relative amplitudes of equally spaced points along an exponential decay curve. The count condition of the least significant bits of the counter correspond to the mantissa of number expressed in binary floating point notation. The most significant bits represent the power. The bits of the mantissa are transferred to a parallel shift circuit and shifted a number of times determined by the bits of the power to convert the number in the counter to fixed point notation. The output of the shift circuit is used to control the envelope amplitude of a musical tone. The output may be subtracted from one (2's complement) to produce a set of values that correspond to an exponential attack curve rather than a decay curve. The counter can be interrupted at any point for some period of time or counted at a different frequency to tailor the wave shape to a particular attack, decay, sustain and release pattern.

Frequency indicating circuit

Abstract: The relative frequency of two signals is indicated by applying pulses indicative of the two signals to respective bistable flip-flops. The flip-flops are interconnected to produce two binary outputs each of which varies between two binary values in response to occurrence of the pulses. These binary outputs are applied to a logic circuit which produces a binary output that varies between two binary values as a function of the similarity and difference in binary values of the two flip-flop signals. The binary output of the logic circuit is applied to two further bistable flip-flops along with the pulses to control the outputs of the further flip-flops. The outputs of the further flip-flops produce respective signals which indicate the relative frequency of the two signals, and which can be used to change this relative frequency.

Apparatus for performing floating point arithmetic operations using submultiple storage

Abstract: A scientific processing unit includes apparatus for performing floating point multiplication operations with operands in binary coded form. The apparatus is constructed from standard multibit LSI microprocessor chips organized into a number of vertical slices. Each chip includes an arithmetic logic unit (ALU) and a random access memory (RAM). The ALU's are used to generate a predetermined number of submultiples of a mantissa portion of a floating point number which are stored in the chips memories. The submultiples are generated by multiplying the mantissa by predetermined factors which correspond to the values of multiplier digit positions selected during the multiplication operation. The apparatus further includes selection circuits which provide for selection of the least significant bit positions from each of a number of groups of multiplier digits during the multiplication operation. The least significant bit positions selected are used to read out the entire submultiple from the chip memories which thereafter are summed to produce a final product.

Binal data coding method

Abstract: PURPOSE:To obtain a unit which is suitable to highly concentrated magnetic recording by connecting the binary data system into the binary symbol system at a constant ratio of 2:3 and by limiting the number of 1 to minimum of one and maximum of seven within a given continuously arranged ones.

System for the digital clamping of periodic, binary encoded signals

Abstract: A binary encoded signal which is to be clamped at a desired binary value is simultaneously applied to a digital subtractor and a digital adder. The digital subtractor subtracts the difference between the desired binary value and the value of the binary encoded signal. The resulting difference is applied to a storage flip-flop circuit having a switching pulse input which receives a periodic signal. The flip-flop transfers the last received difference until the periodic signal is received causing it to transfer the latest received difference. A binary adder adds the output of the storage flip-flop to the binary encoded signal. This results in a corrected clamped binary encoded signal.

Error detection and indication system for bi-phase encoded digital data

Abstract: A real-time error detection system for bi-phase or similarly encoded digital data is disclosed. Bi-phase or similarly encoded data, which utilizes two transitions in a bit cell for either a binary "1" or a binary "0" value, and one transition in a bit cell for the other binary value inherently generates an even number of transitions of the binary value represented by the two transitions between the occurrence of the other binary value represented by one transition. Monitoring for the number of transitions of the binary value represented by two transitions provides an indication of the occurrence of an odd number of transitions. This represents an error condition. The system utilizes a logic circuit responsive to the binary "1" and binary "0" data clock retrieved from the self-clocking bi-phase encoded data. When an error condition is detected, an error indicating signal is generated.

Accurate phase-measuring system using arithmetic synthesis

Abstract: Circuit for comparing the difference in phase between two signals having like waveforms and adjusting the phase of one until the difference is zero. Two waveform generators, controlled by signals derived from the same clock source, produce the signals to be measured. One control signal is derived from the clock source by a fixed divider; the other, using an arithmetic synthesizer. The phase of the other control signal is adjusted by changing the frequency number of the arithmetic synthesizer and the phase difference is available as a binary number of n bits, where n is an integer. Precision of phase measurement in femtoseconds is possible.

Ternary Simulation of Binary Gate Networks

Abstract: The behavior of sequential gate networks can be represented mathematically by using a binary model of gates. Unfortunately, the analysis algorithms in such a model grow exponentially with the number of gates. In this paper we describe an analysis method based on a ternary model of gates, which leads to algorithms that grow linearly with the number of gates.

The Number of Roots in the Wilson Equation and Its Effect on Vapor-Liquid Equilibrium Calculations

Abstract: The Wilson equation has found extensive use in the correlation and prediction of vapor-liquid equilibrium (VLE) data. In predicting multicomponent equilibria from binary VLE data, the binary parameters first must be found. It is customary to regress all the available binary data; however, use of one binary point also has been suggested, especially if the data pair are the infinite dilution values. The purposes of this study are (1) to discuss the number of sets of binary parameters (i.e., roots) obtained either from one data point (including the use of the infinite dilution activity coefficients) or from regressing all the binary data; and (2) to explore the effect of multiple sets of parameters, wherever they exist, on the accuracy of predicted data. The best predictions of binary multicomponent data appear to result from the set of roots that are smallest in absolute value. (20 refs.)

Digital binary group call circuitry arrangement

Abstract: DIGITAL BINARY GROUP CALL CIRCUITRY ARRANGEMENT ABSTRACT Group call capability is provided as for a digital pager having a two word page address and using asynchronous detection. A group call is initiated by transmitting two identical binary words having an extra bit space between them, the binary word being word one of the individual paging address of each unit in the group to be called.

Working with Numbers

Abstract: The main objective of this chapter is to develop your ability to handle simple problems involving numbers on the computer. As in all the other chapters the emphasis is on problem solving and programming, not on mathematics.

Digital to analog converter with binary and binary coded decimal modes

Abstract: A digital to analog converter with bit circuits arranged in binary order, in which a supplemental current circuit is added to selected bit circuits to enable convenient and efficient conversion from binary to BCD operation. Supplemental BCD currents are controlled by a bias circuit which automatically increases the BCD bit circuit bias to a level at which the full-scale BCD output current is substantially equal to the full-scale binary output current.

An approximation to a two-dimensional binary process

Abstract: We further consider a two-dimensional stochastic process of binary variables previously discussed by Galbraith and Walley (1976). A method of estimating properties of the equilibrium distribution is described which considerably extends the region of probability space that can satisfactorily be explored. TWO-DIMENSIONAL PROCESS; BINARY VARIABLES; POWER METHOD FOR EIGENVECTORS; MATCHED BOUNDARY CONDITIONS

CCD Binary-to-Gray code generator

Abstract: N charge signals BN-1 . . . B0 in N channels represent an N digit binary code. The charge signal BN-1 representing the most significant binary digit is sensed to produce an output charge signal GN-1 representing the most significant Gray code digit. The N-1 remaining charge signals are processed by, in each case, adding a charge signal representing one binary digit Bj to a charge signal Bj-1 representing the binary digit of next lower significance in EXCLUSIVE OR fashion to obtain the Gray code digit Gj-1.

Developing Large Binary to BCD Conversion Structures

Abstract: Fast binary to BCD conversions consist of static implementation of a sequential algorithm and are limited to relatively small number of bits as the hardware increases rapidly with each added bit.

Comparator circuit apparatus

Abstract: The method and circuitry for detecting two different binary numbers or digital words in a register or counter using logic gates wherein bits are detected using n-1 logic gates when all the digits of each of words or numbers are at the same one of a plurality of possible logic levels. In other words, two numbers such as all logic ones as the first number and all logic zeros as the second number. Specifically, this concept is applied to checking an up-down counter output so that it is prevented from overflowing or underflowing by stopping it at either a count of all logic zeros or all logic ones.

Method and device for reduction of fibonacci p-codes to minimal form

Abstract: An arrangement for reduction of Fibonacci p-codes to minimal form, which performs, in succession, all convolutions and all devolutions of bits of the original Fibonacci p-code of a number, whereto the original combination of binary signals corresponds. The original combination of binary signals is handled during the convolution operation so that a binary signal corresponding to a 0 value of the lth digit of the original Fibonacci p-code of the number, as well as binary signals corresponding to l values of the (l - i)th and the (l - p- 1)th digit of the original Fibonacci p-code of the number, are substituted by their inverse signals. The original combination of binary signals is handled during the devolution operation so that a binary signal corresponding to a 1 value of the lth digit of the original Fibonacci p-code of the number, as well as binary signals corresponding to 0 values of the digits (l - p) through (l - 2p), inclusive, of the original Fibonacci p-code of the number, are substituted by their inverse signals.

Threshold value setting method for binary circuit

Abstract: PURPOSE:To obtain binary signal having excellent resolution, by changing the threshold level of next picture element, depending upon the binary signal of the last pattern picture element although the size of source pattern picture approaches the size of picture element.

Current mode 4-bit arithmetic logic unit with parity

Abstract: An arithmetic logic unit employing soft-saturating current mode logic gates receives as inputs two 4-bit plus parity bytes and generates a 4-bit plus parity binary output byte in accordance with the particular operational mode prescribed by a binary operation mode control signal. The unit performs sixteen binary arithmetic or sixteen Boolean logic operations on two 4-bit plus parity input fields Ai and Bi. A carry-in input CIN, a carry generate output G, and a carry propogate output P are provided so that the device can be utilized in a full carry look-ahead configuration with a separate carry look-ahead array. A special output F=O is provided for zero detection purposes. In addition to the arithmetic and logic operations, the unit performs parity checking, parity carry, and parity prediction operations on the 4-bit plus parity binary input signals, and accordingly special inputs in the form of a carry-in duplicate CID, parity of the half-sums HS, a parity of the half-parities HP, parity of the carries PC, carry error CE, and parity checking command PCK are provided. A special output E indicates a carry or half-sum parity error. A carry-out signal COUT is also provided. The device can be configured to operate on bytes having fewer than four data bits by means of a pair of configuration select signals P1 and P2.

Current mode 5-bit arithmetic logic unit with parity

Abstract: An arithmetic logic unit employing soft-saturating current mode logic gates receives as inputs two 5-bit bytes and generates a 5-bit binary output byte in accordance with the particular operational mode prescribed by a mode control signal. The unit performs sixteen binary arithmetic or sixteen Boolean logic operations on two 5-bit input fields Ai and Bi. A carry-in input CIN, a carry generate output G, and a carry propogate output P are provided so that the device can be utilized in a full carry look-ahead configuration with a separate carry look-ahead array. A special output F= is provided for zero detection purposes. In addition to the arithmetic or logic operations, the unit generates a parity of the half-sums signal HS, a parity of the half-parities signal HP, a parity of the carries signal PC, and a carry error signal CE. A carry-out signal COUT is also generated.