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Showing papers on "Binary number published in 1978"


Journal ArticleDOI
TL;DR: In this paper, the theory of binary coherent systems is generalized for multi-state components, where the system state is defined to be the state of the worst component in the best min path, or equivalently, the best components in the worst min cut.
Abstract: The theory of binary coherent systems is generalized for multi-state components. The system state is defined to be the state of the “worst” component in the “best” min path, or equivalently, the state of the “best” component in the “worst” min cut. Many of the results for the binary case can be computed for multi-state systems using the binary structure and reliability function concepts. Monotonicity results are now valid with respect to stochastic ordering of component probability vectors.

397 citations


Proceedings ArticleDOI
01 Oct 1978
TL;DR: The logical design of a redundant binary adder with two input digits and one output digit, all in the digit set {1, 0, 1}.
Abstract: This paper investigates the logical design of a redundant binary adder with two input digits and one output digit, all in the digit set {1, 0, 1} Redundant binary arithmetic structures in which all digit sets are {1, 0, 1} were first discussed by Avizienis in 1961 Borovec studied the logical design of a class of such binary adders and subtracters in 1968 At that time, a variation of the adder/subtracter was overlooked This paper studies the logical design of this variation The sum digit is still a function only of the digits in three adjacent digital positions of the operands "Coupled don't cares" are encountered, but have not introduced too much difficulty The nine distinct formats (under permutation and negation) of representing three values with two bits given by Robertson are used The simplest adder/subtracter designs from this variation are less complex than the simplest designs previously known

84 citations


Journal ArticleDOI
TL;DR: In this paper, a new shape factor for objects in a binary picture is presented, which is based on the average distance between an interior picture point and the nearest boundary point and its properties are compared to the common shape factor P 2 4πA.

83 citations



Patent
21 Apr 1978
TL;DR: In this article, a binary random noise generator for the stochastic coding of digital or analog information is proposed, which is more particularly applied to the binary coding of information with a view to calculation or transmission.
Abstract: The present invention relates to a binary random noise generator for the stochastic coding of digital or analog information, comprising a comparator having two inputs, one of which receives a reference voltage and the other a random analog noise coming from a source of noise, said comparator supplying at its output a binary signal with random transitions, said generator comprising a clock and a logic system which, on the one hand, effect the sampling of the binary signal with random transitions in synchonism with the frequency of said clock and, on the other hand, ensure the strict equiprobality of the two logic states of said binary signal with random transitions, without increasing the radius of correlation. The invention is more particularly applied to the stochastic coding of information with a view to calculation or transmission, with equidistribution of binary variable.

42 citations


Journal ArticleDOI
TL;DR: In this article, a new form of expansion of multiple-valued logical functions in generalised Fourier series in terms of the Chrestenson functions is presented, and it is shown that this expansion exhibits the property of ''disjoint spectral translation´ known in binary spectral logic design.
Abstract: A new form of expansion of multiple-valued logical functions in generalised Fourier series in terms of the Chrestenson functions is presented. It is shown that this expansion exhibits the property of `disjoint spectral translation´ known in binary spectral logic design. This allows extending the possibility of low complexity realisation to a large class of multiple-valued logical functions.

26 citations


Patent
Kenichi Miura1
17 Apr 1978
TL;DR: In this paper, a tree-type combinatorial logic circuit comprising a plurality of identical functional units which may be arranged to operate as an N-bit magnitude comparator, a carry generator for an n-bit adder, or a parity predictor for 2N-bit binary counter is presented.
Abstract: A tree-type combinatorial logic circuit comprising a plurality of identical functional units which may be arranged to operate as an N-bit magnitude comparator, a carry generator for an N-bit adder, or a parity predictor for 2N-bit binary counter. Each of the units is provided with four input terminals and two output terminals. The units are arranged to form a binary tree. Each unit has an internal logic circuit which generates outputs of G K*l =G K VE K ·g l and E K*l =E K ·E l , where "V" and "·" denote Boolean OR and AND operations, respectively. The desired functions are provided at the output terminals of the unit in the final stage of the tree. The input signals to the units in the first stage of the tree depend on the applications of the circuit. When used as a magnitude comparator, the inputs are a i ·b i 's and a i .sup.⊕ b i 's (i=0, 1,..., N-1), where a i and b i are the i-th bits of the two binary words (each N bits long) to be compared, and ⊕ represents the Boolean exclusive NOR function. When used as a carry generator, the inputs are a i ·b i 's and a i .sup.⊕ b i 's (i=0, 1, ..., N-1), where a i and b i are the i-th bits of two binary words (each N bits long) to be added and ⊕ represents the Boolean exclusive OR operation. When used as a parity predicator, the inputs are b i 's (i=N-1, N-3, N-5, ..., 1 while non-negative) and b i 's (i=N-2, N-4, ...,) while non-negative, where b i is the i-th bit of any binary number (N bits long, b o is the most significant bit) to be incremented by 1 by a binary counter.

25 citations


Patent
01 Mar 1978
TL;DR: In this article, a known good identical logic circuit is stimulated by a preselected sequence of binary test patterns and the number of transitions in logical state before achieving a final logical state as well as the final logical states for a number of points within the circuit are monitored and saved.
Abstract: The present invention relates to apparatus and method for testing logic circuit boards for complex logical faults contained therein. A known good identical logic circuit is stimulated by a preselected sequence of binary test patterns and the number of transitions in logical state before achieving a final logical state as well as the final logical state for a number of points within the circuit are monitored and saved. The logic circuit being tested is then stimulated by the same test pattern sequence and the number of transitions and final logical states achieved are compared. Failure to have identity between the known good logical circuit and the logical circuit being tested both as to number of transitions and final logical state achieved for the tested points indicates a malfunction within the board which would not be detected by mere sampling of the final output state alone.

24 citations


Patent
Robert Harold Krambeck1
15 Dec 1978
TL;DR: In this paper, the number of gates necessary in an integrated combinatorial logic circuit is reduced by designing the circuit to accept an applied binary word of given length as a plurality of word segments having numbers of bits which add up to the number included in the applied word.
Abstract: The numbers of gates necessary in an integrated combinatorial logic circuit is reduced by designing the circuit to accept an applied binary word of given length as a plurality of word segments having numbers of bits which add up to the number included in the applied word. A preprocessor responds to the word segments to generate a word characterizing the segments and to apply those words to an arithmetic logic unit designed to add binary words and to generate words having lengths of the applied words.

23 citations


Patent
Jack L. Anderson1
16 Jun 1978
TL;DR: An adder provides either binary or binary coded decimal operation under the selection of a control input as discussed by the authors, where the data inputs are a pair of four bit operands and a carry in for providing an additional capability of greater than four bits.
Abstract: An adder provides either binary or binary coded decimal operation under the selection of a control input. The data inputs are a pair of four bit operands and a carry in for providing an additional capability of greater than four bits. Outputs, in addition to the four bit result, include carry propagate and carry generate signals for the four bit group. Binary operation is conventional. For binary coded decimal operation, the adder corrects an initial binary result to the binary coded decimal format by adding six when there is a group carry generate signal present thus forming an intermediate result. This intermediate result is formed before the occurrence of the carry in from a preceding stage. In the final stage of the adder, the intermediate result is incremented to form the final four bit result if there is a carry in.

23 citations


Journal ArticleDOI
Agrawal1, Rao
TL;DR: This method shows new promises for its application to signal processing by extending the addition of two numbers in 2's complement notation-has been extended to n signed summands.
Abstract: Recent application of negabinary number systems in signal processing has evoked the question of the suitability of binary base. Many proposals for multioperand addition of unsigned binary numbers are available in the literature. Here, the addition of two numbers in 2's complement notation-has been extended to n signed summands. The time delay remains the same as that of processing n unsigned numbers. This method shows new promises for its application to signal processing.

Patent
21 Jul 1978
TL;DR: In this article, a waveform display including an opto electric display having m X electrodes and n Y electrodes arranged in a m x n element matrix is presented, where a series of m different reference binary codes are applied simultaneously one to each of the X electrodes.
Abstract: A waveform display including an opto electric display having m X electrodes and n Y electrodes arranged in a m x n element matrix. A series of m different reference binary codes are applied simultaneously one to each of the X electrodes. A waveform to be displayed is sampled and binary numbers representative of the amplitude of each sample are produced. These sample binary numbers are each converted into one of the reference binary codes for applications to the Y electrodes; the code so produced being related to both the amplitude value and the order of reference codes on the X electrodes. As a result of the simultaneous application of appropriate binary codes to each X, Y electrode, unselected X-Y intersections receive an rms voltage above a display threshold while selected X-Y intersections receive a zero voltage and collectively display the waveform. The opto-electric display may be a liquid crystal display or an electro luminescent display. The binary codes may be an ordered series of binary numbers represented by logic zeros and ones, having a period T divided into N bits where m=2 N , or period T divided into L bits and using 2 N codes out of a possible 2 L codes where L is greater than N and m=2 N . Alternatively the binary code may be a pseudo random series of zeroes and ones.

Book ChapterDOI
01 Jan 1978
TL;DR: It is a limiting and perhaps unnatural feature of conventional digital computers with classical von Neumann architectures that they are designed to perform only one calculation at a time, so instructions involving more than three numbers must proceed sequentially.
Abstract: It is a limiting and perhaps unnatural feature of conventional digital computers with classical von Neumann architectures that they are designed to perform only one calculation at a time. Systems have been developed which allow calculations to proceed at the same time as input—output operations and make possible some measure of interleaving of slow and fast operations. However, at any instant, a computer will be carrying out only one basic arithmetic operation, such as adding together two binary numbers, or subtracting them. Hardwired arithmetic units speed up these operations, but the principle remains the same: instructions involving more than three numbers (multiplier, multiplicand, and product, for example) must proceed sequentially.

Patent
Masahiko Sumi1
31 Jan 1978
TL;DR: In this paper, the data corresponding to an IC pattern to be depicted on a semiconductor pellet are compressed and stored in a memory, and a plurality of pattern data trains with the same content are compressed into a single pattern data train.
Abstract: The data corresponding to an IC pattern to be depicted on a semiconductor pellet are compressed and stored in a memory. A plurality of pattern data trains with the same content are compressed into a single pattern data train. A code representing the number of the same patterns is added to the head of the single pattern data train. The data element continuously included in the single pattern data train are encoded into another code for data compression. In this coding, the binary "0" is disposed with the same number as the result of subtraction of 2 from the quotient of n (number of the continuous data elements having the same binary value)/2. Following a series of binary "0"s, the binary "1" is disposed for partition. After the partitive binary "1", the binary "0" or "1" is disposed for indicating odd or even number of the data elements. The binary "1" or "0" is inserted between the code for representing the number of the same line patterns and the compressed single pattern data train. The binary inserted is used for correctly coupling adjacent divided patterns together.

Patent
21 Apr 1978
TL;DR: In this article, a complete binary word with a defined total bit number is subdivided into one or more partial binary words, with the respective bit numbers of the partial binary word being variable.
Abstract: A data transmission system and method in which digitalized information is transmitted via a data transmission link in complete binary words from a transmitter to a receiver. For data transmission, a complete binary word with a defined total bit number is subdivided into one or more partial binary words, with the respective bit numbers of the partial binary words being variable. The individual partial binary words are allocated all binary bit sequences that can be formed with the total number bits of the respective partial binary words, the various bit sequences being coded at respectively different positions within a partial binary word In each partial binary word exactly one binary bit sequence is transmitted from the transmitter to the receiver.

Journal ArticleDOI
TL;DR: Examples of complete enumeration of all 2 × 2 and 3 × 3 nonsingular binary matrices were produced by mapping the intermediate vectors to the matrices, which has application to the Vernam encipherment method using pseudorandom number sequences.
Abstract: Nonsingular binary matrices of order N, i.e., nonsingular over the field {0, 1}, and an initial segment of the natural numbers are placed in one-to-one correspondence. Each natural number corresponds to two intermediate vectors. These vectors are mapped into a nonsingular binary matrix. Examples of complete enumeration of all 2 × 2 and 3 × 3 nonsingular binary matrices were produced by mapping the intermediate vectors to the matrices.The mapping has application to the Vernam encipherment method using pseudorandom number sequences. A bit string formed from bytes of text of a data encryption key can be used as a representation of a natural number. This natural number is transformed to a nonsingular binary matrix. Key leverage is obtained by using the matrix as a “seed” in a shift register sequence pseudorandom number generator.

Patent
20 Apr 1978
TL;DR: In this article, a binary multiplier circuit is described where the product is expressed in coded form as soon as the linear (or non-coded) product is produced, and suitable circuitry is described which allows the coding process, just described, to take place while the linear product is in the process of being formed.
Abstract: A binary multiplier circuit wherein the product is expressed in coded form as soon as the linear (or non-coded) product is produced. When a twelve-bit binary number is multiplied by another twelve-bit binary number a twenty-four bit binary number is produced. The twenty-four bit product can be coded as an unsigned seven-bit binary number (μ-255 code) as follows. The number 33×2 11 in binary form is added to the linear product to form an augmented product. The number of leading zeroes in the augmented product is counted and the base-minus-one complement of the count is used for the three most significant bit positions of the coded product. The four next most significant bits of the augmented product, after the most significant logic 1, are used for the four least significant bit positions of the coded product. Suitable circuitry is described which allows the coding process, just described, to take place while the linear product is in the process of being formed, and produces the coded result when the final linear product is completed.

Proceedings ArticleDOI
01 Oct 1978
TL;DR: Design and analysis of finite precision rational number systems based on fixed-slash and floating-Slash representation is pursued, and the concept of adaptive variable precision in the rounding is developed.
Abstract: Design and analysis of finite precision rational number systems based on fixed-slash and floating-slash representation is pursued. Natural formats for binary fixed-slash and binary floating-slash number representation in computer words are described. Compatibility with standard integer representation is obtained. Redundancy in the' representation is shown to be minimal. Arithmetic register requirements are considered. Worst case and average case rounding errors are determined, and the concept of adaptive variable precision in the rounding is developed.

Proceedings ArticleDOI
01 Oct 1978
TL;DR: It is shown how circuits for the addition of several serial binary numbers can be obtained as a combination of parallel counters and memory cells.
Abstract: It is shown how circuits for the addition of several serial binary numbers can be obtained as a combination of parallel counters and memory cells. The various schemes belong to one of three different classes, characterized by the way in which carries, produced by parallel counters, are treated. A comparison is made between the various schemes, in terms of speed and complexity.

Patent
03 May 1978
TL;DR: In this article, a system for transmitting binary-bit words from a sending station to a receiving station where each word has the same number N of binary bits and each different word has different arrangement of binary O's was proposed.
Abstract: ERROR-REJECTING DATA TRANSMISSION SYSTEM Abstract of the Disclosure A system for transmitting binary-bit words from a sending station to a receiving station wherein each word has the same number N of binary bits and wherein each different word has the same number M of binary l's and the same number (N-M) of binary O's as every other word but in a different arrangement. The number of binary l's in each word received is counted, and if such count is not exactly equal to M, the word i s rejected as inaccurately received.

Journal ArticleDOI
TL;DR: It is shown that every finite binary sequence x has an infinite number of initial segments, x n, with K ( x n ) ⩽ n − f ( n ).
Abstract: Given any function f with σ n =0 ∞ 2 − f ( n ) divergent, it is shown that every finite binary sequence x has an infinite number of initial segments, x n , with K ( x n ) ⩽ n − f ( n ).

Patent
Donald L. Duttweiler1
04 Oct 1978
TL;DR: In this paper, it is shown how to convert μ-law digital code words including a sign bit, m characteristic bits, and n mantissa bits representing respectively the polarity, segment value, and quantizing step of a quantized analog sample into a binary floating point representation of the digital signal.
Abstract: In PCM systems, it is known to convert μ-law digital code words including a sign bit, m characteristic bits, and n mantissa bits representing respectively the polarity, segment value, and quantizing step of a quantized analog sample into a binary floating point representation thereof including a sign, exponent, and mantissa in order to process the digital signal. Known converters are of two relatively expensive types: (1) using a memory having 2 m+n locations or (2) employing a μ-law to fixed point conversion followed by fixed point to floating point conversion. To mitigate such drawbacks, the present converter (100) employs a relatively inexpensive translator (200) for translating the segment value and a prefixed quantizing step into a reference mantissa. The code word quantizing step is then added (90, 95) to the reference mantissa to provide the floating point mantissa. The exponent is equal to the segment value; and the sign bit represents the sign. The translator may be implemented, for example, by using a memory having 2 m locations or by simple combinatorial logic.

Patent
Joachim Heinzl1
18 Sep 1978
TL;DR: In this article, the redundancy of binary character sequences which describe the characters or graphic patterns is reduced such that, within the binary characters sequences, each binary character having a first binary value is assigned to a point which is to be represented and at least one interval corresponding to one element exist between two points represented by the same output component.
Abstract: In a system in which characters or graphic patterns are representd in punctiform fashion, the redundancy of binary character sequences which describe the characters or graphic patterns is reduced such that, within the binary character sequences, each binary character having a first binary value is assigned to a point which is to be represented and at least one interval corresponding to one element exist between two points represented by the same output component. Each element is split into a plurality of sub-elements and the binary character sequences which represent the characters or graphic patterns are split into sub-elements. Of the possible combinations (2 n ) of a group (n) of binary characters of the binary character sequences, code words are assigned to those combinations in which the binary character having a predetermined binary value ("1") is followed by at least one number (k-1) of binary characters having another predetermined binary value ("0"), which number is dependent upon the number (k) of sub-elements within an element. The code words are transmitted and/or stored in place of the binary character sequences and in the representation of characters or graphic patterns code words are reassigned the original binary character sequences which are then fed to the output components. A scanning device is provided to scan a format which has a graphic pattern and emits binary character sequences to an encoder which assigns the code words to the binary character sequences and/or a memory is provided in which the code words of given characters or graphic patterns are stored and a decoder is provided which is supplied with the code words from the encoder or from the memory, the decoder operating to assign the binary character sequences to the code words and emit the latter to the output components.

Patent
14 Dec 1978
TL;DR: A method and system for the implementation of binary multiplication of a number by a sum of two numbers, applicable in the computer systems, particularly in the specialized processors for numerical computations, is presented in this article.
Abstract: A method and system for the implementation of binary multiplication of a number by a sum of two numbers, applicable in the computer systems, particularly in the specialized processors for numerical computations. In the method according to the invention the multiplier, as expressed by two numbers-summands represented in a binary number system, is transformed parallelly into a positional number system with digits from -2 g-1 to +2 g-1 , where "g" is the number of binary positions of multiplier. These two numbers correspond to one partial product--summand of the result. The multiplying system contains registers of multiplier summands, a register of the multiplicand, a system converting the multiplier summands, the system preparing the partial products and the system summing them. Signals are generated by the converting system and represent digits from -2 g-1 to +2 g-1 depending upon signals coming from at most three positon groups of each of registers of multiplier summands and, possibly also, upon signals coming from their sign positions.

Patent
25 Feb 1978
TL;DR: In this paper, the authors simplify the structure of an arithmetic circuit which compares the scale of the difference absolute value of the binary number, and show that it is possible to simplify the circuit by comparing the two scales.
Abstract: PURPOSE:To simplify the structure of an arithmetic circuit which compares the scale of the difference absolute value of the binary number.

Patent
29 May 1978
TL;DR: In this article, the authors synchronously read and control the series information on a magnetic recoeding medium, by combining the information bit from three split bits consisting of two identical binary signals and one binary signal produced through inverting the former binary signal.
Abstract: PURPOSE:To surely, synchronously read and control the series information on a magnetic recoeding medium, by combining the information bit from three split bits consisting of two identical binary signals and one binary signal produced through inverting the former binary signal.

Journal ArticleDOI
01 Jun 1978
TL;DR: In this article, the construction of a decimal grouping table and its use to determine essential and nonessential prime implicants for the minimisation of an n-variable Boolean function are presented.
Abstract: The construction of a decimal grouping table and its use to determine essential and nonessential prime implicants for the minimisation of an n-variable Boolean function are presented in the paper. In existing tabular methods, e.g. the Quine-McCluskey technique, each fundamental product is represented by a row of binary 1s and 0s and the finding of a set of prime implicants necessitates the formation of successive tables of binary characters, and only after an exhaustive search in the tables can one discover any prime implicants. Dealing with binary characters is rather tedious, and searching through several tables to establish a prime implicant is time consuming. The proposed grouping table offers the convenience of using decimal minterm numbers and the advantage of using one table in the search for prime implicants. In the grouping table the decimal equivalent of function terms appear in a column and the entries to a row corresponding to a function term N are the decimal equivalent of product terms related to N by one change of variable. From these entries, only those terms which appear in the function under investigation are selected and only these need to be considered for the minimisation of the problem. Thus, unlike other tabular methods, the grouping table provides all possible combinational terms for each fundamental product term as its row terms and also the facility of at-a-glance comparison of all function terms by referring to the same table. In the paper, a method of minimising Boolean functions with the aid of grouping table is illustrated with examples.


Journal ArticleDOI
Chao-Kai Liu1, Tse Lin Wang
TL;DR: This paper first discusses the general characteristics of arithmetic errors and defines the arithmetic weight and distance in BCD systems and shows that the distance is a metric function.
Abstract: Error-correcting coding schemes devised for binary arithmetic are not in general applicable to BCD arithmetic. In this paper, we investigate the new problem of using such coding schemes in BCD systems. We first discuss the general characteristics of arithmetic errors and define the arithmetic weight and distance in BCD systems. We show that the distance is a metric function. Number theory is used to construct a class of single-error-correcting codes for BCD arithmetic. It is shown that the generator of these codes possesses a very simple form and the structure of these codes can be analytically determined.