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Showing papers on "Binary number published in 1979"


Journal ArticleDOI
TL;DR: If the sequences are the outputs of two correlated memoryless binary sources, then in some cases the rate of this information may be substantially less than the joint entropy of the two sources.
Abstract: How much separate information about two random binary sequences is needed in order to tell with small probability of error in which positions the two sequences differ? If the sequences are the outputs of two correlated memoryless binary sources, then in some cases the rate of this information may be substantially less than the joint entropy of the two sources. This result is implied by the solution of the source coding problem with two separately encoded side information sources for a special class of source distributions.

413 citations


Patent
Glen G. Langdon1, Jorma Rissanen1
28 Nov 1979
TL;DR: In this paper, a method and means of arithmetic coding of conditional binary sources permitting instantaneous decoding and minimizing the number of encoding operations per iteration is presented, where a single shift and subtract operation for each encoding cycle can be achieved if an integer valued parameter representative of a probability interval embracing each source symbol relative frequency is used for string encoding and control.
Abstract: A method and means of arithmetic coding of conditional binary sources permitting instantaneous decoding and minimizing the number of encoding operations per iteration. A single shift and subtract operation for each encoding cycle can be achieved if an integer valued parameter representative of a probability interval embracing each source symbol relative frequency is used for string encoding and control. If the symbol being encoded is the most probable, then nothing is added to the arithmetic code string. However, an internal variable is updated by replacing it with an augend amount. If the updated internal variable has a leading zero, then both it and the code string are shifted left by one position. If the symbol being encoded is the least probable, then a computed augend is added to the code string and the code string is shifted by an amount equal to the integer valued parameter.

65 citations


Journal ArticleDOI
TL;DR: A new parallel multiplier with a very simple configuration that operates in time 0(n), where n is the maximum of the lengths of the multiplier and multiplicand, both of which are fixed point, expressed in binary notation is suggested.
Abstract: Previous proposals for fast multipliers are discussed, along with a summary of the known theoretical limitations of such designs. Then, a new parallel multiplier with a very simple configuration is suggested. This multiplier operates in time 0(n), where n is the maximum of the lengths of the multiplier and multiplicand, both of which are fixed point, expressed in binary notation. It is a logical circuit consisting of 2n modules, each being only slightly more complex than a full adder; instead of three inputs and two outputs, each module has five inputs and three outputs. A logical circuit realization is given for the modules. But perhaps the most significant aspect of this design is the property that the input is required only bit-sequentially and the output is generated bit-sequentially, both at the rate of one bit per time step, least significant bit first. The advantages of such bit-sequential input and output arithmetic units are described.

53 citations


Patent
Alan Huang1
15 Jan 1979
TL;DR: In this article, a processor is constructed from a network of nodes which either store constants, perform modular arithmetic, or perform three operand binary arithmetic, and the nodes are organized in networks to perform encoding, modular computations, residue to mixed radix decoding and mixed to normal radix conversion.
Abstract: Input data is converted into its modular equivalents These equivalents are used to perform the desired computation in a modular manner Each computation is done for several moduli The various modular results are woven into a mixed radix version of the answer This version of the answer is then converted into a normal radix equivalent The processor is constructed from a network of nodes These nodes either store constants, perform modular arithmetic, or perform three operand binary arithmetic The nodes are organized in networks to perform encoding, modular computations, residue to mixed radix decoding, and mixed to normal radix conversion These operations are performed in a parallel manner The function of the nodes can be performed by table lookup The table lookups can be implemented with memories The interconnection of the nodes is structured to facilitate the construction and modification of such processors Processors can be implemented to perform many types of operations Processors which perform summation, inner products, determinate evaluation, and summation of the squares of differences are discussed

46 citations


Journal ArticleDOI
TL;DR: A ternary model is formalized which is being used to study the behavior of binary sequential gate networks and a mathematical theory is developed making precise these two models and the comparison between them.
Abstract: In this paper we formalize a ternary model which is being used to study the behavior of binary sequential gate networks. We first describe a binary model which is capable of a detailed description of network behavior, but involves a number of steps that grows exponentially in the number of gates. The complexity of the ternary model is linear in the number of gates;however, only partial information is obtained in generaL A mathematical theory is developed making precise these two models and the comparison between them. A number of examples illustrate these results. This work generalizes previously reported research.

45 citations



Patent
12 Jul 1979
TL;DR: In this article, a digital-to-analog converter is presented which converts a series of digital binary numbers into an analog signal having an amplitude proportional to the values of the binary numbers.
Abstract: A digital-to-analog converter is provided which converts a series of digital binary numbers into an analog signal having an amplitude proportional to the values of the binary numbers. The disclosed embodiment of this invention includes a segment generator having input terminals coupled to receive the most significant digits of the binary numbers to be converted, wherein the segment generator provides a first signal proportional to the values of the most significant digits of the binary numbers. A step generator is also included which receives the remaining lesser significant digits of the binary number and provides a second signal proportional to the values of these lesser significant digits of the same binary numbers. Additionally, means for combining the first and second signals is provided to form an analog signal proportional to the value of the binary number to be converted.

19 citations


01 Mar 1979
TL;DR: A complete analysis of the size of these codes is given and an ingenious construction for a class of binary codes capable of correcting a single asymmetric error is given.
Abstract: An analysis of the size of a class of binary codes capable of correcting a single asymmetric error is presented.

18 citations


Patent
22 Oct 1979
TL;DR: In this paper, a round off correction logic circuit is disclosed for inclusion within a floating point arithmetic binary digital multiplier implementing a modified Booth's algorithm for generating a final product of binary digits.
Abstract: A round off correction logic circuit is disclosed for inclusion within a floating point arithmetic binary digital multiplier implementing a modified Booth's algorithm for generating a final product of binary digits. The round off logic circuitry is connected in the multiplier for rounding its final product off to a predetermined binary digit without requiring the multiplier to generate any of the less significant binary digits to the right of the predetermined binary digit. Multiplier circuitry otherwise required to generate an unrounded final product prior to round off is eliminated without loss of accuracy in round off.

14 citations


Patent
22 Jan 1979
TL;DR: In this paper, the same binary logical value occurs in successive digits of data to be transmitted, the corresponding 3-valued logical value and a third logical value are transmitted alternately.
Abstract: Two logical values of a 3-valued code correspond to the "1" and "0" values of a binary code. When the same binary logical value occurs in successive digits of data to be transmitted, the corresponding 3-valued logical value and a third logical value are transmitted alternately. When the different binary logical value occurs in the data alternately, the corresponding 3-valued logical values are transmitted alternately.

14 citations


Journal ArticleDOI
TL;DR: In this article, a new pseudo-random generator for decimal numbers is presented, which is obtained by combining a binary and a quinary maximal-length sequence generated by feedback shift-register circuits.
Abstract: A new pseudo-random generator for decimal numbers is presented. A sequence of decimal digits is obtained by combining a binary and a quinary maximal-length sequence generated by feedback shift-register circuits. The autocorrelation sequence (ACS) of the resulting decimal sequence is calculated; it shows that linear dependencies are extremely small. Finally, guidelines are developed for choosing feedback polynomials which yield low cross correlation between various sequences of decimal digits.


Patent
18 Jul 1979
TL;DR: In this paper, a fast, parallel operating device for multiplication of binary coded numbers is presented, in which the numbers are divided into groups of n bits of directly successive significance levels, and all feasible combinations of one group of the first number and the second number are formed, for each combination a partial product being formed in a first array of partial product forming devices.
Abstract: A fast, parallel operating device for multiplying binary coded numbers. The numbers are divided into groups of n bits of directly successive significance levels. Subsequently, all feasible combinations of one group of the first number and one group of the second number are formed, for each combination a partial product being formed in a first array of partial product forming devices. A partial product is preferably formed by a logic circuit which operates non-sequentially but exclusively combinatory, and which has a logical depth of only three gates. The partial products are subsequently applied to a second array of partial sum forming devices in which they are added together with intermediate partial sums, taking into account their relative significance levels. Together with the partial product digit of lowest significance, the final row of partial sum forming devices then generates, co-operating in parallel, the complete product. A corresponding method can be used for the multiplication of binary numbers in two's complement representation. In that case the product of the parts after the decimal point must be increased by the cross products of the parts before the decimal point and the inverted values of the parts of the two numbers after the decimal point. The part of the product before the decimal point is obtained by modulo-2 addition of the parts before the decimal point of the two number in two's complement representation itself.

Patent
21 May 1979
TL;DR: In this article, a programmable digital frequency divider is proposed to convert the binary number system of the program control signal into a modified binary number number system in which the modified binary numbers are an integral multiple of the corresponding input binary number minus error compensating binary digits, wherein the number of compensating bits differs depending on the particular binary number.
Abstract: A programmable digital frequency divider comprises a programmable binary counter in receipt of an input pulse train to develop output pulses at a frequency variable as a function of a set of binary program control signals supplied in the form of normal binary number system. A binary code converter is provided to convert the binary number system of the program control signal into a modified binary number system in which the modified binary number is an integral multiple of the corresponding input binary number minus error compensating binary digits, wherein the number of compensating bits differs depending on the particular binary number. Electrical signals representing the modified binary numbers are supplied to the program input terminals of the binary counter so that the frequency of its output signal is substantially linearly variable as a function of discrete variations of the program control signal.

Patent
31 Dec 1979
TL;DR: In this paper, the authors describe a floating point processor architecture which permits multiple bit shifting over strings of binary 1's and O's in a single machine cycle, using a parallel MQ register so that two bits may be shifted per clock cycle.
Abstract: There is described a floating point processor architecture which permits multiple bit shifting over strings of binary 1's and strings of binary O's in a single machine cycle. During a multiply operation, an MQ register (arranged in parallel) which stored the multiplier, shifts the multiplier out for decoding at a rate comparable to the rate at which the partial product is shifted. This is made possible by using a parallel MQ register so that two bits may be shifted per clock cycle. This architecture permits extremely fast multiplication by using a multiple bit shift architecture while minimizing hardware requirements.

Proceedings ArticleDOI
10 Aug 1979
TL;DR: This program has included the identification of appropriate roles for residue processors, the investigation of I/O techniques, such as analog to residue and residue to radix conversion, and the study of optical implementations of residue arithmetic.
Abstract: In the 1950s, digital designers noted that residue number systems offer the attractive feature of carry-free addition, subtraction, and multiplication. This interest waned, in part because residue number systems possess a multi-state character; flip flops and other binary state devices lend themselves more naturally to binary arithmetic than to multi-state arithmetic. Optics enjoys the requisite multi-state capability: lenses can resolve many discrete positions, gratings can resolve many discrete frequencies, and so forth. This fact has motivated efforts to create a residue based optical processor, which would combine the parallel, speed of light throughput of optics with processing accuracies possible only to digital systems. Our program has included the identification of appropriate roles for residue processors, the investigation of I/O techniques, such as analog to residue and residue to radix conversion, and the study of optical implementations of residue arithmetic.© (1979) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Patent
Robert P. DePuy1
19 Mar 1979
TL;DR: In this article, an approach is described for the generation of a series of binary numbers which has a minimum value other than zero, has a major sequence of numbers in which successive numbers are separated by a first fixed increment starting from the minimum value and defining the range of the series of numbers, and has a plurality of minor sequences, each representing binary numbers of series lying between respective successive numbers of the major sequence with each number of a minor sequence being spaced from a preceding number thereof by a second fixed increment.
Abstract: Apparatus is described for the generation of a series of binary numbers which has a minimum value other than zero, has a major sequence of numbers in which successive numbers are separated by a first fixed increment starting from the minimum value and defining the range of the series of numbers, and has a plurality of minor sequences, each representing binary numbers of the series lying between respective successive numbers of the major sequence with each number of a minor sequence being spaced from a preceding number thereof by a second fixed increment.

Patent
10 Oct 1979
TL;DR: In this paper, a charge coupled device comparator decides whether each bit of the eight bit binary word is to be a logic one or a logic zero by comparing the analog input signal with reference signals selected in successive approximations by a shift register addressing the digital-to-analog converter.
Abstract: An analog-to-digital converter includes a charge coupled device comparator receiving an analog signal which is to be converted to an eight bit binary word. An eight bit charge coupled device shift register addresses an eight bit digital-to-analog converter through eight separate resettable latches to generate a reference signal which is compared in successive approximations to the analog signal by the charge coupled device comparator to generate each binary bit of the eight bit word. Sensitivity of the charge coupled device comparator is enhanced by the use of charge coupled regenerative feedback to generate each binary bit of the eight bit binary word, which is read serially into an output register. The charge coupled device comparator decides whether each bit of the eight bit binary word is to be a logic one or a logic zero by comparing the analog input signal with reference signals selected in successive approximations by a shift register addressing the digital-to-analog converter. The analog signal is compared with a progressively increasing reference signal whose magnitude is increased by successively smaller increments. Eight such successive approximations and comparisons are made in order to generate the eight bit binary word.


Patent
17 Dec 1979
TL;DR: In this article, a complementer for floating point binary numbers utilizes two digital logic decision rules selected by the value of the power of the input number, and the complemented power is set to a -1 value.
Abstract: A complementer for floating point binary numbers utilizes two digital logic decision rules selected by the value of the power of the input number. The first decision rule is selected for an input power of -1 and constructs a power and mantissa determined by the binary sequence form of the input mantissa. The second decision rule is selected for input powers less than -1 and constructs a mantissa determined by the binary sequence form of the input mantissa and the value of the power. The complemented power is set to a -1 value. The complementer is advantageously employed in digital electronic musical instruments.

Proceedings ArticleDOI
10 Aug 1979
TL;DR: An inner product processor is presented which is capable of performing 3.3 million inner products a second, where each vector consists of 100 elements each 20 bits wide, equivalent to more than 660 million 40 bit arithmetic operations a second.
Abstract: An inner product processor is presented which is capable of performing 3.3 million inner products a second, where each vector consists of 100 elements each 20 bits wide. This is equivalent to more than 660 million 40 bit arithmetic operations a second. The latency of a particular calculation is 12.3 microseconds. The processor can be constructed entirely from 1024 by 6 bit ROMs with 300 ns cycle times and latchable inputs or outputs. Modular arithmetic is used internally; the input and output are binary. The specifications of the architecture are compatible with the stricter structural requirements needed by an optical implementation.© (1979) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Patent
31 Oct 1979
TL;DR: In this article, the information transfer path lij is provided between every two processors which differ only by one bit when the numbers are given to plural units of processors and then the number is displayed in the binary number.
Abstract: PURPOSE:To secure a parallel operation such as the butterfly operation or the like by providing the information transfer path between every two processors which differ only by one bit when the numbers are given to plural units of processors and then the numbers are displayed in the binary number CONSTITUTION:Numbers 0 - 7 are given to processors 10 - 17, and these numbers are displayed in the binary number In this case, information transfer path lij is provided between every two processors which differ only by one bit For example, l01 displays the information transfer path between processor 0 and 1 In the same way, the information paths l02, l04, l13, l15; l23, l26; l37; l45, l45, l47; l57; l67 are provided In case the distance between processors (0 and 7) in which the 3 bits are all different, the operation is possible with 3 steps at most And the memory is installed to each information transfer path to be passed through

Proceedings ArticleDOI
01 Apr 1979
TL;DR: Using the Residue Number System (RNS) as a basis for the hardware construction, two different hard-ware structures are discussed for implementing NTTs over a direct sum of Galois Fields GF(m i 2), offering trade offs between speed of operation, and cost.
Abstract: Using the Residue Number System (RNS) as a basis for the hardware construction, two different hard-ware structures are discussed for implementing NTTs over a direct sum of Galois Fields GF(m i 2). The first structure uses arrays of read only memories and the second uses arrays of microprocessors; in particular, single chip microprocessors are proposed. The two techniques offer trade offs between speed of operation, and cost. Using the RNS, rather than conventional binary arithmetic, allows more flexibility in the choice of the generator, α, and consequently more flexibility in allowable transform parameters. A selection of parameters, for the two realizations, are discussed when the Galois Field of m i 2elements is a finite field of Gaussian or quadratic integers.

Journal ArticleDOI
TL;DR: A technique is proposed for implementing parallel tree-like comparator circuits with fan-in constrained gates, exhibiting logarithmic comparison time growth, based on formulating the binary comparator logic to resemble the carry look ahead logic of the binary adder.
Abstract: A technique is proposed for implementing parallel tree-like comparator circuits with fan-in constrained gates, exhibiting logarithmic comparison time growth. The technique is based on formulating the binary comparator logic to resemble the carry look ahead logic of the binary adder. The implementation is extended to modular tree comparator networks.

Patent
16 Mar 1979
TL;DR: In this article, a 2N-bit precision division processing system is presented, where the error caused during the division processing of Q 1 is used as a part of the data for performing the division of Q 2, thus effectively transferring any error evolving during the processing of X to Y.
Abstract: A division processing system performs 2N-bit precision division processing by effectively using division processing circuitry with N-bit precision. The system performs the division with 2N-bit precision as follows: ##EQU1## (n=N: the number of digit positions in selected binary numbers A, B, C and D). The above expression is approximated to the form of Q 1 +Q 2 ×2-n (Q 1 , Q 2 : binary numbers). The binary numbers Q 1 and Q 2 are respectively operated on by the division processing circuitry with N-bit precision. By effective control, the error caused during the division processing of Q 1 is used as a part of the data for performing the division processing of Q 2 , thus effectively transferring any error evolving during the processing of Q 1 to Q 2 . The function is performed in a system having only four registers, each of N-bit capacity (precision), and an operation register, multiplication circuitry, division circuitry, and a shift circuit, affording proper control of data transfer between the registers.

Patent
03 Jan 1979
TL;DR: In this paper, a binary arithmetic logic unit can be corrected to provide a binary coded decimal result by use of correction logic which is responsive to the result produced by the BALU, the type of operation being performed, and whether the binary ALU produced a carry as a result of its arithmetic operation on such operands.
Abstract: Binary coded decimal operands may be operated on by use of a binary arithmetic logic unit and the result corrected to provide a binary coded decimal result by use of correction logic which is responsive to the result produced by the binary arithmetic logic unit, the type of operation being performed and whether the binary arithmetic logic unit produced a carry as a result of its arithmetic operation on such operands.

Journal ArticleDOI
V.H. Tokmen1
TL;DR: In this article, the relationship between the spectral coefficients of the functions in a two-level decomposition and the overall function spectrum is considered, and an algebraic relationship established to give the latter from the former.

Journal ArticleDOI
TL;DR: An algorithm is described to transform sampled CT convolution kernels into "binary" kernels having values which are even powers of 2, so that multiplication in the convolution operation can be replaced by a much faster shift operation.
Abstract: An algorithm is described to transform sampled CT convolution kernels into "binary" kernels having values which are even powers of 2. Multiplication in the convolution operation can then be replaced by a much faster shift operation. A technique for further reducing the number of shift and addition operations using new computationally fast CT kernels is also given. The binary kernels are computationally faster by about 80-90% on a conventional computer. Reconstructed CT images using both conventional kernels and their transformed binary equivalents are compared.


Proceedings ArticleDOI
10 Aug 1979
TL;DR: A single-step truth-table look-up processor is devised for numerical optical processing, based on the EXCLUSIVE OR operation performed holographically on binary arrays and the NAND-OR-OR numerical optical processor.
Abstract: Two numerical optical processor configurations are presented. Both systems are based on holographic recording (to form the processing element) and holographic reconstruction (to perform the numerical processing). In these systems, pairs or arrays of pairs of binary words are presented as the input. The output may be the addition, subtraction, multiplication, division, or other operation on the pairs of words. There is one binary word answer for each pair of binary word inputs. Both numerical optical processor configurations use holographic wavefront addition and subtraction to construct Boolean logic operations. However, as contrasted with constructing arithmetic operations through multiple steps of combinational logic, a single-step truth-table look-up processor is devised. Numerical results are obtained with a single optical pass through the system. Both systems require only a limited part of the complete truth table to be recorded. The first system is based on the EXCLUSIVE OR operation performed holographically on binary arrays. The second system, more complex but more powerful, performs an operation that is equivalent to two levels of logic, a NAND and OR followed by another OR operation. For both the EXCLUSIVE OR numerical optical processor and the NAND-OR-OR numerical optical processor, the array sizes during recording and readout and the number of superposed recordings needed are presented and discussed.