Showing papers on "Binary number published in 1980"

The chip complexity of binary arithmetic

Abstract: The chip complexity of a computation is concerned with the chip area, A, and the time, T, required to perform the computation when implemented on a chip. An area-time product ATα,for α ≥ 0, is used as a complexity measure. A particular value of α, which is chosen by the user, reflects the relative importance between A and T. This paper derives lower and upper bounds on the area-time complexity for chips that implement binary arithmetic, assuming a model of computation which is intended to approximate, current and anticipated LSI or VLSI technology.

Truth-table look-up optical processing utilizing binary and residue arithmetic.

Abstract: Two possible forms of numerical truth-table look-up processors using content-addressable optical holographic memories are presented. Application of these processors to performing numerical calculations in direct binary and in binary-coded residue number systems is discussed. Specific examples of the number of input and output bits required and the number of truth-table combinations holographically recorded for computation in both numerical systems are given. Truth-table look-up processing using binary-coded residue is shown to require the recording of dramatically fewer reference patterns than direct binary.

Binary to one out of four converter

Abstract: An apparatus and method for encoding information receiving a binary information stream. The apparatus actuates one of four outputs as determined by the last output actuated and the binary level of the binary bit received.

Binary decoding device

Abstract: In order to decode the bits of a message transmitted by an array of channels in parallel which have low reliability on account of the many disturbances which interfere with transmission, the binary decoding device comprises means for calculating the probability of error in each channel as a function of the coefficients of logarithmic likelihood of the decoded values and of the binary values received, as well as means for weighting the binary values received on each channel as a function of the calculated probability of error. In accordance with an optimum decision rule applied to the weighted values, a weighted decoding device delivers the binary values which are transmitted with the largest likelihood and the coefficients of logarithmic likelihood of these values.

High speed dividing circuit

Abstract: Logic circuit hardware is provided for dividing a binary fraction divisor into a smaller binary fraction dividend to provide a binary fraction quotient. Initially, the divisor is stored in a storage register with its sign in the highest order bit position and remains unchanged during the division operation. Initially, the dividend is stored in a dividend shift register and is shifted left one bit before being applied to a parallel adder to perform a partial divide operation. A clock signal is provided to time the division operations, wherein, the stored dividend is added to the stored divisor in a parallel binary adder. When the highest order or sign bit of the adder is positive, the sum of the dividend and the divisor are stored in the dividend register and a binary one is stored in a quotient register. When the highest order or sign bit of the adder is negative, the dividend register is shifted left and a binary zero is filled in the quotient register. Control means, including clock means, are connected logically to effect the division operation and data transfer without software implementation.

Interpolative encoder for subscriber line audio processing circuit apparatus

Abstract: An interpolative encoder for a subscriber line audio processing circuit including an interpolative analog-to-digital converter as shown in Fig. 9 for converting an input analog signal to a digital signal including a series of multi-bit binary words each consisting of all 0's or a series of one or more 0's and a series of one or more 1's, logic circuitry (150) for converting each multi-bit binary word into a modified binary word having a new binary format consisting of either all 0's or a single 1 and a plurality of 0's such that the value of each modified word is equal to the value of the corresponding multi-bit word converted such that the least significant bit thereof is doubled and made equal to the second bit in value, and a digital filter as shown in Fig. 17 for filtering the series of modified words.

On the near-optimum binary coherent-state receiver (Corresp.)

Abstract: A recent result on the operator representation for photoemissive detection is used to derive the operator measured by Kennedy's near-optimum receiver for binary coherent-state quantum communication.

Digital filters with reduced multiplier circuitry

Abstract: A digital filter comprises a circuit means for applying a plurality of binary coded weights to a binary coded input data. The circuit means is constructed such that any of integer amounting to the number of bits of the binary coded weight data or to the number of partial bits divided from the weight data is multiplied by the binary coded input data and a result of the multiplication is stored in a memory device in an address thereof corresponding to the integer, that the memory device is accessed by an address of the weight data or the partial bit, and that the digit of the data read out of the memory device is shifted and accumulated to produce a product of the input data and weight data. A product regarding a preceding input data and that regarding a succeeding input data are added together to produce a filter output.

Binary detecting and threshold circuit

Abstract: A repeating binary word detecting circuit produces a plurality of phase shifted samples of the logic of each binary bit forming the word. The plurality of samples are respectively compared with a stored sequence of bits forming the binary word to be detected. These comparisons are made for every possible beginning sequence of samples or stored bits between the time of two samples. An indication is given if a selected number of comparisons agree. A threshold circuit produces a decode output in response to a selected number of indications based on at least two phase shifted samples.

BCD-to-Binary converter

Abstract: A BCD to binary converter, particularly applicable for large numbers, employing an input level of code converter logic comprising PROM groups which provide a specially chosen initial conversion of the BCD number to be converted. Each PROM group comprises a plurality of individually programmed PROMs which provide for this initial conversion by directly converting successive sequential pairs of BCD digits into equivalent binary numbers taking into account their order of significance. A binary adder employing a plurality of PROM logic levels then provides for the binary addition of the binary bits produced by this initial conversion to provide the desired overall BCD to binary conversion.

Testing for numerical computations

Abstract: We consider the problem of error detection in programs or specialised devices computing real functions f(x), where the argument x is represented in binary form. For error detection we use the linear check inequalities |∑τeTf(x ⊕ τ) − C| ≤ e, where e ≥ 0 is some given small constant, ⊕denotes componentwise addition mod 2 of binary vectors, T is some set of binary vectors and C is a constant. A method for the construction of a minimal check set T and constant C for the given f(x) and ɛ is proposed. This method is based on the techniques of Walsh transforms and least-absolute-error polynomial approximation. Several important examples of optimal checks for programs computing exponential, logarithmic and trigonometric functions will be given.

On the coding, processing and display of binary images

Abstract: Large amounts of binary or nominally binary images are handled by humans and computers. Thus it is important with effective interaction as well as processing and storage of binary images.The thesis ...

Floating-point arithmetic and program correctness proofs

Abstract: This thesis develops tight upper and lower bounds on the relative error in various schemes for performing floating-point arithmetic, proposes axioms for characterizing the significant properties embodied by these schemes, and gives examples to illustrate how these axioms may be used to reason about the correctness of floating-point programs. Three addition schemes are considered: (1) chopped addition, (2) addition with both pre and post-adjustment rounding, and (3) addition with pre-adjustment chopping and post-adjustment rounding. Schemes for performing both rounded and chopped multiplication and division are also considered. Our tight bounds are consistent with the commonly held opinion that a binary base minimizes the maximum relative errors in floating-point arithmetic. Also, these bounds show that one guard digit is optimal for minimizing the maximum relative errors in chopped addition. The bounds derived for each of the addition schemes considered are as tight as possible. One guard digit and two guard bits are shown to be sufficient to round the result of an exact addition to the nearest floating-point number. We show how this scheme can be implemented using a single post-adjustment shift, no rounding overflow, and (for certain implementations) requiring no more time than an addition that chops instead of rounds. Two approaches are considered for axiomatizing floating-point arithmetic. In one approach, a set of floating-point numbers is associated with floating-point expression, and the assignment statement is modeled as a nondeterministic selector of one of the members in the set. In the alternative approach, the floating-point operations are modeled in terms of two cropping functions whose significant properties are characterized by a small set of axioms. In both cases, the axioms characterizing floating-point arithmetic are used with Dijkstra's weakest pre-condition calculus to provide an axiomatic framework for reasoning about floating-point programs. Finally, the common practice of modelling the floating-point operations by a single function that chops or rounds the result of the corresponding exact operation is shown to be invalid for many implementations of floating-point arithmetic.

Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders

Abstract: Parallel counters are multiple input circuits that count the number of their inputs that are in a given state. In this correspondence, the implementation of pipelined binary parallel counters with networks of latched quaternary threshold logic full adders is described and compared with the implementation using networks of latched binary full adders. Since each signal variable in quaternary logic may assume four logical states, twice the informational content of a binary variable, an over 50 percent savings in the total number of intermediate signal variables required to implement the parallel counter results. With the new quaternary logic circuits we will employ, over 40 percent fewer transistors and resistors are necessary for the implementation of pipelined binary parallel counters. The combination of these two factors could provide significantly reduced die areas for integrated pipelined parallel counters.

A digital filter structure requiring only m-bit delays, shifters, inverters, and m-bit adders plus simple logic circuitry

Abstract: digital filter structure is presented which requires only m -bit adders, shifters, and inverters, where m is the state-variable word length, to exactly realize the arithmetic operations for state equations. It is assumed that the coefficients in the state equations are finite-wordlength binary numbers; the canonical signed digit code is used to simplify these coefficients. All bits (including underflow bits) of the next state variables are computed, using two's complement (2's C) arithmetic, so the only source of roundoff error is the truncation of the exact next-state variables to m bits. Simple logic circuitry produces magnitude truncation, which suppresses all zero-input limit cycles if a diagonal Lyapunov function exists. Thus the above structure is applied to state equations derived for wave digital filters, which possess a diagonal Lyapunov function and yield short coefficient word lengths due to low sensitivity properties. A computer-simulated example, a third-order elliptic low-pass filter, is given with unit-sample response and frequency response for m equal to 8 and 16 bits.

Communications subsystem idle link state detector

Abstract: A data processing system includes a communications subsystem communicating with a number of devices A counter monitors the communication line to detect when a communication line goes idle, that is at least 15 successive binary ONE bits appear on the line for the bit oriented protocol mode The counter advances on successive binary ONE bits and is forced to a hexadecimal ZERO in response to a binary ZERO If the counter reaches a count of hexadecimal F (decimal 15) a carry signal from the counter prevents the counter from advancing and initiates an idle link state

Fast multiplier for long binary numbers - uses multiple and=gates to multiply one bit of first number simultaneously with every bit of second number and groups like weighted bits

Abstract: Fast multiplication of large binary numbers is obtained by multiplying one element of one number simultaneously with every element of the other number, cycling through each element of the first number and collecting binary product elements of common weight to obtain the product of the two binary numbers. The two 64 bit binary numbers are held in two registers with lines from each register cell, the lines being connected so a single line of one of the registers connects to one side of each of 64 AND gates (5) whose other input is a line from successive bits of the second number held in the other register. The AND gate outputs are connected to transcoder circuits which allocate weighting and hold the intermediate results which are regrouped to form the product by a logic array.

Binaryydecimal conversion system

Abstract: PURPOSE:To decrease the hardware without increasing the conversion processing- time, without correction of the decimal digit when the most significant bit of the shifter is ''1'', and by decimal correction by reducing ''6'' from the decimal digit in other cases. CONSTITUTION:In the system converting the binary number B into binary decimal number according to equation I, the two input decimal adder 13 has binary coded decimal number to one input A0 and +6 is inputted to another input A1 in response to each decimal number. Further, the register 15 stores the binary coded decimal number output of the adder 13, the register 16 stores the binary number to perform binary-decimal conversion, the shifters 17, 18 shift left by one bit the content of the registers 15, 16, and it is inputted to A0 of the adder 13. When the most significant bit of the decimal digit of the shifter 17 is ''1'' or in case of binary addition, if carry is produced from the most significant bit of the decimal digit, the adder 13 does not perform the correction 14 of the decimal digit and if any of them is not established, ''6'' is subtracted from the decimal digit for decimal correction 14. Thus, without increasing the conversion processing time, the amount of hardware can be reduced.

Binary to one of N decoder having a true and a complement output

Abstract: A digital decoder for use with a dual bus system is provided having a minimum number of transistors. The decoder is easily expandable to decode larger binary coded input signals. As a minimum only six transistors are needed to decode a three-bit binary input signal to provide outputs for a data bus and its complement. By using a minimum number of transistors, less current is required for the decoder. The circuitry used to provide each decoded output is repeated in a manner which conserves silicon area when the decoder is placed on silicon. A minimum number of control lines are used.

Binary scan system

Abstract: An original image is reproduced on an electrophotographic member with a series of binary data bits having a statistically valid count corresponding to the relative density of the original image. A sensor senses the density value of individual information forming structure or structures in incremental areas of the original image and converts the density values into a series of binary data bits, one bit per incremental area. An imager receives the binary data bits and forms one binary element on the charged electrophotographic member surface in response to each bit. The elements formed on the member surface correspond in sense to the binary data bits from the sensor and the elements are formed in incremental areas of the member corresponding to the incremental areas of the original image from which their respective binary data bits were produced. An aperture of the sensor which determines the size and configuration of the incremental area scanned is adjustable to aproximately the size and configuration of the information structure and a threshold level value of the sensed density values is adjustable to the mean of the sensed densities of the original image so that a sensed density value above the threshold value produces a binary bit of one sense and a sensed density value below the threshold value produces a binary bit of the other sense to produce the statistically valid count of the series of binary data bits.

Circuit for implementing a digital computer instruction

Abstract: Apparatus for implementing a single computer instruction for moving a binary number of from one to four characters, with the characters of a given binary number having either eight or nine bits per character, from storage in a word addressable memory to a designated addressable register. The characters of the binary number are stored in the word addressable memory with each word of memory being divided into four 9-bit bytes. The most significant character of the binary number can be stored in any designated byte position of a word location with the characters of the number stored in contiguous byte locations in descending order of significance. The apparatus causes the binary number to be stored in the designated addressable register with the binary number being right justified in that register. Higher order bit positions of the register not needed to store the bits of the binary number will have stored into them fill bits or the sign bit of the number.

On Negabinary-Binary Arithmetic Relationships and Their Hardware Reciprocity

Abstract: This correspondence emphasizes the close relationship between binary addition and negative negabinary addition (n.n.b.a.). This is established by describing two possible ways of utilizing binary adders for performing n.n.b.a. Similar techniques of using n.n.b.a. adders for binary addition are also outlined and thus, negative addition is seen to be a primitive operation. These algorithms lead to four simple conversion processes of numbers from binary to negabinary system and vice versa.

Digital Logic and Arithmetic: Background for Interfacing Microcomputers

Abstract: In order to effectively plan and develop projects involving microcomputers, the industrial engineer requires background information on number systems, binary arithmetic, and binary logic. In this tutorial article, a basic introduction to these topics is provided. Specific topics include: positional number systems, conversion between number systems, addition and subtraction of binary numbers, the two's complement of negative numbers, the ASCII and Gray codes, the basic logic functions (AND, OR, NOT, NAND, NOR, XOR), and some applications of basic logic functions, including a decoder, an adder, and a binary latch. This is the first of an integrated series of articles dealing with concepts and techniques for interfacing microcomputers to industrial devices.

Generation of multilevel digital signals from binary signals having a very high bit rate

Abstract: Binary signals are frequently combined from multi-level digital signals for the optimal utilisation of the transmission capacity of digital transmission links. For this purpose, the binary signals are subjected to a weighted addition. At very high bit rates, problems occur with respect to the exact weighting and the reaction-free addition. According to the invention, a circuit arrangement based on a base-coupled differential amplifier (T1, T2) is proposed in which the differential amplifier is preceded by a number of emitter-coupled differential amplifiers (T3, T4...T2n+1, T2n+2) corresponding to the number of input signals.

Fast binary logarithm computing circuit for binary numbers less than one

Abstract: A fast and expandable circuit for computing the approximate binary logarithm and antilogarithm of a fractional binary number is described. Illustration examples are included, and accuracy of the circuit is discussed.

Binary threeelevel signal system

Abstract: PURPOSE:To simplify operation without using a clock signal, etc., by setting a signal of the 3rd level in addition to a binary signal when recording or inputting binary code information and by allotting the signal of the 3rd level to even-numbered signals when the same binary signals continue. CONSTITUTION:To convert binary code into a three-level signal, a shift to low- level signal L is made when binary code information of ''0'' appears after high- level signal H is outputted and a shift to signal M of the 3rd level differing from the binary signal is made when binary code information of ''1'' appears. When binary code information of ''0'' comes after low-level signal L, a shift to level signal M of the 3rd level is made. When information of ''0'' comes after signal M of the 3rd level, a shift to low-level signal L is made and when information of ''1'', a shift to high-level signal H is made. Then, conversion from binary code information into a three-level signal is carried out easily through automatic of manual operation.

Improved binary detecting and threshold circuit

Abstract: A repeating binary word detecting circuit (14-44) produces a plurality of phase shifted samples of the logic of each binary bit forming the word. The plurality of samples are respectively compared (17) with a stored sequence of bits (18) forming the binary word to be detected. These comparisons are made for every possible beginning sequence of samples or stored bits between the time of two samples. An indication is given if a selected number of comparisons agree. A threshold circuit (41) produces a decode output in response to a selected number of indications based on at least two phase shifted samples.