Showing papers on "Binary number published in 1981"

The Area-Time Complexity of Binary Multiplication

Abstract: The problem of performing multtphcaUon of n-bit binary numbers on a chip is considered Let A denote the ch~p area and T the time reqmred to perform mult~phcation. By using a model of computation which is a realistic approx~mauon to current and anucipated LSI or VLSI technology, ~t is shown that A T 2.

A Proposed Standard for Binary Floating-Point Arithmetic

Abstract: Offered here for public comment, this proposed standard facilitates transportation of numerically oriented programs and encourages development of high-quality numerical software.

The entropic limitations on VLSI computations(Extended Abstract)

Abstract: In this paper we will explore the limitations imposed by entropic constraints, both in generality and for specific problems. We list below the main questions that we will address. (1) In the binary number system, addition is easy while multiplication is hard for VLSI. Is there an “ideal” number representation, in which all arithmetic operations have efficient VLSI implementations? (2) Can one build multipliers for binary numbers, which achieve both small area and fast average computation time? (3) Thompson's technique applies only to multiple output functions. How can one prove area-time bounds for single output functions? (4) What other ways are there for deriving entropic constraints from consideration of data movement? Answers to these questions will be discussed in the ensuing sections.

Source coding for multiple descriptions II: A binary source

Abstract: A uniformly distributed (iid) binary source is encoded into two binary data streams at rates R 1 and R 2 , respectively. These sequences are such that by observing either one separately, a decoder can recover a good approximation of the source (at average error rates D 1 , D 2 , respectively), and by observing both sequences, a decoder can obtain a better approximation of the source (at average error rate D 0 ). In this paper a “converse” theorem is established on the set of achievable quintuples (R 1 , R 2 , D 0 , D 1 , D 2 ). For the special case R 1 = R 2 = 1/2, D 0 = 0, and D 1 = D 2 = D, our result implies that D ≥ 1/5.

High-speed arithmetic compression coding using concurrent value updating

Abstract: A method and apparatus for recursively generating an arithmetically compressed binary number stream responsive to the binary string from conditional sources. Throughput is increased by reducing the number of operations required to encode each binary symbol so that only a single shift of k bits is required upon receipt of each least-probable symbol or an "add time", followed by a decision and a one-bit shift in response to each most-probable symbol encoding. The concurrent augmentation of the compressed stream and an internal variable involves only the function of a probability interval estimate of the most-probable symbol, and not upon the past encoding state of either variable (2 -k , 49, 63, C, T). Each binary symbol may be recovered by subtracting 2 -k from the q-most-significant bits of the compressed stream and testing the leading bit of the difference.

A topological analysis of the complexity of computer programs with less than three binary branches

Abstract: Katzan [4] defines the complexity of a system as referrin g to the number of relations or connections among components of th e system . Most would agree that it is an understatement to sa y that computer programs are complex entities . Indeed, they are s o complex that at times one marvels at the fact that they are eve n developed . Even more important than their original developmen t however, is the fact that they must often be modified an d therefore comprehended over and over again by people, mos t likely not the original developer, during the debugging an d maintenance phases .

Method and means for pipeline decoding of the high to low order pairwise combined digits of a decodable set of relatively shifted finite number of strings

Abstract: An apparatus for ensuring continuous flow through a pipeline processor as it relates to the serial decoding of FIFO Rissanen/Langdon arithmetic string code of binary sources. The pipeline decoder includes a processor (11, 23) and a finite state machine (21, FSM) in interactive signal relation. The processor generates output binary source signals (18), status signals (WASMPS, 31) and K component/K candidate next integer-valued control parameters (L0, k0; L1, k1; 25). These signals and parameters are generated in response to the concurrent application of one bit from successive arithmetic code bits, a K component present integer-value control parameter (52) and K component vector representation (T, TA) of the present internal state (51) of the associated finite state machine (FSM). The FSM makes a K-way selection from K candidate next internal states and K candidate next control parameters. This selection uses no more than K2 +K computations. The selected signals are then applied to the processor in a predetermined displaced time relation to the present signals in the processor. As a consequence, this system takes advantage of the multi-state or "memory" capability of an FSM in order to control the inter-symbol influence and facilitate synchronous multi-stage pipeline decoding.

An Enskog Correction for Size and Mass Difference Effects in Mixture Viscosity Prediction.

Abstract: A method is presented which corrects the one-fluid conformal solution viscosity model for size and mass difference effects. This correction, which is based on the Enskog model for hard sphere mixtures, is empirical as applied to transport but has a rigorous basis in equilibrium theory. Comparisons of predictions and experimental viscosities for 24 binary mixtures are presented.

Speech synthesis system

Abstract: 8 A speech synthesis system comprising input means for receiving frames of speech data, said frames of speech data comprising binary representations of speech-determinative data Interpolation means are coupled to said input means for interpolating between adjacent frames of said speech data Further synthesizer means are coupled to said input means and to said interpolation means for selectively converting said speech data and interpolated values thereof into signals representative of human speech Means are coupled to said synthesizer means for producing audible sound The frames of speech data as received by said input means include coded frame rate data Decoding means are coupled to said input means for decoding said frame rate data The interpolation means are also coupled to said decoding means for providing a variable number of interpolation calculations between adjacent frames of speech data The variable number of interpolation calculations being directly related to said frame rate data The speech synthesis system may be constructed by employing metal-insulator-semiconductor technology so as to provide circuits capable of low voltage operation

Multiplier for binary numbers in two's-complement notation

Abstract: A device for multiplying two binary numbers in two's-complement notation having an array for forming bit-wise partial products and a further array for successively forming the result bits therefrom. The modules of the further array form either a full adder or a full subtractor under the control of a one-bit control signal. The negative sign of the most-significant bits of the factors can thus be taken into account. Devices of this kind can be linked in order to realize multiplications with higher precision, variation of the control signal signalling that only the device to which a most significant factor bit is applied takes into account a negative sign. A pipe line product-accumulator device is formed by construction in n-MOS dynamic logic circuits, with an inherent trigger function on the outputs of full adders/subtractors.

Ternary 3PM magnetic recording code and system

Abstract: In 1976, ISS Sperry/UNIVAC introduced the 8434 disk drive with the binary 3PM code. This code increased the linear bit density by 50% over the generally accepted MFM code. The present paper introduces the ternary version of the 3PM code that is capable of further increase in bit density. This new code uses ternary signal elements, still relying on saturation recording techniques. The ternary alphabet permits the use of more combinations than the binary. Therefore, higher code rate (2/3) and Targer detection window (66%) can be realized than in binary. Test results show 6,000 bits/cm linear bit density on 3370 equivalent head/disk interface with an error rate better than 1 × 10-10.

Variable size character generator

Abstract: Apparatus and method of generating variable size, point-display type characters. Each character is defined through a matrix comprising a plurality of identical block elements. One of a predetermined number of geometric patterns forming a section of each character is disposed within each block element. A distinct binary index code is assigned to each geometric pattern on a row-by-row, column-by-column basis of each character matrix for the entire character set to be displayed and stored in a first memory. A binary code defining the sequence of binary states of the points in the point display of each geometric pattern is assigned to each geometric pattern on a line-by-line basis for each block element of the character matrix. The first set of binary codes are selected on a row-by-row, column-by-column basis for the character matrix of the selected character. A second set of binary codes are generated in response to the selected first binary codes, with the second binary codes corresponding to the sequence of binary states of the points defining the point matrix on a line-by-line basis for each block element of the selected character matrix. A binary sequence of signals is generated in response to the second binary codes which are used to generate each character point-by-point.

Arithmetic circuits for digital filters

Abstract: A digital filter is provided which selectively employs binary arithmetic and offset two's complement arithmetic in an adder ladder to protect against signal overflows and underflows, as well as to minimize adder size. Signal overflows and underflows are prevented by performing subtraction and certain additions in offset two's complement notation, while adder sizes are minimized by performing certain other additions in binary notation. In an alternate embodiment, positively weighted values are combined by binary addition in a first adder ladder, and negatively weighted values are combined by binary addition in a second, parallel adder ladder. At the outputs of the two ladders, the two sums are converted to offset two's complement notation, and the negatively weighted sum is subtracted from the positively weighted sum.

One-bit frequency-shift-keyed modulator

Abstract: A shift-keyed modulator utilizes a lookup table (41) to provide a binary sequence of digits one at a time. Since the binary digits are selected so that their accumulation represents the amplitudes of a series of points on a theoretical sinusoidal wave, a low-pass filter (51) acting as an integrator is able to provide a sinusoidal wave signal. Furthermore, the low-pass filter includes gates that operate in push-pull fashion to form a balanced configuration for cancelling even ordered harmonic distortion. The modulator has a rate multiplier (11) responsive to space/mark signaling for controlling the rate that the binary digits are produced by the lookup table. A second group of binary digits is stored in the lookup table and is read out concurrently with the first sequence. Alternate pairs of gates (52 and 53 or 54 and 55) are enabled in the low-pass filter to provide binary data signals for either of the frequency bands used in duplex data signaling circuits.

Magnitude comparator circuit and method

Abstract: A magnitude comparator circuit is provided for determining the largest binary number, out of a plurality of binary numbers received bit-serially, in parallel A latch is used to store the results of the comparison and is initialized to an all logic 0 state The latch has a unique one-bit location corresponding to each number being compared, and a logic 0 stored in the latch indicates that the number corresponding thereto is still in contention (ie remains a candidate) for being the largest, and a logic 1 indicates it has been eliminated from contention As the numbers are received bit by bit (most significant bits first) the bits are applied to gating circuits, one for each number, which invert the bits and store the inverted result in the latch The exceptions to this are twofold; (a) when a number has already been eliminated from contention, as indicated by a logic 1 stored in the latch corresponding to that number, it remains a logic 1; and (b) when the remaining candidates all have a binary 0 in an equal significant bit location no choice is of course possible and the aforestated inversion does not take place and the contents of the latch are simply recycled

Code converter for polarity-insensitive transmission systems

Abstract: A polarity-insensitive code converter in which blocks of binary digits are translated into multilevel words having either one mode or another mode so that each coded word of one block of binary digits is the inverse coded word of the block of inverse binary digits. Hence, the inversion of a code word during transmission results in the inversion of the recovered binary. With additional precoding and postcoding of the binary signal, polarity integrity of the original signal can always be restored.

A two's complement cellular array multiplier

Abstract: A cellular array for the multiplication of signed binary numbers is presented. The implementation is based on the direct addition of the partial products. The addition of the negative partial products is performed with a new method which yields a fully cellular array. Furthermore, the proposed array multiplier has an iterative cell interconnection pattern and it is well suited for large-scale integration.

Digital adder circuit for binary-coded numbers of radix other than a power of two

Abstract: A digital adder circuit for binary-coded-decimal operation, comprising a set of multiplexers (11) which are conditioned with a pattern of input bits causing them to form an intermediate result (IR) equal to the sum of the two operands (A0-A3, B0-B3) plus a correction value of six. The intermediate result is adjusted by subtracting the correction value if the intermediate result is less than sixteen. The circuit is also operable in a pure binary mode, or can be made to perform various logical operations.

Method and apparatus for encoding digital data

Abstract: Digital data formed of binary bits of first and second values occupying consecutive bit cells of predetermined intervals are encoded such that successive binary bits of the first or second values are represented by predetermined separations between succeeding transitions. A first transition is produced at a first reference point in a bit cell when a binary bit of the second value changes over to a binary bit of the first value. When successive binary bits of the first value are sensed, a respective second transition is produced at a second reference point in a bit cell after sensing every 2 or 3 binary bits of the first value. When successive binary bits of the second value are sensed, a respective second transition is produced at the second reference point in a bit cell when at least two successive binary bits of the first value are followed by a binary bit of the second value and also after sensing every 3 or 4 successive binary bits of the second value, such that the last-mentioned second transition at the second reference point is separated from the closest first transition thereto by at least 1.5 bit cell intervals but no more than 4.5 bit cell intervals and successive ones of the second transitions are separated from each other by no more than 4 bit cell intervals.