Showing papers on "Binary number published in 1983"

Apparatus for symmetrically truncating two's complement binary signals as for use with interleaved quadrature signals

Abstract: Symmetrical truncation of two's complement binary numbers is performed by simply discarding the LSB's of positive values and by adding "one" to the truncated negative value when any one of the discarded LSB's is a logical "one" value. Apparatus to perform an N bit truncation includes an incrementer, a two input AND gate and an N-input OR gate.

The reconstruction of two-directionally connected binary patterns from their two orthogonal projections

Abstract: A heuristic reconstruction algorithm is described, by which binary matrices can be produced from their two orthogonal projections. It is necessary for proper reconstruction that the binary pattern corresponding to the binary matrix bex- andy-directionally connected. By this method a large class of binary matrices can be reconstructed. It is proved that after a finite number of iterative steps this algorithm produces all thex- andy-directionally connected binary patterns belonging to the given two projections. Finally, some remarks on the implementation of this algorithm and results are presented.

A Combinatorial Construction of Perfect Codes

Abstract: A combinatorial construction for perfect binary single error correcting codes is presented. Several results are derived from this construction. In particular, we establish that there are a large number of nonisomorphic perfect codes of length 15.

Bus access arbitration using unitary arithmetic resolution logic and unique logical addresses of competing processors

Abstract: A composite address resolution scheme is used in a distributed processing computer communications system. Many parallel processors are connected together via a multi-processor intertie bus, which serves to communicate data from any processor to any other processor. Resolution of control among several competing processors which desire access to the bus is resolved directly on the bus. The processors are online replaceable; and the system fails soft. Each processor contains resolution logic which enables simultaneous parallel resolution by any number of processors. The resolution is performed on the basis of a composite logical address (CLA) which originates within each processor. The CLA can contain non-unique priority information as well as unique logical location information. The bus is awarded to the processor exhibiting the lowest CLA. The resolution is performed starting with the most significant bit or bits and working downward towards the least significant bit or bits. The resolution for each bit or bits is delayed an appropriate period of time to enable resolution information from each processor to travel along the bus to all other processors which might be requesting access. Individual resolutions are performed by resolve elements which analyze the status of each binary bit or group of bits following translation into unitary state representation. The number of resolves can be reduced, thereby increasing the speed of the network, by means of performing resolves on two or more binary bit positions simultaneously, provided one is willing to accept added complexity.

Finite Precision Rational Arithmetic: An Arithmetic Unit

Abstract: The foundations of an arithmetic unit performing the add, subtract, multiply, and divide operations on rational operands are developed. The unit uses the classical Euclidean algorithm as one unified algorithm for all the arithmetic operations, including rounding. Binary implementations are discussed, based on techniques known from SRT division, and utilizing ripple-free borrow-save and carry-save addition. Average time behavior is investigated.

Conversion of multilevel digital data to binary data

Abstract: A system for converting a multilevel video signal into a binary video signal for use in an image processing machine such as a facsimile machine or digital copier includes a threshold setting circuit which first determines average density levels of a predetermined number of scanning lines and then a digitally weighted average of these average density levels, said digitally weighted average being used as a threshold for the binary conversion processing.

Optimization of binary thermodynamic and phase diagram data

Abstract: An optimization technique based upon least squares regression is presented to permit the simultaneous analysis of diverse experimental binary thermodynamic and phase diagram data. Coefficients of polynomial expansions for the enthalpy and excess entropy of binary solutions are obtained which can subsequently be used to calculate the thermodynamic properties or the phase diagram. In an interactive computer-assisted analysis employing this technique, one can critically analyze a large number of diverse data in a binary system rapidly, in a manner which is fully self-consistent thermodynamically. Examples of applications to the Bi-Zn, Cd-Pb, PbCl2-KCl, LiCl-FeCl2, and Au-Ni binary systems are given.

Parallel syntactic thinning by recoding of binary pictures

Abstract: In recoding with three bits the pixels of objects in binary images according to some measure of distance to the background, parallel thinning is achieved using syntactic rules. The codes in a 3 × 2 window are searched for interrelations which determine the new code of the central pixel. The local structure of the codes is determined through a binary cascade of tables. To each structure corresponds a rewriting rule. The new code is the output of the cascade. A two-scan postprocessing is needed to obtain a skeleton with linear structure.

A carry-free algorithm for finding the greatest common divisor of two integers

Abstract: We investigate a variant of the so-called “binary” algorithm for finding the GCD (greatest common divisor) of two numbers which requires no comparisons We show that when implemented with carry-save hardware, it can be used to find the modulo B inverse of an n-bit binary integer in a time proportional to n, using only registers of length proportional to n Such a hardware implementation of this algorithm set up for finding inverses with respect to a 336 bit modulus B would have applications in the currently expanding field of secure data transmission and storage In such an implementation, multiplication in linear time-both modulo B and ordinary—would come along as a by-product because multiplication can be achieved by a sequence of nine inversions, some additions and negations

A fast recursive algorithm for binary-valued two-dimensional filters

Abstract: An efficient algorithm for computing the response of a linear spatially varying digital image filter to an arbitrary digital input image is described. This response is the superposition summation of the input image with a digital point spread function (PSF). It is assumed here that the PSF is binary valued. The approach to this computation is based on the Principle of Inclusion and Exclusion. This approach leads to a new efficient algorithm. This algorithm is also efficient when the PSF is spatially invariant.

A new distance mapping and its use for shape measurement on binary patterns

Abstract: The paper describes a new class of distance mappings for binary images, which are based on a border-to-border distance rather than on the distance between an individual point and the border of an object. It is shown how these mappings can be used to calculate efficiently meaningful features like the “line-shapeness” or “compactness” of objects within binary images or to characterize binary images in a global sense. The algorithms involved are well suited for conventional sequential processors.

Demodulator for an asynchronous binary signal

Abstract: To decode a binary signal without regard to the speed at which it is read, each transition in the binary signal is detected, and the time lapse between successive transitions is determined to thereby establish the length of a pulse in the binary signal. The length of one pulse is compared with that of the immediately preceding bit cell to determine whether their lengths are approximately the same or vary by a factor of approximately 2, and any change in the binary state of the signal is determined accordingly. A multiplexing technique is employed to simultaneously decode a number of signals in this manner.

Equal nine apparatus for supporting absolute value subtracts on decimal operands of unequal length

Abstract: A data processing system having a central processing unit (CPU) capable of performing binary and decimal arithmetic software instructions is disclosed. The CPU includes a microprocessor which executes the binary arithmetic software instructions under firmware control. Also disclosed is apparatus utilizing a programmable memory and logic circuits that are used to subtract two operands and to generate and temporarily store a digit equal nine indication when the result of subtracting the two operands has a value of nine.

Vital processor implemented with non-vital hardware

Abstract: A method and apparatus for effecting vital functions notwithstanding the fact that non-vital hardware is employed. A vital processor is implemented using non-vital hardware in the form of a digital computer which may for example be a microprocessor. The vital processor accepts binary input values and, based on a series of logical expressions relating output values to input values, determines the appropriate output values. Rather than employing a single bit to represent the condition of a particular input or output, unique multibit binary values or names are used. Each input or output has assigned to it at least two unique multibit values, each satisfying the code rules of a different code. Thus rather than representing a closed contact as a single 1 bit, and an open contact as a single 0 bit, the closed contact is represented by a unique multibit name which satisfies the code rules of a first code. At any point in the processing the value representing the contact can be checked to see if it satisfies the code rules, and if it does not a potential error is detected and handled. Although it is highly unlikely that a hardware failure would result in generating one of the few multibit names satisfying the code rule, that occurrence is not unlikely enough to be considered vital. Before actually controlling output devices in accordance with the processing, further tests are implemented which ensure that the multibit value computed for a particular output not only satisfies the predetermined code rule which is required, but is also correct bit for bit. Logic equations describing the relationship between output and input are actually computed using the multibit values as opposed to single bit values.

Method of storing characters in a display system

Abstract: In a method of storing characters in a display system having a display device with an orthogonal matrix of addressable points, each character is represented as a succession of strokes each constrained to lie in one of the eight fundamental directions of the matrix and, except for the first stroke, each starting at the end of the previous stroke. Each such stroke is stored in a binary coded form which includes a first binary number (direction code) defining the angular direction of the stroke, a second binary number (length code) defining a number of matrix steps from one addressable point to the next along the stroke in that direction, and a third binary number (move/draw code) defining the visibility of the stroke. In order to facilitate character rotation by any multiple of 45° the direction code defining each fundamental direction corresponds to the addition modulo 2" of a binary constant to the direction code which defines the fundamental direction at 45° thereto in a given direction of rotation, where n is the number of bits in the direction code.

Apparatus for executing an instruction and for simultaneously generating and storing related information

Abstract: In a computer system, an instruction is executed. The results of the execution of the instruction are stored, and, simultaneously with the execution of the instruction, information is generated and stored which is related to the results of the execution of the instruction. This information is used by the computer system during the execution of subsequent instructions. The results of the execution of the instruction comprise a binary number. The information which is generated, simultaneously with the execution of the instruction, includes, inter-alia, a count of the number of binary "1" bits and binary "0" bits which constitute the binary number, and a set of addresses representing the address locations of each bit of the binary number which constitutes the stored results of the execution of the instruction. The set of addresses include a first set of addresses representing address locations for all the binary "1" bits and a second set of addresses representing address locations for all the binary "0" bits of the binary number. The first set of addresses are stored in a first portion of a memory, the second set of addresses being stored in a second portion of the memory. As a result, the information is immediately available upon completion of the execution of the instruction.

On Binary DPSK Error Rates Due to Noise and Intersymbol Interference

Abstract: This paper presents a new series for evaluating the conditional bit error rate (BER) of a given transmitted data sequence in a band-limited binary differential-phase-shift-keyed system. This series involves modified Struve functions and it was found to have converged quickly. The conditional BER can then be averaged over all possible bit sequences to yield the system BER. The results obtained are close to those reported by G. J. Marshall. In our analysis the noise samples a bit period apart were assumed to be uncorrelated.

Digital clock bit synchronizer

Abstract: A clock wave is synchronized to the frequency of serial binary data bits. Digital circuitry derives a clock wave by responding to the data bits to selectively (a) increment a reference frequency, (b) decrement the reference frequency, and (c) not change the reference frequency. The digital circuitry divides each data bit into an even number of sub-bits. The binary value associated with a first half of the divided sub-bits of a particular data bit is compared with the binary value associated with a second half of the divided sub-bits of the particular data bit. In response to the derived clock wave and the comparison, the reference frequency is derived, incremented or decremented. The frequency of the source is respectively incremented and decremented in response to first and second relations of the binary value associated with the first half relative to the binary value associated with the second half. The frequency of the source is not changed when the binary values associated with the first and second halves are equal.

Apparatus for performing simplified decimal multiplication by stripping leading zeroes

Abstract: Processor apparatus is described for performing binary and decimal arithmetic operations. In performing decimal multiplication with the processor apparatus, to reduce the amount of processing to be done with the apparatus and thereby speed up the performance of the decimal multiplication, the leading zeroes prefixing the highest order significant digit in both a multiplier and a multiplicand are identified, counted and removed. Decimal multiplication is then performed using the stripped multiplier and multiplicand, and to the resultant partial product a number of zeroes are prefixed equal to the number of zeroes originally stripped from the multiplier and multiplicand. The result is the product of the original multiplier and multiplicand.

Improved Accuracy For An Optical Iterative Processor

Abstract: A scheme is introduced and experimentally demonstrated for increasing the accuracy of an optical implementation of matrix-vector multiplication. The system is configured in a feedback loop to iteratively solve simultaneous equations. The technique is based upon a binary expansion of the matrix which is convolved with the binary expansion of the vector. This is implemented optically by the outer product synthesis of matrix products using crossed acousto-optic cells and a strobed light source.© (1983) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

A Fast Complementation Algorithm for Sum-of-Products Expressions of Multiple-Valued Input Binary Functions,

Abstract: : A recursive algorithm to obtain a complement of a sum-of-products expression for a binary function of p-valued input variables is presented.

Direct Implementation of Discrete and Residue-Based Functions Via Optimal Encoding: A Programmable Array Logic Approach

Abstract: This paper presents a technique for direct truth table implementation of residue-based functions by an encoding scheme that employs programmable array logic (PAL) technology. The scheme models the basic associative memory operation, i.e., the detection of matchings between input patterns and prestored information in the PAL's. The complexity of this model is related to the amount of stored logic, i.e., the P-terms in the logic arrays. A linear programming approach is proposed for the encoding of the residue set with the objective of minimizing the complexity of addition and multiplication, modulo M, simultaneously. It is shown that the addition is more complex than the multiplication modulo M, with both (two-operand) operations being upper bounded by O(M2). Results produced using the optimal encoding compare favorably to corresponding results regarding the usual binary representation of residues. Practical constraints are also considered such as limitations on the number of pins, the number of P-terms, and the chip area, with the latter shown to be more efficiently utilized in the PAL scheme than in a ROM-or PLA-based implementation. The encoding technique is also applicable to the functions of discrete logic, in general.

Overflow detector for algebraic adders

Abstract: An MOS high-speed overflow detector for algebraic adders which add two binary numbers (a,b) in two's complement notation and contain one full adder per digit which provides a sum signal (s) and a carry signal (c) consists of a complex gate (k) made up of three two-input AND elements (u1, u2, u3). The outputs of the three AND elements are NORed. The two inputs of the first AND element (u1) are fed with the sign signal (va) of the first binary number (a) and with the inverted sign signal (vb) of the second binary number (b), respectively. The two inputs of the second AND element (U2) are fed with the sign signal (vb) of the second binary number (b) and with the sum signal (vs) of the full adder (av) of the sign digit, respectively. The two inputs of the third AND element (u3) are fed with the inverted sum signal (vs) and the inverted sign signal (va) of the first binary number (a), respectively.