Showing papers on "Binary number published in 1984"

Connected components in binary images: The detection problem

Abstract: From the Publisher: Concerns the separation of objects from their background--a major problem in pattern recognition. This unique monograph outlines--down to the code level--an algorithmic approach to the real-time detection of connected components in binary pictures acquired in a raster-scan fashion.

Communication interface connecting binary logic unit through a trinary logic transmission channel

Abstract: A communications interface for transferring data from a first binary logic circuit to a second binary logic circuit by using a trinary logic transmission channel. The first set of binary logic signals is converted into a first set of binary control signals which, in turn, control trinary drivers connected to the transmission channel. The trinary drivers drive the transmission channel to one of three discrete voltage levels as opposed to one of two levels in binary systems. Trinary receivers are located on the second binary logic circuit and are connected to the trinary transmission channel. The receivers produce a second set of binary control signals which are translated into a second set of binary logic signals for use by the second binary logic circuit.

Optical logical processing in parallel with theta modulation

Abstract: Theta modulation is used to implement in parallel the nonlinear class of logical operations. This includes binary logic as well as higher-order logic, such as residue-number arithmetic. Theta modulation, which means encoding of pixel information by grating structures of different orientations, involves a preprocessing operation. For this purpose, a hybrid optical–electronic system is used. Basic principles for logical operations with theta modulation are outlined and experimental examples are given for different types of information encoding, for binary and ternary logical operations, and for addition in the residue-number system.

Electrooptical matrix multiplication using the twos complement arithmetic for improved accuracy

Abstract: The improved electrooptic signal processing relies upon matrix-matrix multiplication using twos complement arithmetic. A source of pulse collimated light illuminates two two-dimension spatial light modulators that operate in a reflective mode through a polarizing beamsplitter. Each of the spatial light modulators has a matrix of optically encoded information of numbers in the twos complement binary representation so that a mixed binary representation of signals is generated within the two-dimensioned photodetector array. The mixed binary representation signals are decoded to a twos complement binary representation or a decimal representation to be useful for more conventional processing techniques. The twos complement arithmetic when incorporated with the electrooptic architecture provides for a convenient means for handling bipolar numbers, avoids the need for matrix partitioning when the matrices are real and offers a means to improve accuracy over conventional optical analog techniques.

Algorithms for the euler characteristic and related additive functionals of digital objects

Abstract: The Euler characteristic, the volume, the surface, and the mean width belong to the more important geometric properties of the polytopes in R d . They may be considered as values of certain additive functionals belonging to the family of the so-called quermassintegrals which are more generally defined for all bounded polyhedra in R d . A first recursive algorithm is presented to compute all quermassintegrals of digital objects in R d and a second one just for the Euler characteristic. The digital objects are assumed to be represented as binary arrays. The complexity of both algorithms is shown to be of the order of the number of elements of the respective binary arrays.

Symmetrical optimized adaptive data compression/transfer/decompression system

Abstract: Data compression for transfer (storage or communication) by a continuously adaptive probability decision model, closely approaches the compression entropy limit. Sender and receiver perform symmetrical compression/decompression of binary decision n according to probabilities calculated independently from the transfer sequence of 1 . . . n-1 binary decisions. Sender and receiver dynamically adapt the model probabilities, as a cumulative function of previously presented decisions, for optimal compression/decompression. Adaptive models for sender and receiver are symmetrical, to preserve data identity; transfer optimization is the intent. The source model includes a state generator and an adaptive probability generator, which dynamically modify the coding of decisions according to state, probability and bit signals, and adapt for the next decision. The system calculates probability history for all decisions, including the current decision, but uses probability history for decision n-1 (the penultimately current decision) for encoding decision n (the dynamically current decision). The system, separately at source and destination, reconfigures the compression/expansion algorithm, up to decision n-1, codes each decision in the data stream optimally, according to its own character in relation to the calculated probability history, and dynamically optimizes the current decision according to the transfer optimum of the data stream previously transferred. The receiver operates symmetrically to the sender. Sender and receiver adapt identically, and adapt to the same decision sequence, so that their dynamically reconfigured compression-expansion algorithms remain symmetrical--even though the actual algorithms may change with each decision as a function of dynamic changes in probability history.

On the minimum distance of some quadratic residue codes (Corresp.)

Abstract: We find the minimum distances of the binary (113, 57) , and ternary (37, 19), (61, 31), (71, 36) , and (73, 37) quadratic residue codes and the corresponding extended codes. These distances are 15, 10, 11, 17 , and 17 , respectively, for the nonextended codes and are increased by one for the respective extended codes. We also characterize the minimum weight codewords for the (113, 57) binary code and its extended counterpart.

Variable-passband variable-phase digital filter

Abstract: A variable-passband, variable-phase digital filter in which Q digital samples of a signal are entered through (Q-1) delay lines, to be delayed into q two-bit adjacent doublets. Weighting tables in read only memories are addressed by each doublet. Each weighting table includes the results of linear combinations of the weights of doublets composed of bits of the same order multiplied by multiplier coefficients which are smaller than unity. Each integral portion of a result found in a table is applied at the same time as the fractional portions of the other results provided by the other tables to the addressing inputs of a programmed memory containing binary words. Binary words are addressed in the prorammed memory by the integral and fractional portions of the results found in the weighting tables. Each binary word has a value equal to the linear combination of the corresponding values of the samples of the signal by the multiplier coefficients.

Bit Error Rate Evaluation for Spread-Spectrum Multiple-Access Systems

Abstract: A unified method for approximating and bounding the average bit error probability for spread-spectrum multiple-access communication systems is presented. Various forms of direct-sequence spreadspectrum modulation are considered including binary phase-shift keying, quadriphase-shift keying, and minimum-shift keying. The analysis of the multiple-access interference makes use of a number of moments sufficent to evaluate the error probability with a high degree of accuracy. A computationally efficient algorithm for computing the moments is also given. The subsequent transformation from the moments to the average bit error probability is carried out by means of Gauss-type numerical integration formulas. It is shown that the same approach can be exploited for evaluating two classes of upper and lower bounds on the bit error rate. Finally, some results and comparisons are reported.

A note on binary arrays with a certain window property (Corresp.)

Abstract: For some rs = 2^{mn} , there exist periodic r \times s binary arrays such that all m \times n binary matrices will appear in it. As two-dimensional versions of de Bruijn sequences, these kinds of arrays have possible applications in cryptography and the design of mask configurations for spectrometers.

Gray code counter

Abstract: A gray code counter is produced from a binary code counter by connecting each output of the binary counter to a "toggle" flip-flop. Each toggle flip-flop has a toggle input connected to its corresponding binary output. The output of each toggle flip-flop changes state (i.e. "toggles") only when its corresponding binary code bit makes a transition from a first level to a second level (i.e., it does not change state when its corresponding binary code bit makes a transition from the second level to the first level).

A switched-capacitor multiplier/divider with digital and analog outputs

Abstract: A novel switched-capacitor circuit is proposed for digital multiplication and division. The inputs (two binary numbers) are first converted to analog charges by means of binary-weighted capacitor arrays. Then, multiplication or division is performed between these charges to provide the product or ratio in the form of an analog voltage. Finally, the resulting analog voltage is converted to a binary number by successiveapproximation analog-to-digital (A/D) conversion. An error analysis using the charge conservation equation has shown that a 10-bit accuracy is obtainable using this technique with presently available MOS technology. An experimental circuit was built and tested. The results confirmed the principles of operation.

Complex multiplier for binary two's complement numbers

Abstract: A method and apparatus for multiplying two digital pairings representing complex numbers is described. The method includes preloading a memory with contents based on the second complex combination and the basis vector, and repeatedly addressing the memory based on the first complex combination taken L bits at a time in order to accumulate a complex product combination. The complex multiplication apparatus is preferably constructed as high speed circuitry on a gallium arsenide integrated circuit chip.

Digital synthesis technique for pulses having predetermined time and frequency domain characteristics

Abstract: A digital synthesis technique provides pulse shaping in accordance with predetermined time domain and frequency domain constraints. In the technique, the informational content of a binary bit stream is used by an access circuit (12) to form address words for accessing a read-only-memory (13). The digital representations stored in the ROM (13) represent a superposition of temporally-displaced truncated impulse time functions, each weighted by the discrete transmission symbol levels of the analog output signal. The digital representations from two ROMs (13-1 and 13-2) are toggled by a sequencing circuit. In other embodiments of the invention, different memory arrangements ranging from a single ROM (142) to an array of ROMS (163-1 through 163-3 and 164-1 through 164-3) are respectively used to decrease circuit complexity. In a digital radio transmission application of the technique, this arrangement is economical, readily reproducible and stable since it obviates the need for conventional complex analog filters.

Residue Number System Truth-Table Look-Up Processing—Moduli Selection and Logical Minimization

Abstract: Truth table look-up processing using binary coded residue numbers is investigated for full-precision addition and multiplication for implementations using either electronic or optical technologies. The logically minimized numbers of input combinations needed for each operation are presented for moduli 2-23. The moduli sets that require the minimum number of reference patterns are determined for addition and multiplication of 4, 8, 12, and 16 bit words.

A generalization of the near-optimum binary coherent state receiver concept (Corresp.)

Abstract: The structure of a maximum {\em a posteriori} decoder is derived for binary optical fields processed according to Kennedy's near-optimum scheme, but operating in the presence of random optical phase-error and interfering background fields. An exact expression is found for the error probability, and examples to illustrate decoder performance under various operating conditions of interest are provided.

Residue to analog converter

Abstract: A residue to analog converter associated with residue numbers {m1,m2,m3} of the residue number system defined by the moduli set {p1=2 n -1, p2=2 n , p3=2 n +1} and which does not require memory comprises five standard binary adder circuits, apparatus for performing multiplication by bit shifting, and a modulo p1 p3 adder circuit. First and second binary adders combine the residue signals m1 and m3 to produce sum and difference signals which are bit shifted by grounding 2n-1 and n-1 lines, respectively, and locating them as less significant bit lines ahead of these sum and difference signal lines. A modulo p1*p3 adder sums these bit shifted signals. A third binary adder, which ignores overflow, performs a modulo p2=2 n subtraction of m2 from the n less significant bits of the modulo p1*p3 sum signal to produce a second difference signal. This second difference signal is bit shifted by 2n grounded lines that are connected as less significant bit lines ahead of this signal, and then subtracted from this bit shifted signal in a fourth binary adder to produce a correction signal. The modulo p1*p3 sum signal and the correction signal are summed in a fifth binary adder to produce a three dimensional binary signal r(m1,m2,m3) that is representative of a residue signal {m1,m2,m3}. The corresponding analog signal is produced with a standard D/A converter. Structure for implementing the modulo p1*p3 adder circuit with adders that are all standard binary adders is disclosed.

Ripple-borrow binary subtraction circuit

Abstract: A binary subtracter stage for subtracting single bit binary numbers includes a first exclusive OR gate to which the numbers to be subtracted are applied. The output of the exclusive OR gate is connected to one input of a second exclusive OR gate which has a second input connected to a borrow input signal. The output of the second exclusive OR gate provides the difference between the single bit binary numbers. A borrow output signal is generated with the combination of a pass transistor coupled between the borrow input and borrow output terminals and a three state logic circuit which has its output termial connected to the borrow output terminal. The pass transistor is controlled by the output of the first exclusive OR gate and the three state logic circuit is controlled by the single bit binary numbers to be subtracted.

Method of residue to analog conversion

Abstract: In a residue number system defined by the moduli set {p1=2n -1, p2=2n, p3=2n +1}, a method of converting residue numbers {m1,m2,m3} to associated analog signals r(m1,m2,m3) comprises the steps of selecting a first binary signal satisfying the relationships |m1*S3+m3*S1|p1*p3 (where the constant S1=p1*p2/2 and S3=p2*p3/2) from a first look-up table; and summing the n less significant bits of this first digital signal and the negative of the residue digit signal m2 in a first binary adder for generating a second binary signal that is representative of the difference therebetween, taken modulo p2. This second binary signal addresses a second look-up table containing third binary signals which correspond to possible values of the product of the second binary signal and p1 and p3. Selected first and third binary signals are summed in a second binary adder for producing a binary output signal r(m1,m2,m3) that is representative of the residue number {m1,m2,m3}. This binary output signal is converted to a corresponding analog signal in a standard D/A converter. In an alternate method, 2n binary 0's are stuffed as less significant bits of the second binary signal prior to subtracting the latter from this bit shifted signal for producing the third binary signal. In yet another method, the first binary signal is obtained by selecting the binary signals m1*S3 and m3*S1 from associated look-up tables prior to summing them modulo p1*p3.

Log and antilog functions for video baseband processing

Abstract: The log encoder includes means for determining a number r corresponding to the position of the most significant one in the respective input samples, and generating an equivalent binary value To the binary value is added a predetermined value when the input samples are non-zero to generate m-bit binary values representing the m most significant bits of the output samples in the log domain The log encoder further includes means for generating l-bit binary values corresponding to the bits to the right of the most significant one in the input samples The m-bit binary values are concatenated with the l-bit binary values as the most and least significant bits, which concatenated values represent the output samples in the log domain The process is essentially reversed to convert the binary values in the log domain back into the non-log domain

Digital arithmetic unit having shortened processing time and a simplified structure

Abstract: A digital arithmetic unit useful in data processing digital circuits comprises a plurality of stages each having two half-adders combined into a full adder and a carry logic element. An objective is to shorten the processing time for the addition and subtraction of binary numbers. For this purpose, the stages are divided into at least two groups and two separate carry paths are provided within each group. One of the carry paths is only switched on by means of selection logic elements. The activation occurs sequentially in group-wise fashion after simultaneous carry runs in all carry paths. The advantage particularly consists of the chronological coincidence of the carry runs in all groups.

Digital phase-locked loop for synchronisation on reception of binary signals

Abstract: On the basis of known DPLL circuits (Digital Phase-locked loop), comprising a cycle counter (Z), a phase detector (ECPD), a forward/backward counter (VRZ) and a control circuit (I/D) connected in front of the cycle counter (Z) for insertion or extraction of one of the clock pulses for the cycle counter (Z) so that the latter is incremented in accelerated or delayed fashion and a phase correction thereby effected, the direct evaluation of binary data signals with varying frequencies is possible due to an additional bistable trigger circuit (BK) and a novel combination of the alternating input and output signals (DAT and SYN-T) to control the forward/backward counter (VRZ) so that, using simple means, binary data signals with different coding can be directly evaluated. (FIG.1)

Binary digital processor

Abstract: A binary digital microprocessor is arranged to perform rotations and additions on complex input variables A + jB by means of binary shifts and additions. The functions cos 0/ and sin 0/ are appromimated by the functions C(m) and S(m) respectively, where, C(m) = 1-2 -(2m+1) and S(m) = 2-m, to achieve rotation by an angle 0/ = tan-1 S(m)/C(m). The input variables may correspond to the exponential terms of a discrete Fourier transform, and the microprocessor may therefore be used for frequency analysis.

Binary search trees with binary comparison cost

Abstract: We introduce a new variant of the cost measure usually associated with binary search trees. This cost measure BCOST, results from the observation that during a search, a decision to branch left need require only one binary comparison, whereas branching right or not branching at all requires two binary comparisons. This is in contrast with the standard cost measure TCOST, which assumes an equal number of comparisons is required for each of the three possible actions. With BCOST in mind we re-examine its effect with respect to minimal and maximal BCOST trees, minimal and maximal BCOST-height trees, and introduce a class of BCOST-height balanced trees, which have a logarithmically maintainable stratified subclass. Finally, a number of other issues are briefly touched upon.

Jackpot-resistant magnetic card encoding

Abstract: A method of magnetic encoding of credit instruments having a strip form magnetic recording medium provides at least one data field on the strip. First and second magnetic field orientations are selected for recordation on the medium of successive, adjacent bit regions in an alternating field orientation pattern with the transition between such orientations defining the transition from one bit region to the next, signalling the initiation of a recorded bit representing either a binary "1" or a binary "0". A first bit region length d1 for representing one of the binary values "0" and a second bit region length d2 for representing the other binary value as well as the ratio of d1 /d2 are selected, with d1 /d2 being from about 0.1 to about 0.5. Thus, the magnetic field transition between adjacent bit regions signals a binary bit and the length of each bit region represents its binary value. Data is recorded in binary format on the medium in one or more data fields using the bit length d1 and d2 and ratio d1 /d2 so selected. The length of the data fields depends upon the actual value of the data so recorded. The variable data field length assures against jackpotting by unauthorized masking of one of multiple data fields.

Memory versus error trade-offs in binary-valued retrieval problems

Abstract: Question-answering systems have been studied from the viewpoint of achieving drastic savings of storage with a small error tolerance. A system is called elastic if a drastic memory saving may be achieved by tolerating a low level of indefiniteness of the answer. A necessary condition for the system to be elastic is that the query sets exhibit diverging redundancy. In the binary-valued retrieval problems discussed by P. Elias and R.A. Flower (1975), a system that admits the set of all binary questions regarding an arbitrary binary data with the highest redundance has been shown to be inelastic. On the other hand, a system that admits the exact match question set regarding an arbitrary binary data with the second highest redundancy is found to be elastic.

System for deciding and processing binary/multi-value picture area

Abstract: PURPOSE:To offer a processing system of high speed specification exceeding the performance of an exclusive processor by performing the discriminating processing of binary/multi-value picture area by a local vicinity arithmetic exclusive processor for multi-value picture and by an external discriminating circuit, to realize easily the discrimination of the binary/multi-value picture area. CONSTITUTION:In the figure, 20-20' and 23-23' constitute a processing image buffer 24 having hour sets of 4-bit width as an alternate buffer form. 25-25''' are processors and they are controlled to obtain a maximum and a minimum value respectively, and a picture data for 4 picture elements' share of each scanning line is applied in parallel from the image buffer. The result of arithmetic is transferred among the processors via each linkage unit respectivey, and the maximum value and the minimum value in 4X4 picture elements are outputted as an output of the processor 25''' of the 4th stage. After the maximum value is latched once in a register 26, the difference with the minimum value outputted in the next timing is used at an arithmetic circuit 27 and the result is compared with a threshold value Po for binary/multi-value decision at an arithmetic circuit 28, allowing to obtain a command signal for separating the binary/ multi-value picture area.

Electronic device for the execution of a mathematical operation on sets of three digital variables

Abstract: A device is described for electronically executing a mathematical operation, being Z=KA+(1-K)B. It is also described how this device or how several of such devices can be used for the design of a number of realizations, such as a recursive filter, a digital mixer etc. The basic idea is the electronic implementation of a mathematical function for binary variables.