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Showing papers on "Binary number published in 1985"



StandardDOI
John E. May, John P. Riganati, Sava I. Sherr, James H. Beall, Fletcher J. Buckley, Rene Castenschiold, Edward Chelotti, Edward J. Cohen, Paul G. Cummings, Donald C. Fleckenstein, Jay Forster, Daniel L. Goldberg, Kenneth D. Hendrix, Irvin N. Howell, Jack Kinn, Joseph L. Koepfinger, Irving Kolodny, R. F. Lawrence, Lawrence V. McCall, Donald T. Michael, Frank L. Rose, Clifford O. Swanson, J. Richard Weger, W. B. Wilkens, Charles J. Wylie, Andrew Allison, William Ames, Mike Arya, Janis Baron, Steve Baumel, Dileep Bhandarkar, Joel Boney, E. H. Bristol, Werner Buchholz, Jim Bunch, Ed Burdick, Gary R. Burke, Paul Clemente, W. J. Cody, Jerome T. Coonen, Jim Crapuchettes, Itzhak Davidesko, Wayne Davison, R. H. Delp, James Demmel, Donn Denman, Alvin Despain, Augustin A. Dubrulle, Tom Eggers, Philip J. Faillace, Richard Fateman, David Feign, Don Feinberg, Smart Feldman, Eugene Fisher, Paul F. Flanagan, Gordon Force, Lloyd Fosdick, Robert Fraley, Howard Fullmer, Daniel D. Gajski, C. W. Gear, Martin Graham, David Gustavson, Guy K. Haas, Kenton Hanson, Chuck Hastings, David Hough, John E. Howe, Thomas E. Hull, Suren Irukulla, Richard, Paul S. Jensen, W. Kahan, Howard Kaikow, Richard Karpinski, Virginia Klema, Les Kohn, Dan Kuyper, M. Dundee Maples, Roy Martin, William H. McAllister, Colin McMaster, Dean Miller, Webb Miller, John C. Nash, Dan O 'Dowd, Cash Olsen, A. Padegs, John F. Palmer, Beresford Parlett, Dave Patterson, Mary H. Payne, Tom Pittman, Lew Randall, Robert Reid, Christian Reinsch, Frederic N. Ris, Stan Schmidt, Van Shahan, Robert L. Smith, Roger Stafford, G. W. Stewart, Robert Stewart, Harold S. Stone, W. D. Strecker, Robert Swarz, George Taylor, James W. Thomas, Dar-Sun Tsien, Greg Walker, John S. Walther, Shlomo Waser, P. C. Waterman, Charles White 
01 Jan 1985

119 citations


Book ChapterDOI
23 Aug 1985
TL;DR: A CMOS digital LSI device which generates a random bit stream based on the frequency instability of a free running oscillator and the output is a truly random binary number; not pseudo random.
Abstract: This paper describes a CMOS digital LSI device which generates a random bit stream based on the frequency instability of a free running oscillator. The output of the device is a truly random binary number; not pseudo random.

89 citations


Journal ArticleDOI
TL;DR: Two binary algorithms for the square rooting of a number or of a sum of two numbers are presented, based on the classical nonrestoring method, with the main difference in the replacement of subtractions and additions by a parallel reduction of three summands.
Abstract: Two binary algorithms for the square rooting of a number or of a sum of two numbers are presented. They are based on the classical nonrestoring method. The main difference lies in the replacement of subtractions and additions by a parallel reduction f three summands, which may be positive and negative, to two summands to eliminate the carry propagation. Two of three summands form the successive partial remainder. Their most significant bit triples, sometimes together with a sign bit of the earlier partial remainder, are used to determine digits -1,0, +1 of a redundant square-root notation. These digits are transformed during the square-rooting process into the conventional notation square-root bits which are next used in further square-rooting steps to form the third reduced summands.

68 citations


Patent
Stephen N. Levine1
30 Aug 1985
TL;DR: In this paper, a decoding system and method for a radiotelephone system carrying digital messages is described. But the decoding scheme is based on normal or inverse words as binary levels when fewer than a predetermined number of bit errors exist in the bit sequence.
Abstract: A decoding system and method is disclosed for a radiotelephone system carrying digital messages. A set of multibit high auto-correlation, low cross-correlation synchronization words and their ones complement inverses are employed for message synchronization and supervisory functions. System state communication is achieved by utilizing a sequence of normal synchronization words and their ones complement inverses. Reliability of the coding is achieved by detecting normal or inverse words as binary levels when fewer than a predetermined number of bit errors exist in the bit sequence. If the predetermined number of bit errors is exceeded, a selected binary one or zero is substituted. This selected sequence of binary levels is decoded and the Hamming distance between a masked decoded sequence and a masked selected sequence is calculated. If the Hamming distance calculated yields a number less than or equal to a number equal to the synchronization error correction capability of the coding function, the decoded sequence is accepted as correct. If the Hamming distance calculation yields a number greater than the error correction capability value, a new set of substituted binary levels is tried.

51 citations


Journal ArticleDOI
TL;DR: Analysis of retrieval considerations associated with the binary matrix indicate that the binary data base's efficiency increases with increases in query complexity.
Abstract: A binary approach to data storage and retrieval is introduced. It views the data base as a two-dimensional matrix that relates entities to all possible values the attributes of these entities may take. As such, it provides a unified solution to the two conflicting types of data base transactions—operational and managerial. An analytical investigation of the feasibility of binary storage and a compression method for reducing meaningless areas of the matrix are presented. Storage efficiencies of binary and conventional inverted file methods are compared and evaluated. An analysis of retrieval considerations associated with the binary matrix is given, particularly the issue of going from high to low orders of compression. Results of these analyses indicate that the binary data base's efficiency increases with increases in query complexity. Future research directions are sited and discussed.

45 citations


Journal ArticleDOI
TL;DR: In this paper, a method for the definition and description of structures, sets of visible elements in a binary digital image, is presented for the extraction, analysis, and manipulation of structures and is based on a numerical code which synthesizes the description of an element in its 8-neighborhood.
Abstract: A method is presented for the definition and description of structures, that is, sets of visible elements in a binary digital image. The method is designed so as to facilitate the extraction, analysis, and manipulation of structures and is based on a numerical code which synthesizes the description of an element in its 8-neighborhood. Taxonomies of features and structures are derived and discussed. The exploitation of APL typical “many-words-at-a-time” computing notation allows us to show how every defined structure may be derived and described by the use of simple techniques of parallel selection and sorting. The same techniques are used in the definition of a parallel algorithm which identifies the descriptions of the connected components and assigns them intrinsic labels by establishing relations of surroundedness. The inverse parallel algorithm, which displays the binary image corresponding to a given description, is thereafter described. The method has been tested in different practical experiments. Hints are then given on strategies which were originated using the method in practical experiments.

41 citations


Patent
02 Jul 1985
TL;DR: In this paper, a logarithmic converting apparatus for converting a digital binary integer into a digital integer representation and for converting it into digital binary representation was presented, where the bit position of a leading non-zero bit of an integer was determined by a look-up table.
Abstract: A logarithmic converting apparatus for converting a digital binary integer into logarithmic representation and for converting logarithmic representation into digital binary integer is disclosed. The apparatus determines the bit position of a leading non-zero bit of an integer, shifts the integer such that the leading non-zero bit is the leftmost bit. A look-up table receives the shifted integer and provides a number representative of the mantissa portion of the logarithm of the shifted number. An encoder receives a Point Set Input value, a scale value for said integer, and the number of binary positions shifted and generates the exponential portion of the logarithm of the integer. For converting logarithmic representation of a number into integer representation, the apparatus has a look-up table which receives the mantissa component of the logarithmic representation and provides a first number. A decoder receives the exponential component of the logarithmic representation and a Point Set Output value, a scale value for said integer, and supplies a shifted signal. The shifted signal is supplied to a shifter along with the first number and the shifter shifts the first number by the shift signal to produce the integer.

36 citations


Journal ArticleDOI
TL;DR: An algorithm and its hardware implementation which converts the 3 moduli (2 n - 1, 2 n + 1) residue numbers into their binary representation, which enables an extremely wide, fixed-point dynamic range, since its upper bound is not limited by a memory size.
Abstract: This paper describes an algorithm and its hardware implementation which converts the 3 moduli (2^{n} - 1,2^{n}, 2^{n} + 1) residue numbers into their binary representation. The given technique requires only binary adders, and no look-up tables. antages of this approach are two-fold: 1) It enables an extremely wide, fixed-point dynamic range, since its upper bound is not limited by a memory size. 2) The Integrated Circuit area required for its realization can be directly traded off with conversion speed. As a result, a 66-bit convertor with a conversion time of 120 ns, or a 36-bit one with 40 ns, may be implemented as single CMOS chips with 3 \mu m geometries.

31 citations


Patent
Nukiyama Tomoji1
19 Aug 1985
TL;DR: In this paper, a high speed digital arithmetic unit comprises a plurality of binary adders in cascade arrangement, each binary adder comprising carry lookahead means for generating a carry signal representative of an actual carry bit based on a segment of a first binary number, a corresponding segment of the second binary number and fed from an adder located at a lower position.
Abstract: For reduction in circuit complexity, there is disclosed a high speed digital arithmetic unit comprises a plurality of binary adders in cascade arrangement, each binary adder comprising carry lookahead means for generating a carry signal representative of an actual carry bit based on a segment of a first binary number, a corresponding segment of a second binary number and a carry signal fed from an adder located at a lower position, adding means for adding the segment of the first binary number to the corresponding segment of the second binary number in parallel operation with the carry lookahead means, the adding means simultaneously adding a suspense carry to a partial sum of the segments for generation of a temporary result, and final result determination means operative to generate a final result based on the partial sum in accordance with the actual carry fed from the lower adder.

21 citations


Proceedings ArticleDOI
04 Jun 1985
TL;DR: The problem of designing squarers for binary number in serial form (with the condition of the least possible delay between input and output) is treated and some of such multipliers offer a considerable saving in components when they are reduced to squarers.
Abstract: The problem of designing squarers for binary number in serial form (with the condition of the least possible delay between input and output) is treated. Several schemes are Illustrated, derived from fast multipliers for binary numbers in serial form, described in a previous paper. It is shown that some of such multipliers offer a considerable saving in components when they are reduced to squarers. Some schemes are illustrated, both for positive and for two's-complement numbers.

PatentDOI
TL;DR: An optical processor suitable for matrix-vector multiplication is described in this paper, where coherent light passes through an acousto-optic cell modulated by the elements in the rows of the matrix.

Patent
15 Oct 1985
TL;DR: In this article, a system for continuously linearly interpolating intermediary binary numbers operates to coordinate the transfer of binary numbers to a binary averager so as to provide output binary numbers equal to the average value of the input binary numbers during first and second time intervals.
Abstract: A system for continuously linearly interpolating intermediary binary numbers operates to coordinate the transfer of binary numbers to a binary averager so as to provide output binary numbers equal to the average value of the input binary numbers during first and second time intervals wherein the average values provided during the second time intervals correspond to interpolated intermediary binary numbers.

Patent
29 Jan 1985
TL;DR: In this article, a coder-decoder device for OQPSK signals with four phase states was proposed, which consists of a first logic circuit for assigning to each bit of the bit stream X n the binary value 1 or 0 in accordance with the logic equation X.sub.n =T.subn *+H.n/2.
Abstract: A coder-decoder device for OQPSK signals with four phase states comprises a coder for converting a binary signal bit stream T n into two digital bit streams X n and Y n and a decoder for restoring the digital bit stream T n from the digital bit streams X n and Y n applied to its inputs. The coder comprises a first logic circuit for assigning to each bit of the bit stream X n the binary value 1 or 0 in accordance with the logic equation X.sub.n =(T.sub.n *+H.sub.n /2)*⊕X.sub.n-1 where H n /2 designates synchronization pulses in phase with the bits of the bit stream T n . A second logic circuit assigns to each bit of the bit stream Y n the binary value 1 or 0 in accordance with the logic equation Y.sub.n =T.sub.n ⊕X.sub.n ⊕X.sub.n-1 ⊕Y.sub.n-1. The decoder comprises a third logic circuit which assigns to each bit of the restored bit stream T n the binary value in accordance with the following logic equation: T.sub.n =X.sub.n ⊕X.sub.n-1 ⊕Y.sub.n ⊕Y.sub.n-1.

Patent
18 Jan 1985
TL;DR: In this article, a circuit for operating finite fields performs multiplication or division using an accumulator for storing an arbitrary element and an adder for performing modulo 2 addition, using the contents of the accumulator and a vector representation of the primitive polynomial, with a binary arithmetic unit for performing addition or subtraction using such exponents.
Abstract: A circuit for operating finite fields performs multiplication or division using an accumulator for storing an arbitrary element and an adder for performing modulo 2 addition, using the contents of the accumulator and a vector representation of the primitive polynomial; or first and second tables for translating exponents with elements of the polynomial over the finite field, with a binary arithmetic unit for performing addition or subtraction using such exponents.

Patent
31 Dec 1985
TL;DR: A 3-by-3 convolver as mentioned in this paper utilizes 9 binary arithmetic units (10) connected in cascade for multiplying 12-bit binary pixel values p i which are positive or two's complement binary numbers by 5-bit magnitude (plus sign) weights w i which may be positive or negative.
Abstract: A 3-by-3 convolver utilizes 9 binary arithmetic units (10) connected in cascade for multiplying 12-bit binary pixel values p i which are positive or two's complement binary numbers by 5-bit magnitude (plus sign) weights w i which may be positive or negative. The weights are stored in registers (13, 14 and 15) including the sign bits (shown separately for convenience). For a negative weight, the one's complement of the pixel value to be multiplied is formed at each unit by a bank of exclusive OR gates under control of the sign of the corresponding weight w i , and a correction is made by adding the sum of the absolute values of all the negative weights for each 3×3 kernel. Since this correction value remains constant as long as the weights are constant, it can be precomputed and stored in a register (16) as a value to be added to the product PW of the first arithmetic unit.

Journal ArticleDOI
TL;DR: In this article, a generalized theory of ordered binary alloys is derived from a pair interaction model, which is applicable for arbitrary alloy structures with any given number of long and short-range parameters and also for all possible numbers of interaction potentials and component concentrations.
Abstract: Starting from a pair interaction model a generalized theory of ordered binary alloys is derived. Such approach is applicable for arbitrary alloy structures with any given number of long- and short-range parameters and also for all possible numbers of interaction potentials and component concentrations. On the base of pair correlation functions a new definition of short-range ordering parameters is proposed. Some explicit forms of correlation functions above critical temperature Tc are obtained. The computed results are compared with experimental data for the case of β-brass. With the accuracy to third-order perturbation theory, interactions and ordering in 13 coordination shells are considered. [Russian text ignored].

Patent
27 Nov 1985
TL;DR: In this paper, a three-channel binary coding technique was proposed for identifying intermittently, erratically, or continuously moving objects along a linear path (conveyor track, roadway, or the like).
Abstract: A three channel, binary coding technique, especially adapted for identifying intermittently, erratically, or continuously moving objects along a linear path (conveyor track, roadway, or the like). Three parallel channels of coded information are each provided with some type of photoelectric, electronic, or mechanical indicating means or indicia representative of one of two logic states, which logic states on each channel change during each successive segment or interval thereon. A change in the timing channel indicates to a sensing means that a new binary bit of intelligence is to be transmitted. The order in which the coding channels change during the succeeding segment then indicate whether the binary bit being generated is a ONE, a ZERO, or in the alternative whether the reading is erroneous or invalid.

Proceedings ArticleDOI
04 Jun 1985
TL;DR: The MaxSD number system has the highest redundancy within the carry-absorbing signed-digit number system proposed by Avizienis in 1961 and is an excellent choice far multiprecision arithmetic on binary machines.
Abstract: The maximal redundancy signed-digit (MAXSD) number system has the highest redundancy within the carry-absorbing signed-digit number system proposed by Avizienis in 1961. The digital values for radix R lie in [1-R, R-1]. Its compatibility with both standard nonredundant systems and binary arithmetic makes it an excellent choice far multiprecision arithmetic on binary machines. The representations for finite numbers are however nonunique and can even be unbounded in wordlength; this is resolved by algorithms for partial or complete conversion to standard nonredundant notation without explicit carry propagation.

Journal ArticleDOI
TL;DR: The basis for a new method of type synthesis of spatial mechanisms with the use of single-loop structural groups having zero degrees of freedom is described, which can be programmed for digital computation and applied towards the automatic type synthesis in the design of spatial mechanism.

Patent
18 Feb 1985
TL;DR: In this paper, a method and a machine for checking the legality of issue of a bank or postal cheque with a view to allowing the payee to detect a stolen cheque was presented.
Abstract: The invention relates to a method and a machine for checking the legality of issue of a bank or postal cheque with a view to allowing the payee to detect a stolen cheque The machine comprises a microprocessor ( mu P), means for acquiring the account number inscribed on the cheque (MG), means for conversion into binary ( mu P), logic calculation means (CAL) adapted to make the foregoing set of holder account numbers in a binary base correspond to the image set of the binary numbers with at most 14 bits, a decimal input system (CL) for insertion of a confidential four-number decimal code, means of conversion of the code into binary base (CV), means of temporary memory storage for the said code (RAM), logic means (COMP) for comparison of the result issued by the calculating means and of the memory-stored binary base code, and warning means AFF; SON; LA3; LA4 for interpreting the results of the comparison in a simple form

Journal ArticleDOI
TL;DR: It is shown that, in the worst case, the delay necessary to permute boolean variables on a star-connected network of n binary automata is $n - 1$.
Abstract: In this paper it is shown that, in the worst case, the delay necessary to permute boolean variables on a star-connected network of n binary automata is $n - 1$.

Patent
24 Jan 1985
TL;DR: In this paper, the authors propose to shorten the arithmetic time and reduce the quantity of hardware by calculating after separating high-order (M-N) bits in case it is known that the low-order N bits as one side are 0 among two M-bit binary inputs.
Abstract: PURPOSE:To shorten the arithmetic time and to reduce the quantity of hardware by calculating after separating high-order (M-N) bits in case it is known that the low-order N bits as one side are 0 among two M-bit binary inputs. CONSTITUTION:Binary numbers Y1, X1 and X2 are fed to an absolute value arithmetic circuit 300 containing auxiliary input to produce a full-bit OR C1 of the X2. A decision signal C0 satisfying X1+C1 Y1 is satisfied. While Y1-X1-C1 is calculated in the case of X1+C1<=Y1. Thus the binary numbers Z1 of the result of calculation, i.e., the absolute value of the difference between upper bits of X and Y is delivered. A complement generating circuit 310 delivers the complement X3 of X2 to the circuit 320, and the circuit 320 supplies X2 and X3 and the signal C0 to select the X2 or its complement X3 in accordance with 1 or 0 of the signal C0. This selected X2 or X3 is delivered as a binary number Z2 which means the absolute value of the difference between low-order bits of X and Y.

Journal ArticleDOI
TL;DR: This correspondence shows a method for determining the ternary delta sequence of the third of the sum of two analog signals through their corresponding delta sequences.
Abstract: This correspondence shows a method for determining the ternary delta sequence of the third of the sum of two analog signals through their corresponding delta sequences. The hardware implementation proposed here is modular employing a universal logic T-gate which allows building both sequential and combinatorial circuits. The primary advantage of a ternary nonredundant symmetric presentation of the TDM over a binary DM presentation is the reduction of problems of carry propagation in arithemetic operation and reduction in connections and interconnections between chips and interchips.

Patent
Dwight W. Grimes1
01 Oct 1985
TL;DR: In this paper, a trinary logic transmission channel is used to transfer data from a first binary logic circuit to a second binary logic circuits by using the trinary transceiver, which is located on the second binary circuit and is connected to the transmission channel.
Abstract: 57 A communications interface for transferring data from a first binary logic circuit (11) to a second binary logic circuit (12) by using a trinary logic transmission channel. The first set of binary logic signals is converted into a first set of binary control signals which, in turn, control trinary drivers (18) connected to the transmission channel. The trinary drivers drive the transmission channel to one of three discrete voltage levels as opposed to one of two levels in binary systems. Trinary receivers (21) are located on the second binary logic circuit and are connected to the trinary transmission channel. The receivers produce a second set of binary control signals which are translated into a second set of binary logic signals for use by the second binary logic circuit.

Journal ArticleDOI
TL;DR: The principle of binary coding is employed for the formulation of various multiple-choice situations and on the basis of a given coding matrix it is possible to find powerful constraints which define the binary coding procedure within an LP model.

Patent
21 Mar 1985
TL;DR: In this paper, a process for the parallel transmission of binary digital signals over the channels of a frequency division multiplex is described, where the bandwidth utilisation of the channels is doubled by combining in each case two bits of the information to be transmitted to form a new quaternary code element having four possible characteristic states.
Abstract: A process for the parallel transmission of binary digital signals over the channels of a frequency division multiplex is described. The band-width utilisation of the channels is doubled by combining in each case two bits of the information to be transmitted to form a new quaternary code element having four possible characteristic states. The quaternary code element is equalised and shaped on the receiving side by a Nyquist filter (N) and an all-pass filter (A).

Patent
06 Dec 1985
TL;DR: In this article, a vital processor is implemented using non-vital hardware in the form of a digital computer which may for example be a microprocessor, and the vital processor accepts binary input values and determines the appropriate output values based on a series of logical expressions relating output values to input values.
Abstract: A method and apparatus for effecting vital functions notwithstanding the fact that non-vital hardware is employed. A vital processor is implemented using non-vital hardware in the form of a digital computer which may for example be a microprocessor. The vital processor accepts binary input values and, based on a series of logical expressions relating output values to input values, determines the appropriate output values. Rather than employing a single bit to represent the condition of a particular input or output, unique multibit binary values or names are used. Each input or output has assigned to it at least two unique multibit values, each satisfying the code rules of a different code. Thus rather than representing a closed contact as a single 1 bit, and an open contact as a single 0 bit, the closed contact is represented by a unique multibit name which satisfies the code rules of a first code. At any point in the processing the value representing the contact can be checked to see if it satisfies the code rules, and if it does not a potential error is detected and handled. Although it is highly unlikely that a hardware failure would result in generating one of the few multibit names satisfying the code rule, that occurrence is not unlikely enough to be considered vital. Before actually controlling output devices in accordance with the processing, further tests are implemented which ensure that the multibit value computed for a particular output not only satisfies the predetermined code rule which is required, but is also correct bit for bit. Logic equations describing the relationship between output and input are actually computed using the multibit values as opposed to single bit values.

Patent
10 Dec 1985
TL;DR: In this paper, a binary subtracter stage for subtracting single bit binary numbers includes a first exclusive OR gate (18) to which the numbers to be subtracted are applied, and the output of the exclusive gate is connected to one input of a second exclusive gate (20) which has a second input connected to a borrow input signal (10).
Abstract: A binary subtracter stage for subtracting single bit binary numbers includes a first exclusive OR gate (18) to which the numbers to be subtracted are applied. The output of the exclusive OR gate is connected to one input of a second exclusive OR gate (20) which has a second input connected to a borrow input signal (10). The output of the second exclusive OR gate provides the difference between the single bit binary numbers. A borrow output signal (32) is generated with the combination of a pass transistor (22) coupled between the borrow input and borrow output terminals and a three state logic circuit (24, 26. 28, 30) which has its output terminal connected to the borrow output terminal. The pass transistor is controlled by the output of the first exclusive OR gate and the three state logic circuit is controlled by the single bit binary numbers to be subtracted.