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Showing papers on "Binary number published in 1987"


Journal ArticleDOI
TL;DR: A 16-bit/spl times/16-bit multiplier for 2 two's-complement binary numbers based on a new algorithm is described, characterized by use of a binary tree of redundant binary adders.
Abstract: A 16-bit /spl times/ 16-bit multiplier for 2 two's-complement binary numbers based on a new algorithm is described. This multiplier has been fabricated on an LSI chip using a standard n-E/D MOS process technology with a 2.7-/spl mu/m design rule. This multiplier is characterized by use of a binary tree of redundant binary adders. In the new algorithm, n-bit multiplication is performed in a time proportional to log/SUB 2/ n and the physical design of the multiplier is constructed of a regular cellular array. This new algorithm has been proposed by N. Takagi et al. (1982, 1983). The 16-bit/spl times/16-bit multiplier chip size is 5.8 /spl times/ 6.3 mm/SUP 2/ using the new layout for a binary adder tree. The chip contains about 10600 transistors, and the longest logic path includes 46 gates. The multiplication time was measured as 120 ns. It is estimated that a 32-bit /spl times/ 32-bit multiplication time is about 140 ns.

154 citations


Journal ArticleDOI
15 Aug 1987-EPL
TL;DR: A model which self-organizes to perform a task via a learning-by-example scheme which is a network of Boolean operators which has been able to achieve an error-free design for addition between integer binary numbers when shown only a small subset of all possible additions.
Abstract: We realized a model which self-organizes to perform a task via a learning-by-example scheme. The system is a network of Boolean operators which, in some of our computations, has been able to achieve an error-free design for addition between integer binary numbers when shown only a small subset of all possible additions. The training procedure, based on optimizing the network on the given sampling using simulated annealing, is completely general and allows in principle to treat any binary mapping. We recognize different regimes in learning, i.e. the system can both memorize patterns (with a capacity which is numerically estimated) and generalize information to construct rules and algorithms. Some scaling relations are conjectured and numerically tested for these different regimes.

71 citations


Proceedings ArticleDOI
18 May 1987
TL;DR: An algorithm to implement radix four division andRadix four square-root in a shared hardware for IEEE standard for binary floating point format will be described, and extending the algorithm to radix eight or higher division/square-root will be discussed.
Abstract: An algorithm to implement radix four division and radix four square-root in a shared hardware for IEEE standard for binary floating point format will be described. The algorithm is best suited to be implemented in either off-the-shelf components or being a portion of a VLSI floating-point chip. Division and square-root bits are generated by a non-restoring method while keeping the partial remainder, partial radicand, quotient and root all in redundant forms. The core iteration involves a 8-bit carry look-ahead adder, a multiplexer to convert two's complement to sign magnitude, a 19-term next quotient/root prediction PLA, a divisor/root multiple selector, and a carry save adder. At the end, two iterations of carry look-ahead adder across the length of the mantissa are required to generate the quotient/root in a correctly rounded form. Despite its simplicity in the hardware requirement, the algorithm takes only about 30 cycles to compute double precision division or square-root. Finally, extending the algorithm to radix eight or higher division/square-root will be discussed.

68 citations


Patent
26 Nov 1987
TL;DR: A combined binary and binary coded decimal (BCD) arithmetic logic unit (ALU) having a binary ALU adapted to perform decimal operations on BCD data without impacting the performance of binary operations is described in this paper.
Abstract: A combined binary and binary coded decimal (BCD) arithmetic logic unit (ALU) having a binary ALU adapted to perform decimal operations on BCD data without impacting the performance of binary operations. Said combined binary and BCD ALU comprises a look-ahead carry binary ALU for generating the binary sum or logical combination of inputs to the binary ALU to an output (Y), arranged in groups of four bits, and providing carry outputs (Co) of the binary additions from each of the groups of four bits of the Y output; a decimal correction means, responsive to the Y and Ci outputs from the binary ALU means, for correcting the binary sum from the binary ALU means when performing BCD arithmetic, and; a multiplexer for selecting output from the binary ALU means or from the binary ALU means to a result output, wherein the output from the binary ALU means is selected for performing operations on binary data and output from the decimal correction means is selected for performing operations on BCD data.

53 citations


Journal ArticleDOI
TL;DR: Utilization of the final point condition makes the algorithm faster and the flexible deletion of end points produces a line pattern of good quality even for noisy figures.

50 citations


Journal ArticleDOI
Nicholas Pippenger1
TL;DR: The current state of knowledge concerning the computation of Boolean functions by networks, with particular emphasis on the addition and multiplication of binary numbers, is surveyed.
Abstract: We survey the current state of knowledge concerning the computation of Boolean functions by networks, with particular emphasis on the addition and multiplication of binary numbers.

39 citations


Patent
07 Jul 1987
TL;DR: In this paper, an arithmetic processor and an addition/subtraction circuit therefor are disclosed, which comprises a plurality of the addition and subtraction units arranged in parallel, each unit being capable of carrying out addition (or subtraction) with respect to respective digits of two operands.
Abstract: An arithmetic processor and an addition/subtraction circuit therefor are disclosed. The arithmetic processor comprises a plurality of the addition/subtraction units arranged in parallel, each unit being capable of carrying out addition (or subtraction) with respect to respective digits of two operands. An addition/subtraction unit comprises a first circuit and a second circuit coupled to receive binary signals each representing a respective digit of the operands. At least a first of the two binary signals is a 2-bit signal representing a signed digit expression, one bit of which ("the sign bit") represents the sign of one of the digits of the operands and the other bit of which ("the magnitude bit") represents the magnitude of that one digit of the operands. The first circuit provides a binary signal representing an intermediate carry (or borrow) and the second circuit provides a binary signal representing an intermediate sum (or difference) from the two binary signals representing the digits of the operands. The addition/subtraction unit further comprises a third circuit which is coupled to receive the intermediate sum (or difference) binary signal output from the second circuit and a binary signal representing an intermediate carry (or borrow) from a next-lower-order digit, and outputs a 2-bit binary signal representing an addend (or subtrahend). That 2-bit signal output by the third circuit represents a signed digit expression, one bit, i.e., the sign bit, represents the sign of the addend (or subtrahend) and the other bit, i.e., the magnitude bit, represents the magnitude of the addend (or subtrahend).

31 citations


Patent
09 Jan 1987
TL;DR: In this paper, a method and circuit for decoding binary signals processed according to an error correcting convolution code, in which the path metrics are transformed from the arithmetic into the logic range of operation, is presented.
Abstract: A method and circuit for decoding binary signals processed according to an error correcting convolution code, in which the path metrics are transformed from the arithmetic into the logic range of operation. The path metric having the extreme value is subtracted from all other path metrics. All possible binary signal states occurring at the encoder are simulated in real time and are utilized to address hypothetical source data channels. From such a hypothetical source data channel fed by path decision bits, a buffer memory is actualized as well as the simulated binary signal states at the encoder. The output of decoded data from a buffer memory is effected in accordance with their addresses, namely for the extreme value of the path metric. For branching in the trellis diagram, the buffer memories whose associated trellis paths did not survive are overwritten.

30 citations



Journal ArticleDOI
TL;DR: This paper shows the design of a parallel optical adder based on MSD number representation using the method of symbolic substitution originally proposed by Karl-Heinz Brenner and Alan Huang and discusses the use of this adder along with barrel shifters to efficiently implement multiplication.
Abstract: The design of a processor can vary considerably with the type of technology (optical or electronic, analog or digital), the number system, and the coding scheme used for the number representation. Binary number representation is accepted as the best suited for electronic computers. However, the delay due to carry propagation in binary arithmetic makes the binary number representation a very weak candidate for an optical processor that is inherently parallel. The modified signed digit (MSD) number representation satisfies the requirements of totally parallel addition using modular or identical units and allows the addition of any two numbers in three successive steps. In this paper, we show the design of a parallel optical adder based on MSD number representation using the method of symbolic substitution originally proposed by Karl-Heinz Brenner [Appl. Opt. 25(18), 3061-3064 (1986)] and Alan Huang [Proc. IEEE Int. Optical Computing Conf., pp. 13-17 (1983)]. Polarized light is used to code the inputs and outputs. We also discuss the use of this adder along with barrel shifters to efficiently implement multiplication.

23 citations


Patent
17 Apr 1987
TL;DR: The Gray code counter as mentioned in this paper employs modules of binary bits to form expressions or numbers, and the count is sequenced from one expression to the next by changing only one binary bit in one location of an expression.
Abstract: A Gray code counter employs modules of binary bits to form expressions or numbers. The count is sequenced from one expression to the next by changing only one binary bit in one location of an expression. The Gray code counter can be an incrementing counter or an increment/decrement counter. The counter can operate with expressions of several bits, and employs a minimal number of D type flip-flops and logic gates.

Journal ArticleDOI
TL;DR: Some measures for the quantitative description of correspondence relations between binary patterns are proposed and analysed, based upon measures of area for finite grid point sets, and others on distance mappings indicating the minimum distance of a grid point from a given grid point set.

Patent
28 Jul 1987
TL;DR: In this paper, a detector logic circuit was proposed to restore the value 0 or ± 1 of a ternary symbol converted into a signal on five levels 0, ± 1 and ± 2 as a result of class 1, type n=2 partial response transmission.
Abstract: A detector logic circuit restores the value 0 or ±1 of a ternary symbol converted into a signal on five levels 0, ±1 and ±2 as a result of class 1, type n=2 partial response transmission. Employing only binary logic circuits, it is connected to the output of a comparator which has four thresholds and which delivers a value representing the receive level by four binary signals. Two of these signals indicate positive overshooting of extreme and intermediate positive thresholds. The other two indicate negative overshooting of negative extreme and intermediate thresholds. The circuit delivers the values of the ternary symbols detected in the form of two binary components which are available at the output and stored for the duration of a symbol by two flip-flops. Both are generated by combinational logic devices of similar design utilizing OR and NOR gates.


Patent
09 Oct 1987
TL;DR: In this paper, a binary arithmetic unit performs arithmetic operations on binary coded dedicmal (BCD) operands by converting the BCD digits to hexadecimal excess 3 digits, generating hexade cimal excess 6 partial product digits, and modifying selected excess 6 part product digits to generate a BCD result.
Abstract: A binary arithmetic unit performs arithmetic operations on binary coded dedicmal (BCD) operands by converting the BCD digits to hexadecimal excess 3 digits, generating hexadecimal excess 6 partial product digits and modifying selected excess 6 partial product digits to generate a BCD result.

Journal ArticleDOI
TL;DR: The proposed hardware algorithm is a modification of the CORDIC method, and considers gradual rotation of a point on plane orthogonal coordinates about the origin, and is more advantageous as the bit length increases.
Abstract: A hardware algorithm for computing sine and cosine using redundant binary representation for internal computations is proposed. This paper considers the computation of sine and cosine of angle tH (0; 4) (rad). Our hardware algorithm is a modification of the CORDIC method, and considers gradual rotation of a point on plane orthogonal coordinates about the origin. Sinecosine are calculated by iteratively computing coordinates of the point. The sequences of numbers representing X- and Y-coordinates of the point rotated and the remaining angle of rotation are expressed by a redundant binary representation, where each digit of number is an element of {-1, 0, 1}. The direction of rotation at each step is determined based on the upper 3 digits of the remaining angle, and all the internal computations are done in the redundant binary number system. Since parallel addition and subtraction of two numbers by a combinational circuit can be done in a fixed time regardless of the number of digits in the redundant binary number system, the computation for one step can be done in a fixed time. Following this algorithm, n-bit computation of sine-cosine by a combinational circuit can be done in the computation time proportional to n and with the number of elements proportional to n2. Since the computation time proportional to at least n log n is required in the existing hardware algorithm based on the CORDIC method, our algorithm is more advantageous as the bit length increases. Moreover, faster computation can be done with about the same number of elements for practical bit lengths.

Proceedings ArticleDOI
22 Jan 1987
TL;DR: A new triangulation method for range image acquisition is presented, which makes it possible to acquire moving scenes by making each sample point identifiable by means of a binary signature, which is locally shared among its closest neighbours.
Abstract: A new triangulation method for range image acquisition is presented. The scene is illu-minated with a fixed binary coded light pattern. The 64x63 range picture is determined from the information of a single camera image, which makes it possible to acquire moving scenes. The ambiguity inherent in multiple sample triangulation is solved by making each sample point identifiable by means of a binary signature, which is locally shared among its closest neighbours. The applied code is derived from pseudo-noise sequences. Analysis of an illumination-coded image yields the image coordinates of the detected sample points with sub-pixel accuracy, along with their assigned code bit. Exploration of the local topology around each sample retrieves its associated binary signature, by which it is identified. The corresponding spatial coordinates of an identified sample are determined by applying a linear transformation to its image coordinates, the appropriate matrix being selected by the identification result.

Patent
09 Nov 1987
TL;DR: In this article, a video signal processing system is described in which a characteristic of individual picture points is provided to an accuracy of m binary bits but conveyed by n bits, where n is less than m. The value of a lower order bit of the n bit signal is switched to cause, for any one picture point, either a value above or a value below the original value.
Abstract: A video signal processing system is described in which a characteristic of individual picture points is provided to an accuracy of m binary bits but conveyed by n bits, where n is less than m. The value of a lower order bit of the n bit signal is switched to cause said binary value to represent, for any one picture point, either a value above or a value below the original value. The new values are distributed without order among the picture points with a probability dependent upon the value of the (m-n) lowest order bits of the desired value.

Journal ArticleDOI
TL;DR: In this article, an analytic solution for the behavior of the inner binary separation with time for a coplanar hierarchical triple system in which both the inner and outer orbit are (initially) circular is presented.
Abstract: This paper presents an analytic solution for the behavior of the inner binary separation with time for a coplanar hierarchical triple system in which both the inner and outer orbit are (initially) circular. This separation will be important if the inner binary is a mass transferring binary system, since in this case small changes in the inner binary separation are likely to result in significant changes in the mass-transfer rate and hence in the luminosity. The timing of the minima in the separation, when such luminosity bursts would occur, is shown to be strongly dependent on the inner binary mass ratio and might therefore serve as a diagnostic on the inner binary mass ratio in such systems. The advantages and drawbacks of the method are discussed.

Patent
04 Sep 1987
TL;DR: In this paper, the authors present a device for computing a discrete cosine transform (DCT) consisting of a set of elementary circuits operating in serial arithmetic connected to receive the samples and arranged to provide the sums and differences of couples of the input samples on respective outputs; an additional circuit has inputs connected to the outputs of the elementary circuits for receiving the differences between couples of inputs and for directly computing one of the two of the samples of the transform in distributed arithmetic.
Abstract: Most of the useful discrete transforms of a signal X represented by N binary samples x0 . . . , xi . . . , x N-1 (Where N is a power of two) are such that, by combining the samples for obtaining the sum and the difference of couples of samples, the transforms may be converted into two transforms of half-length one of which may again be decomposed into two transforms of half-length. A device for computing such a discrete transform, for instance a discrete cosine transform (DCT) comprises a set of elementary circuits operating in serial arithmetic connected to receive the samples and arranged to provide the sums and differences of couples of the input samples on respective outputs; An additional circuit has inputs connected to the outputs of the elementary circuits for receiving the differences between couples of the input samples and for directly computing one of the two of the samples of the transform in distributed arithmetic. Another computing circuit distinct and different from the additional circuit has inputs connected to the elementary circuits and computes the remaining samples of the transform from the sums.

Journal ArticleDOI
TL;DR: This work shows how to produce a binary doubly even self dual codes as binary images of some principal ideals in a group algebra starting from any binary cyclic code with length not a multiple of 4 and dimension at least 3.

Journal ArticleDOI
TL;DR: An equation is developed that allows for determination of the firing vector in terms of the markings and the input and allows for extension to other classes of Petri-nets as well as yield ease of programming for petri-net analysis.
Abstract: A full set of equations describing binary Petri-nets is presented in terms of integer algebra. In doing this, an equation is developed that allows for determination of the firing vector in terms of the markings and the input. Because the results are expressed in terms of integer arithmetic rather than Boolean algebra, they allow for extension to other classes of Petri-nets as well as yield ease of programming for Petri-net analysis.

Journal ArticleDOI
TL;DR: The long-hand square root algorithm, when implemented in binary arithmetic, produces immediately the analytic result (as opposed to the successive approximations generated by the Newton-Raphson method).
Abstract: The long-hand square root algorithm, when implemented in binary arithmetic, produces immediately the analytic result (as opposed to the successive approximations generated by the Newton-Raphson method). It also uses only addition, subtraction, and bits shifts; it is related to the binary integer division algorithm, but is in fact a simpler procedure.

Patent
27 Mar 1987
TL;DR: In this paper, an optical computer apparatus and method in which binary operations are implemented by utilizing optical elements to perform AND-OR-INVERT operations of the binary operation and combinatorial logic elements perform the remaining operations.
Abstract: An optical computer apparatus and method in which binary operations are implemented by utilizing optical elements to perform AND-OR-INVERT operations of the binary operation and combinatorial logic elements perform the remaining operations. Preferably, a pair of acousto-optic cells are energized by binary data, which data are supplied by combinatorial logic, and which cells modulate light rays that are focused on detectors which determine the presence or absence of light. The particular combination of data supplied by the combinatorial logic is a function of the operations remaining in the desired binary operation once any AND-OR-INVERT functions have been implemented by way of optical structures. Further, the propagational time through the acousto-optic cells is utilized to implement systolic type implementations of binary functions.

Journal ArticleDOI
TL;DR: This letter adresses the problem of computing the average values associated to geometric decompositions of binary quadtrees, under a faisly general branching process probabilistic model adapted to these types of trees.

Journal ArticleDOI
M. Serra1
TL;DR: Using multiple-valued LFSR's for the testing of MVL circuits and of binary circuits to show higher effectiveness while maintaining a smaller implementation is examined.
Abstract: Binary linear feedback shift registers (LFSR's) have acquired great importance in their implementation of a method of data compaction used in the testing of digital circuits. In this paper a new idea is examined: using multiple-valued LFSR's for the testing of MVL circuits and of binary circuits. For MVL circuits a non-binary LFSR avoids the need of decoding the signals and its implementation requires fewer digits than the binary tester. For binary circuits, a multi-valued LFSR tester shows higher effectiveness while maintaining a smaller implementation. An analysis is given of fault coverage for binary and multi-valued circuits, and optimal implementations of multi-valued LFSR's are presented.

Journal ArticleDOI
TL;DR: A new family of multivalued logic circuits is presented that are the first MV dynamic operators reported in the literature, they implement the Vranesic-Smith-Lee algebra, and their performance has been found to be similar to binary counterparts by simulation.
Abstract: A new family of multivalued logic circuits is presented These circuits exhibit some appealing features: they are the first MV dynamic operators reported in the literature, they implement the Vranesic-Smith-Lee algebra (which is specially suited for arithmetic operations), and their performance has been found to be similar to binary counterparts by simulation

Patent
04 May 1987
TL;DR: An apparatus and method for high speed parallel processing of image data corresponding to picture elements of an image in which the image data for each picture element is formatted as a binary word for multiplication by a plurality of different coefficients also in binary format as mentioned in this paper.
Abstract: An apparatus and method for high speed parallel processing of image data corresponding to picture elements of an image in which the image data for each picture element is formatted as a binary word for multiplication by a plurality of different coefficients also in binary format. Parallel processing is accomplished by a plurality of multiplication circuits each of which stores select coefficients and receives binary formatted image data words simultaneously in timed sequence from the least significant data bit to the most significant data bit.

Journal ArticleDOI
R. De Mori1, R. Cardin1
TL;DR: The same structure can be used for computing the antilogarithm of a number, thus allowing to obtain the quotient of two binary numbers in O(logN) time complexity and O(N2) area complexity.

Patent
05 Oct 1987
TL;DR: In this paper, a plurality of members, each constructed to produce a sunstantially constant current when energized, are disposed electrically in a matrix defined by the plurality of rows and columns.
Abstract: A plurality of members, each constructed to produce a sunstantially constant current when energized, are disposed electrically in a matrix defined by a plurality of rows and a plurality of columns. A plurality of signals cumulatively represent a digital value. Each of the signals has logic levels respectively coding for a binary "1" and a binary "0" and each has an individual binary significance. The binary signals of intermediate binary significance are decoded to activate an individual one of the rows. The binary signals of high binary significance are decoded to activate an individual one of the columns. The member common to the activated row and the activated column then receives a substantially constant current, as do all of the members of lower binary significance than such common member. The signals of lowest binary significance are also decoded to produce a current having a magnitude indicative of the binary value coded by such signals. This magnitude corresponds to that obtained by multiplying a particular portion of the substantially constant current by a ratio having a numerator the value represented by the binary signals of least binary significance and having as its denominator the maximum value capable of being coded by such binary signals. The current coding for the binary signals of least binary significance passes through a member otherwise superfluous in the matrix and preferably having an extreme position electrically in the matrix. The currents flowing through all of the members in the matrix are added in an output line to indicate an analog of the digital value.