Showing papers on "Binary number published in 1988"

A new efficient memoryless residue to binary converter

Abstract: An algorithm is described which converts the moduli (2/sup k/+1, 2/sup k/, 2/sup k/-1) residue numbers into their binary equivalent. A hardware implementation for this algorithm was constructed using binary adders only. The proposed algorithm and its implementation have the following advantages: (1) it enables an extremely wide fixed-point dynamic range, since its upper bound is not limited by a memory size; (2) it requires only four binary adders, two of which are operating in parallel; consequently, its conversion speed is higher than any similar reported converter, and its integrated circuit implementation would occupy less area; and (3) novel compact forms of the multiplicative inverses for the above moduli set are introduced. >

An efficient residue to binary converter design

Abstract: A description is given of a novel residue to binary converter It converts the three moduli residue number system (RNS) representation (2/sup n/-1, 2/sup n/, 2/sup n/+1) into binary representation The conversion process depends on simple mathematical relationships without using mixed radix or the Chinese remained theorem These simple relationships provide simpler hardware realization for the RNS to binary conversion >

Optimal hardware and software arithmetic coding procedures for the Q-Coder

Abstract: The Q-Coder is an important new development in arithmetic coding. It combines a simple but efficient arithmetic approximation for the multiply operation, a new formalism which yields optimally efficient hardware and software implementations, and a new form of probability estimation. This paper describes the concepts which allow different, yet compatible, optimal software and hardware implementations. In prior binary arithmetic coding algorithms, efficient hardware implementations favored ordering the more probable symbol (MPS) above the less probable symbol (LPS) in the current probability interval. Efficient software implementation required the inverse ordering convention. In this paper it is shown that optimal hardware and software encoders and decoders can be achieved with either symbol ordering. Although optimal implementation for a given symbol ordering requires the hardware and software code strings to point to opposite ends of the probability interval, either code string can be converted to match the other exactly. In addition, a code string generated using one symbol-ordering convention can be inverted so that it exactly matches the code string generated with the inverse convention. Even where bit stuffing is used to block carry propagation, the code strings can be kept identical.

Infinite families of perfect binary arrays

Abstract: The author constructs four infinite families of perfect binary arrays. Jedwab and Mitchell have constructed some small perfect binary arrays using quasiperfect binary arrays and doubly quasiperfect binary arrays. The author shows that a doubly quasi-perfect binary array is equivalent to a quasiperfect binary array. This means Jedwab and Mitchell's construction can be iterated to obtain larger perfect binary arrays. >

Encoding and decoding system for electronic data communication system

Abstract: An encoding and decoding system for electronic data communication system, wherein each character to be transmitted is encoded as a unique multi-bit binary value. The total number of bits as well as the number of logic one bits in all unique multi-bit binary values are the same. A pulse generating means generates a wide pulse for each logic one and a narrow pulse for each logic zero. The pulses which make up a unique pulse form for each data character to be transmitted are of alternating polarity and are transmitted as analog signals.

Fast conversion between binary and residue numbers

Abstract: New, efficient hardware implementations are considered which perform code conversions between the three moduli (2n − 1, 2n, 2n + 1) residue number systems and their binary representations. Significant hardware saving together with high-speed throughput is achieved by using onlynand (n + 1)-bit binary adders.

Residue to binary conversion for RNS arithmetic using only modular look-up tables

Abstract: A novel technique for converting from the residue digits in a residue number system (RNS) to weighted binary digits is proposed. This technique is an alternative to existing methods based on the Chinese remainder theorem (CRT) and the mixed-radix conversion (MRC) algorithm. The proposed technique obtains the binary digits in a slice-by-slice fashion, directly from the residues. The primary advantage of the method is that this conversion technique can be implemented using only modular lookup tables. >

Constructing new perfect binary arrays

Abstract: Only a small number of different sizes are known for which there exist two-dimensional perfect binary arrays. Construction methods are given which generate new two-dimensional perfect binary arrays, four of which are larger than any previously reported.

Method for canonical ordering of binary data for portable operating systems

Abstract: A method for making files compatible between different computers having different binary structures while using the same operating system by keeping all files in a standardized canonical order when they move to or from external data storage or communication means. The method includes converting all binary data accessed from a file or communications channel from the canonical order to the natural order of the host computer before using the binary data in the host computer and converting all binary data which is to be sent to a file or communications channel from the natural order of the host computer to the canonical order before sending the binary data.

Digital information coding system

Abstract: In a digital information coding system for transforming a binary digital information train without limitation of bit arrangement into run length limited binary codes, the run length taking only a value obtained by adding an integer multiple of a specific positive integer s to a minimum value d, within the range of the minimum value d and the maximum value k, and the positive integer s is 2 or more and is an aliquant number relative to d+1, and the maximum value k is a value obtained by adding an integer multiple of the positive integer s to the minimum value d. The advantages of this coding system are that the gradient of a magnetization reversal distance relative to a discrimination timing window width can be set as desired, and that the minimum magnetization reversal distance and the effective data discrimination timing window width during signal reproducing can be set as desired within the range of the channel capacities and have a considerable degree of freedom which has not been obtained by conventional codes.

Resisting the effects of channel noise in digital transmission of information

Abstract: A method for resisting the effects of channel noise in the digital transmission of information by means of the technique known as vector quantization, in which the codebook for binary index code assignment is generated by picking a vector quantized codeword with high probability and low perceptually-related distance from a required group of nearest neighbors, assigning that codeword and those neighbors binary index codes differing only in one bit, repeating the steps just outlined for assigned binary index codes to residual codewords until the lasts assignments must be made arbitrarily. Applications include transmission of speech by coded LPC parameters and transmission of image intensity or chrominance blocks for visual images. Such systems also make possible and are attractive for memory-efficient storage of such signals.

Means and method for implementing a two-dimensional truth-table look-up holgraphic processor

Abstract: Algorithms and optical processor architectures for implementing a two-dimensional truth-table look-up processor are disclosed. An optical holographic medium stores the spectral expansion coefficients that map two-dimensional digital inputs of a binary truth-table into two-dimensional outputs of that binary truth table. Several algorithms are described using discrete orthogonal transforms such as one of the Walsh transforms (the Walsh-Hadamard transform, the Rademacher-Walsh transform, the Walsh-Kaczmarz transform) or the Haar transform. These transforms are used to find the corresponding spectral vectors and the corresponding boolean basis vector. The inner product multiplication of the spectral vector with the boolean basis vector yields the digital outputs of the binary truth-table. Another algorithm uses the Reed-Muller expansion which is a non-orthogonal transform. Various architectures of digital optic two-dimensional truth-table look-up processors are also disclosed. They include a coded phase correlator, a matrix multiplication optical processor, a bipolar coded phase optical correlator and a bipolar matrix multiplication optical processor.

Image signal binary encoder

Abstract: An image signal binary encoder converts a document image photoelectrically into analog signals and then into digital image signals by an analog-to-digital converter. A small area is considered around each point of interest and the average density value of the area is compared with the density value of the point of interest. A choice is made between an ordinary binary conversion method and a dither method according to the result of this comparison.

Circuit for comparing a plurality of binary inputs

Abstract: A circuit for comparing a plurality of binary numbers according to this invention includes a circuit (101, 102, 103, 111) for receiving M (M ≧ 3) binary numbers (A, B, C), and generating and outputting a signal (NA, NB, NC) representing which of the binary numbers is maximum or minimum.

Efficient axis-translation of binary digital pictures by blocks in linear quadtree representation

Abstract: For binary digital pictures with large all-black fragments, the linear quadtree representation is a space-efficient data structure on which many time-efficient algorithms, such border-determination and filling, have been implemented. Translation—moving the picture bodily in a fixed direction—was originally done by converting each pixel into bit-map form. More recently, a recursive translation-rotation algorithm has appeared which makes better use of the hierarchical nature of the data structure, together with a time-complexity bound expressed in terms of the output. We present a nonrecursive translation algorithm with the same asymptotic worst-case time-complexity bound as the recursive algorithm, but which turns out to execute significantly faster than either of the previous algorithms. We generalize this algorithm to higher dimensional pictures, and we express the time-complexity in terms of the input data.

Arithmetic Fourier Transform And Adaptive Delta Modulation: A Symbiosis For High Speed Computation

Abstract: This report presents preliminary results on the VLSI design and implementation of a novel and promising algorithm for accurate high-speed Fourier analysis and synthesis. The Arithmetic Fourier Transform is based on the number -theoretic method of Mobius inversion. Its computations proceed in parallel and the individual operations are very simple. Except for a small number of scalings in one stage of the computation, only multiplications by 0, +1, and -1 are required. If the input samples were not quantized and if deal real-number operations were used internally, then the results would be exact. The accuracy of the computation is limited only by the input A/D conversion process, any constraints on the word lengths of internal accumulating registers, and the implementation of the few scaling operations. Motivated by the goal of efficient, effective, high-speed realization of the algorithm in an integrated circuit, we introduce further simplicities by the use of delta modulation to represent the input function in digital form. The result is that only binary (or preferably, ternary) sequences need to be processed in the parallel computations. And the required accumulations can be replaced by up/down counters. The dynamic range of the resulting transformation can be increased by the usemore » of adaptive delta modulation.« less

Optical on-the-fly conversion of a modified signed digit into two's complement binary number representation.

Abstract: An optical carry-free technique is introduced for conversion of a modified signed digit (MSD) into two’s complement binary number Using a combination of optical polarizing beam splitters and retardation waveplates, the proposed device performs this conversion on the fly The availability of this converter will lead to a large speed increase for various proposed optical parallel MSD arithmetic processors

Design of polarization-encoded optical shadow-casting logic units using truth-table partitioning

Abstract: The input pixel size of a polarization-encoded optical shadow-casting logic system is reduced by means of truth-table partitioning. The proposed design algorithm is used to encode the inputs of a three-input, two-output binary full adder. A comparison with alternative designs proves that the technique leads to an improved memory-efficient optical computing unit.

Methods and devices to read decimal figures on numerical indicators, especially on meters

Abstract: The device reads figures on the digital display of a counter (1) and consists of a housing (4) which is fixed to the counter and which contains an optical device (8) and a scanning image analyser (9). The optical device forms an image of the digital display in the image plane of the analyser. The video signal emitted by the analyser is converted into elementary binary signals by a digitizer. These binary signals are sent to a pattern recognition device comprising a microprocessor which is programmed to compare each combination of binary signals corresponding to one decimal figure with ten combinations which are contained in a memory and which correspond to the ten decimal figures.

A new parallel multiplication algorithm and its VLSI implementation

Abstract: A new fast algorithm for parallel multiplication of two n-bit binary numbers has been presented in this paper. The proposed algorithm computes the product in 31og2n units of time of a single bit full-adder and is easily implemented on a suitable VLSI architecture using less than n(n + (1/2) log2n)/2 processing elements. The algorithm requires regular interconnection between only two types of cells and hence is very suitable for VLSI implementation. It can also be easily modified to handle two's complement numbers without any additional execution time.

Algorithms for the minimization of binary and multiple-valued logic functions

Abstract: The objective of logic minimization is to find a representation which lends itself to cost effective implementation. In this thesis new algorithms for the minimization of multiple-valued logic functions are presented. Any binary multiple-output problem can be transformed into a multiple-valued function. Therefore, the binary multiple-output problem can be solved by the techniques described in this thesis. Similarly, any multiple-valued multiple-output can be transformed into a single multiple-valued logic function. The thesis thus covers the complete spectrum of logic minimization. In some technologies, the truncated SUM operator is easier to implement than the more commonly used MAX operator. Due to the increased complexity associated with the truncated SUM operator, exact minimization is not feasible. A new direct cover algorithm for minimization with the truncated SUM is presented. Two heuristics are used by the proposed algorithm. First, the most isolated minterm is selected to be initially covered. Second, for each implicant which contains the chosen minterm the break count reduction is calculated. The implicant with the best break count reduction is chosen to be part of the solution. Directed search minimization integrates the choice of the minimal cover into the prime implicant generation process. An extension of the directed search algorithm to accommodate multiple-valued logic function is described. A new binary recursive consensus algorithm which starts with a sum-of-products expression is presented. The order in which product terms are generated is different from the traditional iterated consensus. In addition, information on the intersection between product terms is kept. These two changes facilitate the early detection of essential and pseudo-essential prime implicants. Moreover, the algorithm is adapted to handle multiple-valued logic functions. The algorithm combines the advantage of starting from a list of terms and detection of essential prime implicants while generating prime implicants. Finally, it is shown how the algorithms can be adapted to minimization with window literals. Window literals appear more frequently in the literature and are often easier to implement.

Directed search minimization of multiple-valued functions

Abstract: A directed search algorithm to minimize multiple-valued input functions with a single binary output is presented. A multiple binary output minimization problem is readily transformed to such a function. Further, any multiple-valued function can be transformed to a multiple binary output problem and hence to a function suited to the presented algorithm. The proposed algorithm can thus be applied to a broad class of minimization problems. Heuristics suitable for PLA (programmable logic arrays) realizations are used. Some results showing the performance of the algorithm are presented. >

Binary calculation circuit

Abstract: A circuit for performing binary calculation, the circuit being of the type having at least one cell possessing: a first bit input (Ai), a second bit input (Bi), a carry-in input (Ri-1), circuitry (1600) for generating a two input bit exclusive-OR signal (Ai⊕Bi) and its complement (Ai⊕Bi), circuitry (1800) for producing a result signal, and circuitry (1900) for producing a carry-out signal (Ri), the circuitry being constituted by multiplexed logic. The complemented two input bit exclusive-OR signal (Ai⊕Bi) is produced by inverting the two input bit exclusive-OR signal (Ai⊕Bi), thereby making it possible to utilize only 15 transistors in the most cut-down version of the circuit. The invention also relates to a circuit (20) having an addition cell (22) calculating the sum of the input bits and a subtraction cell (24) calculating the difference of the input bits. The circuitry (1600) for producing the two input bit exclusive-OR signal (Ai⊕Bi) and its complement (Ai⊕Bi) are then used in common both by the addition cell (22) and by the subtraction cell (24).

Preferred patterns in convection in rotating binary mixtures.

Abstract: It is shown that for rotating binary liquids in the extreme Soret regime there is a critical Taylor number below which convection sets in as zero-wave-number rolls. Above the critical Taylor number a finite wave number is selected and the critical wave number depends on the rotation speed. Experimental possibilities are discussed.

Adder using multi-state logic

Abstract: A binary digital full adder as a component element of a digital circuit receives three binary signals including two input signals and a carry-in from the lower digit. The adder comprises a four-state logic converter for adding together the three binary signals in terms of current addition to convert the sum into a four-state logic signal, and an encoder for deciding a four-state logic level to encode it into a binary sum and a carry-out.

Simplified arithmetic for optical symbolic substitution

Abstract: Simplified arithmetic rules for optical symbolic substitution are identified. The proposed scheme involves only one single step and only four symbolic substitution rules for both addition and subtraction of binary numbers.