Showing papers on "Binary number published in 1989"

Test set embedding in a built-in self-test environment

Abstract: The authors describe a built-in self-test (BIST) technique where the on-chip test pattern generator is a binary counter with associated XOR gates. A precomputed set of tests (obtained through some test generation scheme) is required for this approach. A subset of this set of tests forms the basis for the synthesis of the binary counter and accompanying (combinational) logic using linear algebraic techniques. Simulation of this BIST technique on various benchmark circuits has given good results in terms of both coverage and hardware size. >

Digital Optical Computing With Symbolic Substitution

Abstract: Symbolic substitution is a spatial logic which is adapted well to optical processing. Unlike Boolean logic it also includes spatial information in the coding. It requires only regular interconnections and nonlinear devices with limited fan-out. Nevertheless the potential of this kind of logic ranges from parallel binary arithmetic to a programmable MIMD processor. Fundamentals of symbolic substitution and its applications are presented.

Digital parallel correlator

Abstract: An improved digital parallel correlator is disclosed. Illustratively, the inventive correlator utilizes a shift register which receives a signal comprising data bits encoded as chips. At each cycle of the signal, the chips in the shift register are compared to a reference sequence and the number of matches is obtained. Whenever the number of matches exceeds a fixed high threshold or falls below a fixed low threshold, indicating the presence of a binary 1 or binary 0 data bit, the chips in the shift register are set to a predetermined sequence such as the reference sequence or its complement. This amounts to correcting any chips of a bit that are received in error as soon as it is determined that the bit is a binary 1 or binary 0. This enables the high and low thresholds to be located as far as possible from the peak correlation values thereby increasing the number of chips that can be received in error.

Binary partitions with applications to hidden surface removal and solid modelling

Abstract: We consider schemes for recursively dividing a set of geometric objects by hyperplanes until all objects are separated. Such a binary partition is naturally considered as a binary tree where each internal node corresponds to a division and the leaves correspond to the resulting fragments of objects. The goal is to choose the hyperplanes properly so that the size of the binary partition, i.e., the number of resulting fragments of the objects, is minimized. We construct binary partitions of size O(n log n) for n edges in the plane, and of size O(n) if the edges are orthogonal. In three dimensions, we obtain binary partitions of size O(n2) for n planar facets, and prove a lower bound of O(n3/2). Two applications of efficient binary partitions are given. The first is an O(n2)-sized data structure for implementing a hidden-surface removal scheme of Fuchs, Kedem and Naylor [5]. The second application is in solid modelling: given a polyhedron described by its n faces, we show how to generate an O(n2)-sized CSG (constructive-solid-geometry) formula whose literals correspond to half-spaces supporting the faces of the polyhedron (see Peterson [9] and Dobkin et al. [3]). The best previous results for both of these problems were O(n3).

Rotation invariant phase-only and binary phase-only correlation.

Abstract: Phase-only circular harmonic filters and binary phase-only circular harmonic filters are proposed. Both filters have full rotation invariance and excellent performance for discrimination between objects and against background noise. Their properties have been studied and implemented for computer applications. The binary filters are appropriate for real-time applications using spatial light modulators.

JANUS, an on-line multiplier/divider for manipulating large numbers

Abstract: The authors deal with the detailed VLSI implementation of a fast bit-serial operator designed to perform very high precision (600 decimal digits) additions, multiplications, and divisions, and some of the applications of the circuit are discussed. Online arithmetic needs carry-free redundant number systems. Frequently, the radix chosen is different from 2, since a carry-free addition algorithm can be used in radix r not=2. In radix 2, carry-free addition is possible, but with two inconveniences: the algorithm seems more complicated, and the delay is larger. The authors show that the first inconvenience vanishes if good binary representation of the digits in radix-2 signed digit notation is chosen. >

Data transmission system

Abstract: PURPOSE: To prevent the mixing of a warning signal used for a system with a signal indicating data by selecting bits in a first binary state so that the bits in the first binary state can not be constituted by a correction data stream. CONSTITUTION: This system is provided with a detecting device which applies a detection signal each time the column of (n) bits in a first binary state is detected, and a bit correcting means which corrects the binary state of at least one bit following the column of (n) bits. Then, the value of the (n) is selected so that a corrected data bit stream can not form N bits in the first binary state which are likely to be mixed with the column of N warning bits, arid the corrected data bit stream is applied. Thus, the operation can be attained regardless of the kind of the protocol of a data transferring link used for this system.

A general error-correcting code construction for run-length limited binary channels

Abstract: A general method is presented for constructing a single-error-correcting, run-length-limited code for the class of input-restricted, binary symmetric channels described by the parameters (d,k), where d is the minimum and k the maximum number of consecutive zeros in any allowable channel input sequence. Upper and lower bounds on the rates of these codes are derived. >

Image algebra representation of parallel optical binary arithmetic.

Abstract: A binary image algebra (BIA) that gives a mathematical description of parallel processing operations is described. Rigorous and concise BIA representations of parallel arithmetic and symbolic substitution operations are given. A sequence of programming steps for implementation of these operations on a parallel architecture is specified by the BIA representation. Examples of arithmetic operations implemented on a digital optical cellular image processor architecture are given.

Extension of an entropy property for binary input memoryless symmetric channels

Abstract: The channel output entropy property introduced by A.D. Wyner and J. Ziv (ibid., vol.IT-19, p.769-762, Nov.1973) for a binary symmetric channel is extended to arbitrary memoryless symmetric channels with binary inputs and discrete or continuous outputs. This yields lower bounds on the achievable information rates of these channels under constrained binary inputs. Using the interpretation of entropy as a measure of order and randomness, the authors deduce that output sequences of memoryless symmetric channels induced by binary inputs are of a higher degree of randomness if the redundancy of the input binary sequence is spread in memory rather than in one-dimensional asymmetry. It is of interest to characterize the general class of schemes for which this interpretation holds. >

Device for multi-precision and block arithmetic support in digital processors

Abstract: A device for multi-precision and block arithmetic support in a digital processor including a multiplier for multiplying two signed, unsigned or signed and unsigned binary numbers and having a dynamic range greater than -1 to +1, an arithmetic and logic unit for performing arithmetic and logic operations, a barrel shifter for barrel shifting at least one binary number, shifters for selectively shifting the output of the multiplier and multiplexers for selecting and interconnecting the outputs and inputs of the multiplier, the arithmetic and logic unit, the barrel shifter and the shifters.

Arithmetic operations in optical computations using a modified trinary number system.

Abstract: A modified trinary number (MTN) system is proposed in which any binary number can be expressed with the help of trinary digits (1, 0, 1 ). Arithmetic operations can be performed in parallel without the need for carry and borrow steps when binary digits are converted to the MTN system. An optical implementation of the proposed scheme that uses spatial light modulators and color-coded light signals is described.

Transmission performance analysis of a new class of line codes for optical fiber systems

Abstract: A family of mB(m+1)B binary, nonalphabetic, balanced line codes is presented that is suitable for high bit rate (>or=135 Mb/s) optical fiber transmission due to its relatively simple encoding and decoding rules. Here, B represents a block of m bits, where m is an odd number. The coding, decoding, and bit error rate (BER) performance of the codes are discussed. Statistical and spectral analysis for the specific case in which the number of bits, m, equals seven, is presented. This makes possible a detailed comparison of the proposed code with conventional 7B8B codes. >

A binary single-key-lock system for access control

Abstract: A binary coding method was invented and has been applied to the single-key-lock (SKL) system which achieves access control by associating with each accesser only one key and with each resource only one lock. The new system is called the binary single-key-lock (BSKL) system. In both the SKL and BSKL systems, through operations on the single-key-lock pair, the control information can be revealed. On the basis of the new binary coding method, and because binary operations are much faster, better performance for such an access control system can be achieved. The increased extensibility of the modification is also discussed. >

Robust and fast code-excited linear predictive coding of speech signals

Abstract: A description is given of an efficient code-excited linear predictive (CELP) coder for bit rates between 6 and 16 kb/s, and novel effective algorithms for the selection of the excitation signal. The authors then propose a class of binary codebooks having interesting properties in terms of performance, robustness against transmission errors and flexibility in the choice of the bit rate. Due to the optimal structure of the coder and to the fast algorithms for selecting the excitation signal, a real-time implementation has been made possible on one 32-bit floating-point digital signal processor. >

Fast parallel algorithms for binary multiplication and their implementation on systolic architectures

Abstract: Two algorithms for parallel multiplication of two n-bit binary numbers are presented. Both use column compression to increase the speed of execution. They require almost regular interconnection between only two types of cells and hence are very suitable for VLSI implementation. Both of them can also be easily modified to handle two's complement numbers with constant differences in time. >

Circuit arrangement for adding or subtracting operands coded in BCD-code or binary-code

Abstract: It is possible to add or subtract operands coded in binary coded decimal (BCD) code or in the binary code with the circuit arrangement upon employment of a single binary adder. In order to enable BCD operations, the BCD operations are supplied to the binary adder (DA) via input stages (EG1, EG2). The one input stage (EG1) inverts the allocated operand (A) when this operand has a minus sign. The other input stage (EG2) edits the allocated operand (B) such that, given positive operands, (A, B), the number 6 is added to the allocated operand (B) and the result is inverted given negative operands (A, B). Given operands in the binary code, the allocated operands are inverted when they are provided with a minus sign; otherwise, they are not influenced. After the operation of the edited operands (X, Y) in the binary adder (DA), a correction of the sum result (S) can be required given BCD operation. This is the case when a carry signal (C) in the binary operation in the binary adder (DA) has appeared at the most significant place of the sum result. In this case the number 6 is subtracted from the sum result (S) in an output stage (AGS). This leads to the corrected sum (R). Upon employment of a single binary adder, it is possible to add and to subtract BCD numbers and binary numbers with the circuit arrangement.

Integration model predicting ternary thernodynamic properties from binary ones

Abstract: A new solution model named integration Model has been developed for predicting the ternary thermodynamic properties from its binary ones. This model is more reasonable for its full utilization of binary information. Binary thermodynamic properties are fitted by means of rational function method and ternary partial thermodynamic properties are calculated using R-function method. Integration model was applied to the Na-Hg-Pb system and a good accordance was obtained between the calculated and experimental values.

Methods and apparatus for determining the absolute value of the difference between binary operands

Abstract: In a floating point ALU, a carry-lookahead adder circuit includes integral XOR logic means for complementing the sum bits responsive to an invert signal for generating the absolute value of the difference between two binary operands without added gate delay.

Numeric encoding method and apparatus for neural networks

Abstract: A numeric encoding method and apparatus for neural networks, encodes numeric input data into a form applicable to an input of a neural network by partitioning a binary input into N-bit input segments, each of which is replaced with a code having M adjacent logic ones and 2 N -1 logic zeros, the bit position of the least significant of the M logic ones corresponding to the binary value of the input segment it replaces. The codes are concatenated to form an encoded input. A decoding method decodes an output from the neural network into a binary form by partitioning the output into output segments having 2 N +M-1 bits each, each of which is replaced with an N-bit binary segment being a bracketed weighted average of the significances of logic ones present in the output segment. The binary segments are concatenated to form a decoded output.

Variable length encoding method and variable length decoding method, encoding device and decoridng device for the implementation of this method

Abstract: A variable length encoding method for encoding a finite or infinite series of values corresponding to a random variable whose distribution monotonically decreases on either side of the mean value in which the encoding tree has a regular structure which is defined by an arithmetic and logic device. In order to encode each value E, a first binary word, including only bits having a same value and whose number of bits B is an increasing function of the value to the encoded E, is determined. The number of bits B is computed according to a predetermined arithmetic and logic function B(E). The method also involves determining a second binary word having a value to be encoded, in the set of values to be encoded arranged in order of decreasing probability, and whose number of bits B' is derived from the function B(E) and from the number of bits B in the first binary word. A code word is formed by combining the first and second binary words thus determined.

Circuit for detecting zero result of addition/subtraction by simultaneously processing each pair of corresponding bits of a pair of given numbers in parralel

Abstract: A zero detection circuit operates to detect whether or not the result of addition/subtraction between a pair of binary numbers each composed of a plurality of bits becomes zero in all the plurality of bits. The zero detection circuit comprises a logic circuit receiving the pair of binary numbers A and B for generating a zero discrimination signal when anyone of the following four conditions is satisfied for each pair of bits of the same digit of the pair of binary numbers A and B: a first condition: if (Ai, Bi)=(0,0), (A i+1 , B i+1 )=(0,0); a second condition: if (Ai, Bi)=(0,0), (A i+1 , B i+1 )=(1,1); a third condition: if (Ai, Bi)=(1,1), (A i+1 , B i+1 )=0,1) or (1,0); and a fourth condition; if (Ai, Bi)=(1,0) or (0,1), (A i+1 , B i+1 )=(1,0) or (0,1) where i is a natural number indicative of the digit place of the pair of binary numbers A and B.

Smoothing of the edge-enhanced impulse response from binary phase-only filters using random binary patterns

Abstract: We report a technique for reducing the edge-enhanced impulse response from binary phase-only filters (BPOFs) In this technique, the object used to make the filter is multiplied by a random binary pattern Then the BPOF is constructed Experimental details are presented

Method and apparatus for determining the greatest value of a binary number and for minimizing any uncertainty associated with the determination

Abstract: A circuit for determining which of a plurality of binary numbers has the greatest decimal equivalent includes a binary-to-decimal converter which converts each of the binary numbers to a decimal equivalent code, a series of logic OR gates which OR together corresponding bits of like decimal value of each of the decimal equivalent codes, a priority encoder which compares the outputs of the OR gates, determines which output of the OR gates is active and has the greatest decimal value of the decimal codes, and converts the decimal code having the greatest value to a binary number, and a comparator which compares the binary number from the priority encoder with each of the binary numbers provided to the binary-to-decimal converter. A circuit for minimizing any uncertainty which may arise with a greatest value determination includes a series of logic OR gates which OR together bits of like decimal value of the binary numbers, a multiplexer controller which is responsive to the outputs of the logic OR gates and which determines which is the most significant active bit of the binary numbers, and a multiplexer which selects a certain number of bits of the binary numbers to provide to the greatest value determination circuit.

Method and apparatus for implementing adaptive forward differencing using integer arithmetic

Abstract: A method and apparatus for implementing adaptive forward differencing technique in integer arithmetic resulting in an increase in precision while minimizing the number of mathematical operations to be performed is disclosed. The method and apparatus of the present invention provides for using a floating binary point adaptive forward differencing technique in which the binary point of the forward difference register, containing the value of the parametric function, is not shifted during parameter adjust-up and adjust-down operations. The binary point of the succeeding forward difference registers each containing a value corresponding to succeeding higher order derivatives of the parametric functions, are initially shifted a number of bits equal to a predetermined number of bits `N` multipled by a multiplication factor (referred to as guard bits) and the binary point is shifted to the right by one bit when an adjust-up operation is performed and to the left by one bit when an adjust-down operation is performed respectively reflecting the removal of a guard bit when an adjust-up operation is performed and the addition of a guard bit when an adjust-down operation is performed.

Bounds on the reliability of binary coherent systems

Abstract: The structure function of a binary coherent system is approximated by using only a few of its minimal path sets and minimal cut sets. These two incomplete structure functions are represented as disjoint sums. The average of each is a lower and upper bound, respectively, for the system reliability. The usefulness of these bounds is demonstrated on example networks. >