Showing papers on "Binary number published in 1991"

Choice of filters for the detection of gravitational waves from coalescing binaries.

Abstract: Coalescing binaries are one of the most promising candidates for the detection of gravitational waves with the advent of the new generation of laser interferometric gravitational-wave detectors. Signals from coalescing binaries will most probably not stand above the broadband noise of the detector. Their detection is possible by the use of special data analysis techniques such as matched filtering which takes advantage of the fact that the wave form can be fairly well predicted. The wave form of the coalescing binary signal is known very accurately. However, the parameters of the signal are not known priori and the signal needs to be correlated with several filters which are copies of the coalescing binary wave form for different values of the parameters. In this paper we present an algorithm to choose a lattice set of filters by a criterion that every signal of a certain minimal strength is picked up by at least one filter of the set. The wave form is characterized by three parameters: the time of arrival, the mass parameter, and the phase of the signal. We show that it is enough to have just two filters corresponding to the phase of the signal. Determination of the lattice for various values of the mass parameter involves a knowledge of the cross correlation function of two chirp wave forms with different values of the parameters. It is shown that for a considerable range of the mass parameter, the peak value of the correlation function, in a certain approximation, does not depend on the absolute values of the parameters but only on their difference. This leads to a very convenient way of constructing most of the lattice. The maximum possible distance up to which we can see is restricted by the threshold of the detector. There is a further limitation on this distance brought about by the fact that we can use only a finite number of filters. The number of filters which one can use depends on the available computing power. Hence, there is an empirical relation between computing power and the distance up to which we can see. In a restricted sense, the computing power decides the number of detectable events. Numerical experiments indicate that parallel processing is a promising new approach to on-line data analysis.

Performance of binary and quaternary direct-sequence spread-spectrum multiple-access systems with random signature sequences

Abstract: The performance of synchronous and asynchronous, binary and quaternary (with and without offset) direct-sequence spread-spectrum multiple-access (DS/SSMA) communication systems using random signature sequences and arbitrary chip waveforms is investigated. The average probability of error at the output of the correlation receiver is evaluated using a characteristic-function approach for these systems. Numerical results are presented that illustrate performance comparisons between systems using random and deterministic signature sequences, synchronous and asynchronous systems, systems with rectangular or sinewave chip waveforms, and binary and quaternary systems with the same data rates and bandwidth. In all cases, the accuracy of the Gaussian approximation is also examined. >

On the detectability of pulsars in close binary systems

Abstract: The limitations of standard pulse searches in close binary systems are quantitively investigated. An efficiency factor gamma is introduced to describe the ease with which binary pulsars can be found, and the results of calculations of gamma as a function of pulsar spin period and binary orbital period are presented for both standard pulse searches and for searches using sophisticated acceleration codes. Two strategies are suggested which maximize the probability of finding pulsars in close binaries, and empirical relations between the optimum observation time and the parameters of a binary orbit are given.

Elastoplastic behavior of metal matrix composites based on incremental plasticity and the Mori-Tanaka averaging scheme

Abstract: The applicability of the Mori-Tanaka averaging method for the prediction of the response of binary composites loaded in the plastic range is investigated. The applied loading is subdivided into small increments and the Eshelby solution for the inhomogeneity problem is used in conjunction with the Mori-Tanaka averaging scheme to obtain the load increments in the various phases. Since the Eshelby solution depends on the instantaneous matrix material properties and these are updated at the end of each load increment by using the backward difference scheme, an iterative procedure is necessary for the calculation of the correct load increments in the phases (concentration factors). The performance of the Mori-Tanaka method is compared with results obtained using the periodic hexagonal array (PHA) finite element model and experimental results for a B-Al unidirectional fibrous composite; it is also compared with numerical simulations obtained from the modified PHA model for a SiC w -Al particulate composite.

Decomposition of binary integers into signed power-of-two terms

Abstract: Previous work has shown that approximation of digital filter coefficients using sums of signed power-of-two terms yields significant area/speed advantages in custom implementations, at the expense of a slight frequency response deterioration. The completeness, uniqueness, and resolving power of signed powers-of-two representations are studied, and circuits for extracting a prescribed number of signed power-of-two terms whose sum is the closest approximation to a given integer are presented. Examples of implementation of these circuits in a CMOS process are given. >

An accurate elementary mathematical library for the IEEE floating point standard

Abstract: The algorithms used by the IBM Israel Scientific Center for the elementary mathematical library using the IEEE standard for binary floating point arithmetic are described. The algorithms are based on the “accurate tables method.” This methodology achieves high performance and produces very accurate results. It overcomes one of the main problems encountered in elementary mathematical functions computations: achieving last bit accuracy. The results obtained are correctly rounded for almost all arguement values.Our main idea in the accurate tables method is to use “nonstandard tables,” which are different from the natural tables of equally spaced points in which the rounding error prevents obtaining last bit accuracy. In order to achieve a small error we use the following idea: Perturb the original, equally spaced, points in such a way that the table value (or tables values in case we need several tables) will be very close to numbers which can be exactly represented by the computer (much closer than the usual double percision representation). Thus we were able to control the error introduced by the computer representation of real numbers and extended the accuracy without actually using extended precision arithmetic.

Bit error probability for coherent M-ary PSK systems

Abstract: A simple technique for evaluating the bit-error probability of coherent M-ary phase-shift keying (PSK) with any bit-mapping is proposed. Closed-form expressions are given in terms of error functions for half- and quadrant-plane probabilities in the decision space, avoiding the numerical evaluation of complicated integrals that occurs in the direct method. Bit error probability expressions for M-ary PSK with Gray, natural binary, and folded binary bit-mappings are derived. >

Residue number encryption and decryption system

Abstract: An encryption and decryption system performs encryption and decryption using the residue number system. A binary input signal is converted into residue number system representation in a binary to residue converter. Pseudo random numbers, generated from pseudo random number generators, are then added to the converted input signal in modular, that is, residue number system, adders. The outputs of the modular adders are converted into binary or mixed radix digit representation and are then transmitted to the location of a decrypter. The transmitted binary or mixed radix digit signal is converted back into residue number system representation in another converter and is then decrypted by subtracting the pseudo random number sequence. This decrypted signal is then converted into binary representation. The binary representation of the decrypted signal resembles the input signal.

An algorithm for the computation of binary logarithms

Abstract: The author presents a simple algorithm for the computation of the base-2 logarithm of a given binary number. The concept can be easily extended to base-N. Unlike other methods, this is not a curve fitting of the base-2 logarithm of a given binary number. The algorithm constitutes a simple step-by-step, bit-by-bit, computation of the logarithm of binary numbers. It can be easily implemented in simple microcode, and offers precision that is proportional to the number of performed iterations. Thus, it asymptotically converges to the true logarithm of the given number. >

Lower bounds for the linear complexity of sequences over residue rings

Abstract: Linear feedback shift registers over the ring Z2e can be implemented efficiently on standard microprocessors. The most significant bits of the elements of a sequence in Z2e? constitute a binary pseudo-random sequence. We derive lower bounds for the linear complexity over F2 of these binary sequences.

Method for pseudo-systematic error correcting convolutive coding, decoding method and corresponding devices

Abstract: The invention relates to a convolutional coding method correcting errors of a sequence of source binary elements dk, intended to be transmitted in particular in a very noisy channel with a yield greater than 1/2, of the type work of the means (32) for temporarily storing the last n values of a series of intermediate binary values (ak), n being greater than or equal to two, and associating with each of said source binary elements dk two binary elements coded Xk and Yk, one of said binary elements coded Xk or Yk being equal to said source binary element dk and, the second of said binary elements coded Yk or Xk being determined according to a first mathematical combination (31) of a first set of at least two binary values systematically selected from said intermediate binary values ak, ..., ak - nu stored in said temporary storage means (32), each binary value intermediate ak being determined according to a second mathematical combination (33) of said source binary element dk and of a second set of at least one binary value systematically selected from the preceding intermediate values ak - 1, ..., ak - nu. This code can advantageously be punched. In this case, it provides better performance than conventional codes, when the signal to noise ratio is around 2 to 3 dB.

Disk allocation methods using error correcting codes

Abstract: The problem of declustering, that is, how to distribute a binary Cartesian product file on multiple disks to maximize the parallelism for partial match queries, is examined. Cartesian product files appear as a result of some secondary key access methods. For the binary case, the problem is reduced to grouping the 2/sup n/ binary strings on n bits in m groups of unsimilar strings. It is proposed that the strings be grouped such that these group forms an error correcting code (ECC). This construction guarantees that the strings of a given group will have large Hamming distances, i.e., they will differ in many bit positions. Intuitively, this should result in good declustering. The authors describe how to build a declustering scheme using an ECC, and prove a theorem that gives a necessary condition for the proposed method to be optimal. Analytical results show that the proposed method is superior to older heuristics, and that it is very close to the theoretical (nontight) bound. >

High-speed VLSI arithmetic processor architectures using hybrid number representation

Abstract: The design of high-speed architectures is addressed for fixed-point, two's-complement, bit-parallel, pipelined, multiplication, division and square-root operations. The architectures presented make use of hybrid number representations (i.e. the input and output numbers are presented using two's complement representation, and the internal numbers are represented using radix-2 redundant representation). A fast, new conversion scheme for converting radix-2 redundant numbers to two's-complement binary numbers is presented, and this is used to design a reduced latency bit-parallel multiplier. The novel sign-multiplexing scheme helps detect the sign of a redundant number very quickly and is used in combination with the remainder conditioning scheme to achieve very high speed in fixed-point division and square-root operators. These architectures require fewer pipelining latches than their conventional two's-complement counterparts. Reduction in latency without sacrificing clock speed has resulted in reduced computation time for these operations. >

Limits on cluster binaries

Abstract: An unresolved binary system will be systematically brighter and redder than the primary component alone These systems may measurably widen the main sequence in the color-magnitude diagram The width of the main sequence in NGC 6341 (M92) and NGC 7099 (M30) from published high-quality photometry is used to derive limits on the fraction of unresolved binary systems in these cluster fields A 'second sequence' is expected for quite general assumptions about the binary population Then, developing a maximum likelihood technique for using all the high-quality data in a color-magnitude plane, results for the two clusters are analyzed, limits on the binary fraction of about 9 percent and about 4 percent, respectively are derived In M92 in particular, there is a well-determined fraction, about 8 percent of binary candidate objects Photometric indices that most of these are due to crowding, but a small component consists of true binaries 16 refs

Binary encoding method with substantially uniform rate of changing of the binary elements and corresponding method of incrementation and decrementation

Abstract: A binary encoding method notably but not exclusively for the encoding of data elements designed to be represented sequentially, according to a preestablished order, for example in counters, inducing a uniform or substantially uniform mean changing rate for each of the binary elements, the data elements being encoded on two distinct fields of binary elements, a reference field and a permutation field, and the sequence of binary elements assigned to the permutation field undergoing a permutation as a function of the value contained in the reference field.

Fast digital comparison circuit for fuzzy logic operations

Abstract: A fast digital logic circuit for comparing two binary numbers and outputting the greater of the two is disclosed.

Transitive closure based process for generating test vectors for VLSI circuit

Abstract: A process for generating a vector for testing a digital circuit for a given fault first creates a composite circuit including a fault-present version of the circuit and a fault-free version. An implication graph is developed for the composite circuit and its energy function is derived as a combination of binary and ternary terms. All signal states that are consistent with the circuit function minimize the energy function to zero value. The transitive closure is computed for the binary terms, and redundancies, contradictions, fixations, identification and exclusions are identified. By iteration of implication graphs and transitive closures together with arbitrarily assigned signal values all ternary terms of the energy function are converted to binary terms, after which transitive closure recomputes a set of literals that can be used to generate the desired test vector by a standard branch and bound procedure.

Single-stage optical adder/subtractor

Abstract: Fully parallel processors call for a technology that is inherently parallel, a suitable number system, and an efficient encoding scheme for handling the data. The throughput of a binary adder/subtractor is limited by the carry propagation to the most significant bits. Optical adders using a modified signed digit (MSD) number system have been proposed to eliminate the carry propagation chain encountered in binary adders. The MSD number system satisfies the requirements of fully parallel addition/ subtraction by limiting the carry propagation to two positions to the left. This enables one to carry out the addition/subtraction of two n-digit MSD numbers in three stages, independent of n. In this paper it is shown that by suitably exploiting the redundant nature of the MSD number system, the carry generation and propagation can be completely eliminated. The MSD adder/subtractor presented in this paper fully exploits the redundant nature of the MSD number system and performs the addition/subtraction of two numbers in a single stage. The adder employs 81 substitution rules to perform the addition/subtraction of two MSD numbers in a single stage. The number of substitution rules can be reduced to 16 if the input numbers are limited to binary. The proposed architecture reduces the computation time by 33.3% compared to the three-stage MSD adder originally proposed.

Video signal processing with added probabilistic dither

Abstract: A system in which a characteristic of individual picture points is provided to an accuracy of m binary bits but conveyed by n bits, where n is less than m. The value of a lower order bit of the n bit signal is switched to cause said binary value to represent, for any one picture point, either a value above or a value below the original value. The new values are distributed without order among the picture points with a probability dependent upon the value of the (m-n) lowest order bits of the desired value.

Computation system and method using hamming distance

Abstract: Preferred embodiments include systems with neural network processors (58) having input encoders (56) that encode integers as binary vectors so that close integers encode as close binary vectors by requiring adjacent integers have encoded binary vectors that differ in a fixed fraction of their bits.

On learning binary weights for majority functions

Abstract: We investigate algorithms for learning binary weights from examples of majority functions of a set of literals. In particular, given a set of (randomly drawn) input-output pairs, with inputs being binary ±1 vectors, and the outputs likewise being ±1 classifications, we seek to find a vector of binary (±1) weights for a linear threshold element (or formal neuron) which provides a linearly separable hypothesis consistent on the set of examples. We present three algorithms–Directed Drift, Harmonic Update, and Majority Rule–for learning binary weights in this context, and examine their characteristics. In particular, we formally define a distribution dependent notion of algorithmic capacity (which is related to the distibution free notion of the VC dimension) and provide estimates of the capacity of the proposed algorithms.

System for converting a floating point signed magnitude binary number to a two's complement binary number

Abstract: A system for converting a floating point n-bit signed magnitude binary number to a fixed point two's complement binary number having m bits wherein m is greater than n, first converts the n bit signed magnitude binary number to a corresponding n-bit two's complement binary number. Thereafter, a shifter shifts the n-bit two's complement binary number to the left or right and by a number of bits responsive to received shift decode signals for providing the final fixed point m-bit two's complement binary number.

Programmable logic device

Abstract: Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal

Summary of perfect s t arrays, 1 s t 100

Abstract: Perfect binary arrays have been the object of investigation by several authors in recent years. This Letter collects known results, including those obtained by combinatorialists in pursuit of a different objective, and applies them to give an account of the status of such arrays of size s × t with 1 ≤ s ≤ t ≤ 100.

Conditional-sum carry structure compiler

Abstract: A conditional-sum carry structure has an architecture which is sufficiently regular that the structure can be conveniently generated by an automated compiler. The carry structure includes a column of input cells, each of the cells in the column being operative for receiving binary numbers and, for each of the received numbers, generating a sum bit and two carry-out bits. Further the carry structure includes an array of columns of binary logic elements comprised of dual multiplexers (MUX MUX elements), dual exclusive OR gates (XOR XOR elements), multiplexer and exclusive OR gate circuits (MUX XOR elements) and multiplexer units (ONE MUX elements) for receiving sum bits and carry-out bits from the input cells and for performing the operations of a conditional-sum carry structure.