Showing papers on "Binary number published in 1992"

Model-based halftoning using direct binary search

Abstract: In this work, we propose a new method to generate halftone images which are visually optimized for the display device. The algorithm searches for a binary array of pixel values that minimizes the difference between the perceived displayed continuous-tone image and the perceived displayed halftone image. The algorithm is based on the direct binary search (DBS) heuristic. Since the algorithm is iterative, it is computationally intensive. This limits the complexity of the visual model that can be used. It also impacts the choice of the metric used to measure distortion between two perceived images. In particular, we use a linear, shift- invariant model with a point spread function based on measurement of contrast sensitivity as a function of spatial frequency. The non-ideal spot shape rendered by the output devices can also have a major effect on the displayed halftone image. This source of non-ideality is explicitly accounted for in our model for the display device. By recursively computing the change in perceived mean-squared error due to a change in the value of a binary pixel, we achieve a substantial reduction in computational complexity. The effect of a trial change may be evaluated with only table lookups and a few additions.

Power-free values of binary forms

Abstract: Given a binary form f(x; y) 2 Z[x; y], we will be interested in nding the smallest k for which we can establish that there are in nitely many integers a and b such that f(a; b) is k free. Necessarily, we require the f has no xed kth prime power divisor. Until the nal section of this paper, we will also consider f to be irreducible. We set n = deg f . For k = 2, this problem has recently become of interest partially because of its connection to the rank of elliptic curves as described in the work of F. Gouvêa and B. Mazur [4]. In particular, F. Gouvêa and B. Mazur showed that if the degree of the binary form is 3, then f(a; b) is squarefree for in nitely many pairs of integers a and b. More speci cally, for a binary form f(x; y) 2 Z[x; y] of degree 3, they determined the density of pairs (a; b) of positive integers for which f(a; b) is squarefree, i.e., the value of

Fast and flexible architectures for RNS arithmetic decoding

Abstract: An implementation of a fast and flexible residue decoder for residue-number-system (RNS)-based architectures is proposed. The decoder is based on the Chinese remainder theorem. It decodes a set of residues to its equivalent representation in weighted binary number system. This decoder is flexible since the decoded data can be selected to be either unsigned magnitude or 2's complement binary number. Two different architectures are analyzed; the first one is based on using carry-save adders, while the other is based on utilizing modulo adders. The implementation of both architectures is modular and is based on simple cells, which leads to efficient VLSI realization. The proposed decoder is fast; it has a time complexity of theta (log N), where N is the number of moduli. >

Data encoding using one or more adaptive decision trees

Abstract: A method and apparatus for quantizing a stream of data at a predetermined bit compression ratio. A binary decision tree is established for classifying the error between a predicted and actual data value. The binary decision tree comprising a root node and multiple binary nodes represented by a pair of threshold values around the root node, a member of each pair representing a node in the binary decision tree and a threshold value indicative of a range of data values. The range in which the data values lies is then determined and a binary code representing the quantized error (token) between the predicted and actual data values. The quantized error symbol (token) is then encoded and a bit string corresponding to the error symbol is output, thereby representing compressed data. After a predetermined number of errors have been quantized (and encoded), the bit rate of the compressed data is compared to a predetermined (target) compression ratio. The ranges used to quantize the error are then adjusted to maintain the predetermined compression ratio.

The Mass-Ratio Distribution of Spectroscopic Binary Stars

Abstract: In order to determine the mass-ratio distribution of spectroscopic binary stars, the selection effects that govern the observations of this class of binary systems are investigated. The selection effects are modelled numerically and analytically. The results of the models are compared to the data inThe Eighth Catalogue of the Orbital Elements of Spectroscopic Binary Stars (DAO8) compiled by Battenet al. (1989). The investigations involve binary systems with Main-Sequence primary components only, in order to avoid confusion of evolutionary and selection effects.

Correlation VIA linear sequential circuit approximation of combiners with memory

Abstract: Correlation properties of a general binary combiner with an arbitrary number of memory bits are analyzed. It is shown that there exists a pair of certain linear functions of the output and input, respectively, that produce correlated binary sequences. An efficient procedure, based on a linear sequential circuit approximation, is developed for finding such pairs of linear functions. The result may be a basis for a divide and conquer correlation attack on a stream cipher generator consisting of several linear feedback shift registers combined by a combiner with memory.

Binary optical data subtraction by using a ternary dibit representation technique in optical arithmetic problems

Abstract: A new ternary dibit representation technique is proposed for a bitwise binary optical data subtraction process.

An efficient redundant-binary number to binary number converter

Abstract: The authors present a method for converting the redundant-binary representation into the 2's complement binary representation. Instead of using the conventional full adders, a more efficient redundant-binary number to binary number converter can be designed with the aid of the new variable C/sub i/. The method can be applied to both 'serial' and 'lookahead' modes. In both modes, it was shown that the authors' converter takes less chip area and conversion time when compared with the conventional method. >

Picosecond event timer

Abstract: A circuit for time stamping event signals, e.g. zero-crossings, using coarse and fine timers. The fine timer (15) is a circuit section which subdivides a period from a phase-locked ring-oscillator (13) into 2N subparts (39). An event signal is timed by latching a digital representation of a particular subpart. The digital representation of the subpart is an N-bit dual thermometer code (41) which uniquely identifies each subpart with each adjacent subpart differing by only one bit. The subparts are made finer in time quantization than the propagation delay of one active element in the ring oscillator (13) by the use of linear combiner elements (71, 73, 75). The dual thermometer code (41), encoded post-latching into a binary code, forms the "fine" timing part of a binary word representation of the event time. The event (11) also latches the count states of a pair of lead-lag counters (150, 151) in a master-slave configuration counting ring oscillator periods. These counters change states respectively before and after the dual thermometer code turn-overs. Only one reading is chosen for recording as determined by the most significant bit of the fine code. The choice will always find an accurate and stable reading, and reject erroneous readings resulting from reading a counter in transition. The chosen counter reading, encoded to binary, forms the coarse timer (17) for the binary word representation of the event time. The coarse and fine binary words are butt-joinable to form the complete binary timing representation without further arithmetic processing.

High-speed VLSI arithmetic processor architectures using hybrid number representation

Abstract: This paper addresses design of high speed architectures for fixed-point, two's-complement, bit-parallel division, square-root, and multiplication operations. These architectures make use of hybrid number representations (i.e. the input and output numbers are represented using two's complement representation, and the internal numbers are represented using radix-2 redundant representation). We propose newshifted remainder conditioning, andsign multiplexing techniques in combination with novel circuit architecture approaches to obtain efficient divider and square-root architectures. Our divider exploits full dynamic range of operands and eliminates the need for on-line or off-line conversion of the result to binary (this is because our nonrestoring division and square-root operators output binary quotient). Furthermore, since the binary input set is a subset of the redundant digit set, no binary-to-redundant number conversion is necessary at the input of the divider and square-root operators. We also present a fast, new conversion scheme for converting radix-2 redundant numbers to two's complement binary numbers, and use this to design a bit-parallel multiplier. This multiplier architecture requires fewer pipelining latches than conventional two's complement multipliers, and reduces the latency of the multiplication operation from (2W---1) to aboutW (whereW is the word-length), when pipelined at the bit-level.

Signal analysis technique for determining a subject of binary sequences most likely to have been transmitted in a multi-node communication network

Abstract: A method and apparatus are disclosed whereby a received signal comprising a binary spreading-code sequence, which belongs to a set of binary spreading-code sequences available to a transmitting node of a multi-node communication network, can be analyzed to determine the particular sequence from the set of sequences available to the transmitting node that was actually transmitted All sequences of the set of available sequences have the property that each sequence can be generated by the same configuration of two linear feedback binary shift registers, where the feedback taps on the two binary shift registers correspond to primitive polynomials of the same degree over GF(2), the field of two elements The received signal is correlated with each sequence of the set of available sequences to obtain a set of correlation values The correlation values having the largest and the next-largest magnitudes are compared, and if their ratio exceeds a predetermined threshold, a detection decision is made If the ratio does not exceed the predetermined threshold, additional logic is implemented to declare a detection decision or an erasure Once a detection decision has been made, the signal is decoded into a block of information bits corresponding to the largest correlation magnitude The sign of the corresponding correlation value determines one additional information bit

Method and unit for binary processing in image processing unit and method and unit for recognizing characters

Abstract: A binary processing method for a variable density image the method includes the steps of binary processing an image having variable density, according to which brightness of an image having variable density to be binary processed is given as 1/n (where n is an integer of 2 or above), and expansion processing and smoothening processing the image having the brightness of 1/n so that a threshold value image for binary processing is generated. A difference is obtained between the threshold value image and the variable density image to be binary processed, such that it is possible to carry out binary processing even for an image having a complex background or variance in brightness.

High-radix symbolic substitution and superposition techniques for optical matrix algebraic computations

Abstract: This paper presents a new 3-D digit-plane optical architecture for massively parallel matrix computations. This architecture decomposes matrix-structured data into digit planes using high-radix number representation and performs fast arithmetic on digit planes, exploiting spatial parallelism. While arithmetic operations are carried out using symbolic substitution, data manipulation operations (permutation, rotation, and translations) are carried out in parallel by a data manipulator using freespace optical interconnections. A new symbolic superposition technique is proposed to implement logical and set-theoretic operations on matrix-structured data in optics. The potential ofthis architecture is demonstrated to support structured matrix algebraic computation. We derive the complexity of symbolic substitution and symbolic superposition rules for radix-r arithmetic. The representational efficiency and the projected speed gain of high-radix arithmetic are compared against binary electronic matrix arithmetic.

Very-high-speed VLSI 2s-complement multiplier using signed binary digits

Abstract: A high-speed 8*8-bit multiplier design for 2s-complement binary numbers is presented. The multiplier uses the binary signed-digit number system to achieve both high speed and layout simplicity, and is implemented in double layer metal 2 mu m CMOS technology. The multiplication time for the array was found by simulation to be 18 ns at 25 degrees C and its size was measured as 1.7 mm*2.3 mm (excluding pads). Power dissipation was calculated as just less than 40 mW at 55 MHz, and the transistor count is 3754 transistors.

Method for determining the configuration of detectors of a danger alarm system and for determining the system configuration of suitable detectors

Abstract: A danger alarm system includes a plurality of detectors, each of which having a microprocessor, a current drain controllable by the microprocessor for data exchange with a central station, an address register, and a nonvolatile memory for containing an individual binary serial number. In order to allow with few exceptions the use of relayless detectors, the configuration of the detectors is determined by providing each detector with a unique binary serial number at the manufacturer's end, identifying and storing in an initialization routine the serial numbers, setting all detectors through a collective command in a discrete addressing mode and response mode for allowing each detector after being addressed by its own binary serial number to respond with a current pulse and subsequently after being addressed with the binary serial number of another detector to check the occurrence or absence of a current pulse and to store the test result as binary pattern, polling the stored binary pattern from each detector and forming from this pattern and from the binary serial numbers of the respective detectors a first matrix and a second matrix which is defined by the column sums and line sums of the first matrix, and by evaluating the first and second matrices in accordance with a given algorithm for determining the system configuration.

Binary phase accumulator for decimal frequency synthesis

Abstract: A direct digital synthesizer of the phase-accumulator type, constructed entirely of binary-radix digital hardware, generates signals with decimally-defined frequency resolution. The synthesizer is supplied with a clock signal which is also decimally-defined. The usual decimal-binary incompatibility problems of such a combination are overcome by the use of a phase accumulator which is partitioned into two segments. The first segment is assigned the most significant portion of the desired frequency, and the other segment is assigned the remaining portion of the desired frequency. The two segments have different arithmetic moduli. Typically, the modulus of the first segment is a power of two, while that of the second segment is an integer other than a power of two. A procedure is given for determining both the point of partition and the second arithmetic modulus.

Fault-tolerant computation using algebraic homomorphisms

Abstract: Arithmetic codes are a class of error-correcting codes that are able to protect computation more efficiently than modular redundancy. In this thesis we consider the problem of designing an arithmetic code to protect a given computation. The main contributions are as follows: (1) The first constructive procedure, outside of modular redundancy, for generating arithmetic codes for a large class of operations. The approach is mathematically rigorous, based on group-theory, and fully characterizes the important class of systematic-separate codes. The results encompass computation that can be modeled as operations in an algebraic group, ring, field, or vector space. (2) A novel set-theoretic framework for characterizing the redundancy present in a system. We present a decomposition of a robust system into a cascade of three systems and determine general requirements for multiple error detection and correction. (3) We identify an important class of errors for which the redundancy present in a system may be completely characterized by a single integer, analogous to the minimum distance of a binary error-correcting code. (4) We unify the existing literature on arithmetic codes. A wide variety of seemingly unrelated codes are combined into a single general framework. (5) A large number of examples illustrating the application of our technique are presented. (6) Detailed analyses of two new and practical fault-tolerant systems: fault-tolerant convolution and A/D conversion. (Copies available exclusively from MIT Libraries, Rm. 14-0551, Cambridge, MA 02139-4307. Ph. 617-253-5668; Fax 617-253-1690.)

Provably Total Functions of Intuitionistic Bounded Arithmetic

Abstract: This note deals with a proof-theoretic characterisation of certain complexity classes of functions in fragments of intuitionistic bounded arithmetic. In this Introduction we survey the background and state our main result.We follow Buss [B1] and consider a language for arithmetic whose nonlogical symbols are 0, S (the successor operation Sx = x + 1), +, ·, ∣ ∣ (∣x∣ being the number of digits in the binary notation for x), rounded down to the nearest integer), # (x#y = 2∣x∣∣y∣) and ≤. We define 1 = S0, 2 = S1, s0x = 2x and s1x = 2x + 1. In Buss's approach the functions s0 and s1 play a special role. Notice that six is the number obtained from x by suffixing the digit i to its binary representation, and thus the natural numbers are generated from 0 by repeated applications of the operations s0 and s1. This means that they satisfy the induction schemeUsing the fact that is x with its last binary digit deleted, this can be stated more compactly in the following form, called by Buss the polynomial induction or PIND schema:Buss defined a theory S2 consisting of a finite set BASIC of open axioms and the PIND-schema restricted to bounded formulas ϕ. The topic of bounded arithmetic is concerned with S2 and its fragments.

Optical implementation of gray-scale morphology

Abstract: There is much work concerning morphological image processing, both binary and gray scale. Almost all implementations to date are performed electronically on standard computers, specialized processors, or specialized hardware. Prior work has described implementation of binary morphology on an optical processor, as well as indicating the relative merits of using an optical system. However, the restriction to binary morphology on an optical system has required that gray scale problems be reduced to binary morphology solutions using judiciously chosen binarization thresholds. This paper describes how gray scale morphology can be implemented on an optical correlator system using a threshold decomposition algorithm. A series of thresholded binary correlations are formed optically and summed on a CCD detector array or spatial light modulator, to produce the output morphologically processed gray scale image. The speed this optical system is much faster than 30 gray scale images per second. The details of the architecture used to implement threshold decomposition on an optical system is described, and issues relating to the implementation of binary morphology on an optical system are discussed. The threshold decomposition algorithm is discussed with attention to ways to reduce the number of intermediate processing steps required.

Adaptive m-ary segmentation and canonical recoding algorithms for multiplication of large binary numbers

Abstract: We propose a variable-length segmentation strategy which significantly reduces the average number of additions required by the m-ary segmentation and the canonical recodiing algorithms for multiplication of large binary numbers. This strategy produces two new algorithms: the adaptive m-ary segmentation algorithm utilizes both the speedup inherent in high-radix multiplication and the ability to skip zero bits; the adaptive m-ary segmentation canonical recoding algorithm gains additional benefit from the increased probability of zero after the canonical recoding. The average number of additions required is computed using Markov chains.

Leading one anticipator and floating point addition/subtraction apparatus employing same

Abstract: A floating point addition/subtraction apparatus is internally provided with a leading one anticipator having redundant binary numeral generators, intermediate-carry/intermediate-sum generators, and scan-value generators. Each of the redundant binary numeral generators performs a subtraction with respect to two binary operands, a binary minuend and a binary subtrahend, to generate a redundant binary numeral Zsd having "-1", "0" or "1" at each digit thereof. Each of the intermediate-carry/intermediate-sum generators generates an intermediate carry C k and an intermediate sum S k in accordance with Zsd k =2C k +S k using a redundant binary numeral Zsd k positioned at a k th digit from a least significant digit of the redundant binary numeral Zsd and a redundant binary numeral Zsd k+1 positioned at a (k+1) th digit so that C k =Zsd k when Zsd k+1 ="1" or "-1" and C k =0 when Zsd k+1 ="0". Each of the scan-value generators generates "1" (or "0") when a result of an addition with respect to an intermediate carry C k-1 and the intermediate sum S k is "0" and generates "0"(or "1") when the result of the addition is a numeral other than "0".

Central processing unit including two-valued/n-valued conversion unit

Abstract: A central processing unit comprises a bidirectional circuit for converting a binary data and a binary address supplied from a binary logic circuit in the CPU into n-valued (n is an integer of 3 or larger) data and an n-valued address, respectively, and transmitting converted signals to the outside, and for converting n-valued data and an n-valued address supplied from the outside into binary data and a binary address, respectively, and transmitting converted signals to the binary logic circuit.

Random number generator

Abstract: A pseudo random number generator is provided which generates the next number in a pseudo-random sequence of numbers from a binary representation of an input number and a primitive root of a prime number P, where P has the form 2m-1, m being an integer. The binary representations of the current random number and the primitive root are multiplied to form a binary product. The binary number represented by bits 0 to m-1 of the product are added to the binary number represented by bits m to 2m-1 of the product to form a sum. The contents of bit m of the sum are then added to the sum, via the carry-in input of the adder. The next binary number in the sequence is represented by bits 0 to m-1 of the sum with the contents of bit m thereof so added. Particular applications include data processors having an imbedded multiply-add unit with reconfiguration resources to implement the invention.

Modern Digital Design and Switching Theory

Abstract: Number Bases, Codes, and Binary Arithmetic. Boolean Algebra and Implementation. Boolean Algebra and Circuit Realizations. Mapping Boolean Expressions. Advanced Simplification Techniques. Multiplexers, Demultiplexers, ROMs, and PLDs. Latches and Flip-Flops. Counters and Registers. Application-Specific Integrated Circuits. Multilevel Minimization. Index.

A circuit detecting the position of an extreme "1" bit in a binary number

Abstract: Apparatus for detecting the leftmost "1" bit or the rightmost "1" bit of an input number includes a binary tree (11) of two-inputs OR-gates (13, 14, 15, 16) or their logical equivalent to which the input number is applied in parallel and from which signals are derived and applied as inputs and to control a plurality of trees (MA, MB, MC) of two-input multiplexers (12) from the outputs (E0, E1, E2, E3) of which appear the bits of a number representing the position in the input number of the leftmost "1" or the rightmost "1" bit.