Showing papers on "Binary number published in 1993"

Logic structure and circuit for fast carry

Abstract: Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal.

Spinodal decomposition in 3-space.

Abstract: Using a cell-dynamical system (CDS) to model the separation of phases, we present the results of large-scale simulations of spinodal decomposition in 3-space of a symmetric binary alloy and incompressible binary fluid at critical quench. Our main results are (1) the reliable determination of the asymptotic or the almost asymptotic form factors for these systems, and (2) an understanding of the preasymptotic behavior of growth laws in terms of dispersion relations of interface fluctuations. To achieve (1) it is indispensable to have (i) methods to analyze the data, (ii) a scheme to simulate a system with fluid dynamic interactions, and (iii) a demonstration of the self-averaging nature of spherically averaged quantities. Item (iii) allows us to study sufficiently large systems with currently available computational resources. A careful stability analysis of our CDS model (such as artificial pinning, anisotropy, etc.) is also given. We must point out that the conventional data analysis coupled with artificial pinning and finite-size effects may spuriously give the theoretically desired results, especially in binary fluids. The asymptotic form factors are estimated in collage form from our large-scale late-time simulation results and various theoretical asymptotic results such as Tomita's sum rule. We may conclude that for binary fluids, the agreement between our form factor and ones obtained experimentally is excellent. This also clearly demonstrates that apart from time- and space-scale changes binary polymer systems so far studied and low-molecular-weight systems are not distinct; that is, no polymer effect has been observed in the form factor. In the case of binary alloys, the agreement with our form factor and various experimental results is not as good as the binary fluid case. This may be ascribed to various complications in solids, anisotropy, elastic effects, etc.

Noncoherent receiver employing a dual-maxima metric generation process

Abstract: A method and apparatus for decoding an orthogonally encoded data signal in a noncoherent receiver system. The method is referred to as dual-maxima metric generation. It comprises the steps of sequentially searching for a maximum energy level in each of two subsets of a given set of symbol indexes and associated energy levels and calculating a difference of the two values to form a soft decision output value. The two subsets are identified by the binary value (either "0" or "1") of a given digit of the binary equivalent of the symbol index. The soft decision output value reflects a measure of confidence of the value of the corresponding digit of the original signal. The dual-maxima generator sequences through the steps one time for each binary digit of the original signal. The method allows the correlated energy from multiple receivers to be combined before the decoding of the signals, thus further reducing the complexity of the circuitry and improving the performance of the decoder.

Cluster analysis by binary morphology

Abstract: An approach to unsupervised pattern classification that is based on the use of mathematical morphology operations is developed. The way a set of multidimensional observations can be represented as a mathematical discrete binary set is shown. Clusters are then detected as well separated subsets by means of binary morphological transformations. >

Device for generating binary sequences for stochastic computing

Abstract: A novel technique for the generaion of high speed stochastic bit streams in which the '1' density is proportional to a given value Bit streams of this type are particularly useful in bit serial stochastic computing systems, such as digital stochastic neural networks The proposed circuitry is highly suitable fot VLSI fabrication

A 17 /spl times/ 69 bit multiply and add unit with redundant binary feedback and single cycle latency

Abstract: The authors describe a numeric processor with a kernel that is a tree of redundant binary adders and effects either a 17 /spl times/ 69-b multiply-and-add or a 19 /spl times/ 69-b multiply with exact redundant binary output and single cycle latency. Feedback paths selectively allow a high-order or low-order part of the adder tree output to be fed back in redundant binary form to the multiplicand and/or addend inputs to the adder tree. The authors describe algorithms iteratively using this adder tree kernel for IEEE double extended multiplication, division, and square root; conversions between 18-digit BCD integers and 64-b binary integers; and transcendental function evaluation. The multiplier design described was implemented in the Cyrix 83D87 numeric coprocessor (typically 33 MHz). Results for this coprocessor as compared with competitive x87 units are included. >

Method of and apparatus for discriminating NaN

Abstract: When processing a binary floating-point number in the IEEE form, whether or not the data is NaN can be discriminated irrespective of a precision thereof. The binary floating-point number having sign, exponent and fraction parts is based on the IEEE form in which the data is defined as NaN on condition that "all values of respective bits of the exponent part are `1`, and all values of respective bits of the fraction part are not `0`". In this binary floating-point number, if a precision of the binary floating-point is the maximum precision, the data is set intactly as internal representation form data. If the precision is less than the maximum precision, the following transform is executed. The sign part is set as it is. The exponent part is extended to a number of bits of the exponent part of the maximum precision, and deficient bits due to this extension are filled with `1`. The fraction part is extended to a number of bits of the maximum precision, and deficient bits due to this extension are filled with `0`. A result of this transform turns out the internal representation form data. With this internal representation form data, a NaN discriminating process is performed en bloc on all the data as maximum precision data.

System and method for processing logic function and fault diagnosis using binary tree representation

Abstract: A design system of a logic circuit including a logic synthesis and processing unit and a set data processing unit. The set data processing unit includes a node table which records elements of a set. A control unit of the logic synthesis and processing unit reads set data from the node table, assigns a binary number to each element, and transfers them to a control unit of the set data processing unit. The control unit of the set data processing unit separates the set data in accordance with 0 and 1 of individual digits of the binary numbers, generates a 0-suppressed binary decision diagrams of a logic function, and stores them to the node table. In generating the 0-suppressed binary decision diagram, node sharing and 0-suppress node elimination are applied. The 0-suppress node elimination is applied to each intermediate node having edges e0 and e1, which are associated with 0 and 1 of each position of digits. When the edge e1 of an intermediate node points to a 0-terminal node, the intermediate node, the edge e1, and the 0-terminal node are eliminated, and an edge pointing the intermediate node is directly connected to e0 of the intermediate node. The 0-suppressed binary decision diagram is formed in the node table. A subset whose element number is considerably smaller than that of the entire set can be represented by a graph which includes a smaller number of nodes than a conventional binary decision diagram.

Context Tree Weighting : A Sequential Universal Source Coding Procedure for Fsmx Sources

Abstract: A binary FSMX source generates a given sequence of digits from {0, l} whose statistical behavior can be described using a postfix set S. This postfix set is a collection of binary strings which is proper and complete. To weigh an infinite number of models, the authors introduce a principle which says that the model-redundancy has to be proportional to the number of free parameters of the model. It gives us a weighting distribution over all models. A efficient method is outlines that weighs the block probabilities of all models according to this distribution.

Software data protection mechanism.

Abstract: A protection mechanism includes means for taking an input binary value and generating a unique key value as well as performing the reverse operation of taking a key value and generating an input binary value. The mechanism includes a scrambler which includes an array having a number of multibit container locations for storing a unique sequence of random numbers. The scrambler forms another binary value by rearranging the bits of the input binary value as a function of the random number values in addition to altering the states of such bits as a function of the random number values and the numeric bit position values of sources of the input binary bits. The resulting binary value is applied to an alphanumeric encoder which converts the binary value into a series of alphanumeric characters containing a valid key value.

An improved binary algorithm for RSA

Abstract: The normal form and modified normal form for binary redundant representations are defined. An improved binary algorithm to compute modular exponentiation for very large integers is proposed. It is shown that the proposed algorithm requires the minimum number of basic operations (modular multiplications) among all possible binary redundant representations. Compared to the binary algorithm, the proposed algorithm reduces the number of basic operations by 33%. Based on the proposed algorithm, a linear systolic array implementation of the RSA crytographic system is presented, in which the total number of processing elements required is significantly reduced, and better complexity merit in terms of product of area and time of systolic implementation is achieved compared with a previous design based on binary algorithm.

BCH error-location polynomial decoder

Abstract: An error correction circuit wherein the coefficients of the error-location polynomial σ(x) of any three-error correcting binary BCH code over the Galois Field GF(2 m ) are found from the first three odd components S 1 , S 3 , and S 5 of the syndrome vector. The circuit traverses a binary decision tree to find the polynomial coefficients and can be realized totally with combinational logic. The correct equation for the final polynomial coefficients is found at the termination of the tree. The descent through this tree and the computation of the coefficients can be performed by parallel combinational logic. Addition over the Galois Field is performed in the standard representation with exclusive OR gates. Multiplication can be performed by converting the standard representation into a special representation that is passed through a pair of binary adders to form the product. Translation can then be made back to the standard representation. The coefficients of the error-location polynomial appear at the output of the circuit after a time representing the total combinational logic delay of the circuit from the time the syndrome vector is applied to the input.

Apparatus for simultaneously convolving multiple digital binary images using a single convolver with a binary mask to determine pixel densities

Abstract: A system for simultaneously convolving first and second digital binary images in parallel with a single convolver having a binary mask. A first window is selected from the first digital binary image and a second window is selected from the second digital binary image. A first binary pixel is selected from the first window and a second binary pixel is selected from the second window. The first binary pixel is bit-shifted by concatenating a plurality of trailing zero bits to the first binary pixel. A multi-bit input pixel is formed by combining the bit-shifted first binary pixel and the second binary pixel. A single multi-bit output value is generated by simultaneously applying a plurality of multi-bit input pixels to a single convolver. A first convolution result is formed from only the least significant bits of the output value and a second convolution result is formed from only the most significant bits of the output value, wherein the first and second convolution results respectfully represent the results of sequentially applying a single convolver to the first and second windows.

Binary-mask generation for diffractive optical elements using microcomputers

Abstract: A new technique for generation of binary masks for the fabrication of diffractive optical elements is investigated. This technique, which uses commercially available desktop-publishing hardware and software in conjunction with a standard photoreduction camera, is much faster and less expensive than the conventional methods. The short turnaround time and low cost should give researchers a much greater degree of flexibility in the field of binary optics and enable wider application of diffractive-optics technology. Techniques for generating optical elements by using standard software packages that produce PostScript output are described. An evaluation of the dimensional fidelity of the mask reproduction from design to its realization in photoresist is presented.

Almost perfect binary functions

Abstract: The almost perfect binary sequences have been defined in [6] as (−1, +1)-periodic sequences such that all their out-of-phase autocorrelation coefficients are zero except one. In the preceding paper, the study of the almost perfect binary sequences is done by means of the ringF 2[X]/(X n −1). Here, the arithmetic of cyclotomic fields enables us to solve open problems and questions like: structure and existence of these sequences.

Digital circuit for the evaluation of mathematical expressions

Abstract: A digital circuit for determining the result of mathematical operations and functions when supplied with three binary values having a fixed number of binary bits which correspond to: (i) an initial left boundary limit of a first interval, (ii) an initial right boundary limit of a first interval, and (iii) a given working value.

Pattern formation caused by double quenches in binary polymer mixtures: Response of phase-separated structure to a second quench within a two-phase region

Abstract: Here we demonstrate the evolution of an unusual phase-separated pattern caused by a double quench: a first quench from a one-phase to a two-phase region and a subsequent second quench within the two-phase region The resulting pattern evolution strongly depends upon the type of a double-quench sequence A deeper second quench causes a level structure, while a shallower one causes a long-range interface instability coming from a mismatch in the local volume-surface ratio The response of a domain structure to a second quench is qualitatively discussed on the basis of the phase diagram and existing theories for the coarsening dynamics of usual phase separation

Second order effect of binary sources on characteristics of queue and loss rate

Abstract: A wideband source in high speed networks is typically represented by a binary random process. The second-order properties of each binary source are characterized here by a multistate Markov-modulated Poisson process. A comprehensive numerical study is carried out to identify the individual effect of source second-order dynamics on queue length and loss rate. The concept of input power spectrum is then developed as a unified source measurement for multimedia traffic queuing analyses. The authors thoroughly explore the relationship between the source second-order dynamics in the time domain and the input power spectrum in the frequency domain, as well as its overall impact on system performance. >

Efficient codebook structure for code excited linear prediction coding

Abstract: A speech communication system using a code excited linear prediction speech decoder. The decoder using a first codebook containing a first digital value sequence selected from the set of binary values {0, 1}. The decoder also using a second codebook containing a second digital value sequence having values selected from the set of binary values {−1, 0}. The first digital value sequence and the second digital value sequence are combined to become a third digital value sequence having a set of ternary values from the set of {−1, 0, 1}.

The binary bootstrap: inference with autocorrelated binary data

Abstract: We introduce the binary bootstrap for inference with autoconelated binary data. Weempirically evaluate the standard eirors and confidence intervals created with the binary bootstrap using four stochastic process with known results: Bernoulli trials, first-order Markov processes, and long customer delays in M/M/l and D/M/10 queues. The binary bootstrap has certain advantagesover the conventional batch means method for creating confidence intervals on the probability oflong delay using only one run of a discrete-event simulation

Experimental demonstration of binary chaos-shift keying using self-synchronising chua"s circuits

Abstract: Keywords: chaos ; Non-Linear Signal Processing Reference LANOS-CONF-1993-008 Record created on 2004-12-03, modified on 2017-05-12

Self-replicating sequences of binary numbers. Foundations II: Strings of length N=4

Abstract: We study an algorithm which allows sequences of binary numbers (strings) to interact with each other. The simplest system of this kind with a population of 4-bit sequences is considered here. Previously proposed folding methods are used to generate alternative two-dimensional forms of the binary sequences. The interaction of two-dimensional and one-dimensional forms of strings is simulated in a serial computer. The reaction network for the N = 4 system is established. Development of string populations initially generated randomly is observed. Nonlinear rate equations are proposed which provide a model for this simplest system.

Hardware implemented multiplier

Abstract: A sign inverting Booth encoder included in an encoding circuit generates a control signal designating a partial product having a sign different from that designated by an output signal generated from a conventional Booth encoder. A partial product generating circuit generates a partial product according to the control signal from the encoding circuit. A partial product having a sign inverted or non-inverted is generated from a shifter/inverter circuit. A converting circuit generates three-value redundant binary numbers using a sign inverted partial product and a sign non-inverted partial product as a set. An intermediate sum generating circuit performs a redundant binary addition of the three-value redundant binary numbers to generate a final redundant binary number. A final adding circuit converts the finally generated three-value redundant binary number into an ordinary binary number to generate a product Z of binary numbers X and Y. As a result, a multiplier performing multiplication at a high speed with a smaller number of elements is implemented.

Technique for generating sets of binary spreading-code sequences for a high data-rate spread-spectrum network

Abstract: A method and apparatus for electrically generating sets of binary spreading-code sequences for use in a multi-node communication network are disclosed. A method for assigning disjoint sets of binary spreading-code sequences to different nodes of such a network is also disclosed. Each set of binary spreading-code sequences consists of multiple sequences, which are generated using two binary shift registers. The sequences can be generated simultaneously, or sequence segments can be generated sequentially. To generate sequences simultaneously, the contents of multiple pairs of stages of two linear-feedback binary shift registers are combined by modulo-2 addition, where each pair of stages consists of one stage from each of the two binary shift registers. To generate sequence segments sequentially, the contents of a single stage of a first binary shift register are combined by modulo-2 addition with the contents of a single stage of a second binary shift register, where new fills are switched into each of the registers at the beginning of each period. To assign disjoint sets of binary spreading-code sequences to different nodes of the network, the initial fill of the first binary shift register is fixed and different initial fills are specified for the second binary shift register.

Method and apparatus for comparing two numbers

Abstract: A comparator circuit for comparing a first n-bit binary number to a second n-bit binary number to produce a signal indicating if the first n-bit binary number is greater than or equal to the second n-bit binary number. If the signal is in one logic state, then the first n-bit binary number is greater-than or equal to the second n-bit binary number. On the other hand, if the signal is in a second logic state, then the first n-bit binary number is not greater-than or equal to the second n-bit binary number.

Shaft alignment apparatus

Abstract: The specification discloses apparatus for aligning rotatable in-line machine shafts. In a preferred embodiment, the invention provides an alignment system having a sensed point positioned for rotation with the shaft to be aligned to provide a reference point against which misalignment is measured. The position of the sensed point is adjustable in three-dimensional space by an adjustment system so that the sensed point may be easily secured in a desired location to eliminate errors attributable to movement of the sensed point or improper location of the sensed point. In addition, the alignment system provides a capacitive displacement system to more accurately sense the sensed point, binary blocks to facilitate proper vertical positioning of the sensed point, and an improved chain assembly to facilitate mounting of the alignment system and to reduce errors of the type common to conventional alignment systems.

Algorithms and multi-valued circuits for the multioperand addition in the binary stored-carry number system

Abstract: Algorithms for the sum of two (three and four) digits in the binary stored-carry number system, using the smallest set of values for the positional sum, are presented. The corresponding adders, which use multivalued current-mode circuits, are also presented. The implementation of multioperand additions using these adders is compared with the usual binary implementation. >