Showing papers on "Binary number published in 1995"

Verification of Arithmetic Circuits with Binary Moment Diagrams

Abstract: Binary Moment Diagrams (BMDs) provide a canonical representations for linear functions similar to the way Binary Decision Diagrams (BDDs) represent Boolean functions. Within the class of linear functions, we can embed arbitrary functions from Boolean variables to integer values. BMDs can thus model the functionality of data path circuits operating over word-level data. Many important functions, including integermultiplication, that cannot be represented efficiently at the bit level with BDDs have simple representations at the word level with BMDs. Furthermore, BMDs can represent Boolean functions with around the same complexity as BDDs. We propose a hierarchical approach to verifying arithmetic circuits, where componentmodules are first shownto implement their word-level specifications. The overall circuit functionality is then verified by composing the component functions and comparing the result to the word-level circuit specification. Multipliers with word sizes of up to 256 bits have been verified by this technique.

A high-speed realization of a residue to binary number system converter

Abstract: This paper proposes a new high-speed ROM-less residue-to-binary converter for the three moduli residue number systems (RNS) of the form. >

Binary polynomial transforms and nonlinear digital filters

Abstract: Part 1 Binary polynomial transforms: binary polynomial arithmetical and logical functions and matrices fast algorithms and complexity of binary polynomial transforms logical correlations and binary polynomial transforms. Part 2 Binary polynomial transforms and digital logic: spectral methods in analysis of Boolean functions spectral methods in minimization of Boolean functions. Part 3 Applications in nonlinear digital filtering: median and order statistic filters weighted order statistic and stack filters statistical properties of stack filters.

Method for reducing temporal artifacts in digital video systems

Abstract: A method and system for improved display of digital video data. The data is arranged into bit planes according to the binary weight of each bit per pixel. The bit planes are then translated into non-binary weighted bit planes by bit translation circuitry (22). These non-binary bit planes are transmitted to the activation circuitry of a spatial light modulator array (30), such that each non-binary bit is displayed at symmetrical times around at least one predetermined point within a video frame time, eliminating visual artifacts associated with binary pulse-width modulation.

Digital variable in-lock range phase comparator

Abstract: A novel method and apparatus providing an all digital phase comparator of two binary signals which employs a type of cross correlation of two binary signals and provides a 2bit binary word uniquely representative of phase alignment The method can be carried out using a pair of flip-flop (FF) circuits, each FF having a docking input and a data input, and where each FF has a delay in series with its data input

Device and a method for storing data and corresponding error-correction information

Abstract: The invention relates to a multi-level storage device including: at least a first plurality of cells storing an identical first number (greater than one) of binary data, and at least a corresponding for second plurality of cells for storing a second number of error check and correcting words equal to said first number, said words being respectively associated with sets of binary data, each including at least one binary data for each cell in said first plurality. In this way, many of the known error correction algorithms can be applied to obtain comparable results to those provided by binary memories. In addition, where multi-level cells are used for storing the error check and correcting words, the device dimension requirements can also be comparable.

Free energy minimisation algorithm for decoding and cryptanalysis

Abstract: An algorithm is derived for inferring a binary vector s given noisy observations of As modulo 2, where A is a binary matrix. The binary vector is replaced by a vector of probabilities, optimised by free energy minimisation. Experiments on the inference of the state of a linear feedback shift register indicate that this algorithm supersedes the Meier and Staffelbach polynomial algorithm.

Spread spectrum digital screening

Abstract: A spread spectrum digital screening mask and a method and system for digital screening a continuous tone image with the spread spectrum digital screening mask. The mask is characterized in the frequency domain by a function in magnitude independent of angle within a band of frequencies between a minimum frequency and a maximum frequency. The mask may be further characterized by its thresholded binary planes at each of a plurality of predetermined threshold values. The binary planes are characterized in frequency domain by magnitudes primarily distributed within the band of frequencies. For each binary plane, the number of pixels having one of the binary values divided by the total number of pixels in the binary plane equals a fraction determined by the predetermined threshold value of the binary plane divided by the maximum threshold value.

Efficient workspace generation for binary manipulators with many actuators

Abstract: Binary actuators have only two discrete states, both of which are stable without feedback. As a result, manipulators with binary actuators have a finite number of states. Major benefits of binary actuation are that extensive feedback control is not required, task repeatability can be very high, and two-state actuators are generally very inexpensive, thus resulting in low-cost robotic mechanisms. Determining the workspace of a binary manipulator is of great practical importance for a variety of applications. For instance, a representation of the workspace is essential for trajectory tracking, motion planning, and the optimal design of binary manipulators. Given that the number of configurations attainable by binary manipulators grows exponentially in the number of actuated degrees of freedom, 0(2), brute force representation of binary manipulator workspaces is not feasible in the highly actuated case. This article describes an algorithm that performs recursive calculations starting at the end-effector and terminating at the base. The implementation of these recursive calculations is based on the macroscopically serial structure and the discrete nature of the manipulator. As a result, the method is capable of approximating the workspace in linear time, O(n), where the slope depends on the acceptable error. © 1995 John Wiley b Sons, Inc.

Efficient construction of binary moment diagrams for verifying arithmetic circuits

Abstract: BDD-based approaches cannot handle some arithmetic functions such as multiplication efficiently, while Binary Moment Diagrams proposed by Bryant and Chen (1994) provide compact representations for those functions. They reported a BMD-based polynomial-time algorithm for verifying multipliers. This approach requires high-level information such as specifications to subcomponents. This paper presents a new technique called backward construction which can construct BMDs directly from circuit descriptions without any high-level information. The experiments show that the computation time for verifying for n-bit multipliers is approximately n/sup 4/. We have successfully verified 64-bit multipliers of several type in 3-6 hours with 46 Mbyte of memory on SPARCstation 10/51. This result outperforms previous BDD-based approaches for verifying multipliers.

Estimation of the post-Newtonian parameters in the gravitational-wave emission of a coalescing binary.

Abstract: The effect of the recently calculated second post-Newtonian correction on the accuracy of the estimation of the parameters of the gravitational-wave signal from a coalescing binary is investigated. It is shown that the addition of this correction degrades considerably the accuracy of the determination of the individual masses of the members of the binary. However the chirp mass and the time parameter in the signal are still determined to a very good accuracy. The possibility of estimating the effects of other theories of gravity is investigated. The performance of the Newtonian filter is investigated and it is compared with the performance of post-Newtonian search templates introduced recently. It is shown that both search templates can extract accurately useful information about the binary.

Binary image synthesis using mixed linear integer programming

Abstract: Images that are to be transmitted through a distorting imaging system may be deliberately altered to compensate for that distortion. The authors consider an incoherent diffraction-limited imaging system followed by an ideal high-contrast detector that prints binary images, and seek a binary input image (a mask) that generates a desired prescribed binary output image. They have developed a method for determining the optimal binary mask by formulating the problem as a mixed linear integer program (MLIP) and using the branch and bound method to solve it. >

Optimal binary index assignments for a class of equiprobable scalar and vector quantizers

Abstract: The problem of scalar and vector quantization in conjunction with a noisy binary symmetric channel is considered. The issue is the assignment of the shortest possible distinct binary sequences to quantization levels or vectors so as to minimize the mean-squared error caused by channel errors. By formulating the assignment as a matrix (or vector in the scalar case) and showing that the mean-squared error due to channel errors is determined by the projections of its columns onto the eigenspaces of the multidimensional channel transition matrix, a class of source/quantizer pairs is identified for which the optimal index assignment has a simple and natural form. Among other things, this provides a simpler and more accessible proof of the result of Crimmins et al. (1969) that the natural binary code is an optimal index assignment for the uniform scalar quantizer and uniform source. It also provides a potentially useful approach to further developments in source-channel coding.

Redundant binary Booth recoding

Abstract: We investigate the efficiencies attainable pursuing Booth recoding directly from redundant binary input with limited carry propagation. As a digit conversion problem we extend the important result that each radix 4 Booth recoded digit can be determined from 5 consecutive input signed bits to obtain that each radix 2/sup k/ Booth recoded digit can be determined from 2k+1 consecutive input signed bits and prove this to be the minimum possible for any k/spl ges/2. Analysis of alternative bit pair encodings of signed bits yields the improved result that each radix 2/sup k/ Booth recoded digit can be determined from only 2k encoded bit pairs employing sign and magnitude bit encoding, a result which does not extend to conventional borrow-save or carry-save redundant binary digit encodings. Radices 4 and 8 gate level designs are illustrated for alternative encodings, with our signed bit design shown to yield smaller depth and fewer gates than existing redundant binary Booth recoding circuits from the literature. >

Method and apparatus for motion estimation in a video signal

Abstract: A method and apparatus for motion estimation in a video signal includes an edge detector for generating present and reference binary edge bit maps and a binary block matcher for receiving the present and reference binary edge bit maps from the edge detector and for generating a motion vector for each of a plurality of blocks in the binary edge bit maps. By using binary edge bit map data to generate motion vectors, computational requirements are reduced. If the apparatus is provided as an integrated circuit, the technique of the present invention reduces cost, power requirements and size of the integrated circuit.

An RNS to binary converter in a three moduli set with common factors

Abstract: This paper describes a residue number to binary converter that converts numbers in the moduli set 2n+2, 2n+1, 2n with 2 as a common factor. An algorithm and a hardware implementation for the converter are proposed. The hardware implementation uses Chinese Remainder Theorem (CRT) and this has been made possible by mapping the moduli set into a pairwise relatively prime integers to satisfy CRT requirements. Properties of modular arithmetic are used to reduce the complexity of the multipliers in the proposed hardware. The converter does not use any explicit module operation in the evaluation as is normally done in implementations that use CRT. >

A constructive algorithm for binary neural networks: the oil-spot algorithm

Abstract: This paper presents a constructive training algorithm for supervised neural networks. The algorithm relies on a topological approach, based on the representation of the mapping of interest onto the binary hypercube of the input space. It dynamically constructs a two-layer neural network by involving successively binary examples. A convenient treatment of real-valued data is possible by means of a suitable real-to-binary codification. In the case of target functions that have efficient halfspace union representations, simulations show the constructed networks result optimized in terms of number of neurons. >

Word Level Symbolic Model Checking: A New Approach for Verifying Arithmetic Circuits

Abstract: The highly-publicized division error in the Pentium has emphasized the importance of formal verification of arithmetic operations. Symbolic model checking techniques based on binary decision diagrams (BDDs) have been successful in verifying control logic. However, lack of proper representation for functions that map boolean vectors into integers has prevented this technique from being used for verifying arithmetic circuits. We have used hybrid decision diagrams to represent the integer functions that occur in the arithmetic circuit verification. For the state variables corresponding to data bits, our representation behaves like a binary moment diagram (BMD) while for the state variables corresponding to control signals, it behaves like a multi-terminal BDD (MTBDD). By using this representation, we are able to handle circuits with both control logic and wide data paths. We have extended the symbolic model checking system SMV so that it can also handle properties involving relationships among data words. In the original SMV system, atomic formulas could only contain state variables. In the extended system, we allow atomic formulas to be equations or inequalities between expressions as well. These expressions are represented as hybrid decision diagrams. The extended model checking system enables us to verify circuits for division and square root computation that are based on the SRT algorithm used by the Pentium. We are able to handle both the control logic and the data paths. The total number of state variables exceeds 600 (which is much larger than any circuit previously checked by SMV).

Signal comprising binary spreading-code sequences

Abstract: A method and apparatus for electrically generating sets of binary spreading-code sequences for use in a multi-node communication network. Also, a method for assigning disjoint sets of binary spreading-code sequences to different nodes of such a network. Each set of binary spreading-code sequences consists of multiple sequences, which are generated using two binary shift registers. The sequences can be generated simultaneously, or sequence segments can be generated sequentially. To generate sequences simultaneously, the contents of multiple pairs of stages of two linear-feedback binary shift registers are combined by modulo-2 addition, where each pair of stages consists of one stage from each of the two binary shift registers. To generate sequence segments sequentially, the contents of a single stage of a first binary shift register are combined by modulo-2 addition with the contents of a single stage of a second binary shift register, where new fills are switched into each of the registers at the beginning of each period. To assign disjoint sets of binary spreading-code sequences to different nodes of the network, the initial fill of the first binary shift register is fixed and different initial fills are specified for the second binary shift register.

Adaptable binary programs

Abstract: To accurately and comprehensively monitor a program's behavior, many performance measurement tools transform the program's executable representation or binary. By instrumenting binary programs to monitor program events, tools can precisely analyze compiler optimization effectiveness, memory system performance, pipeline interlocking, and other dynamic program characteristics that are fully exposed only at this level. Binary transformation has also been used to support software-enforced fault isolation, debugging, machine re-targeting, and machine-dependent optimization. At present, binary transformation applications face a difficult trade-off. Previous approaches to implementing robust transformations result in significant disk space and run-time overhead. To improve efficiency, some current systems sacrifice robustness, relying on heuristic assumptions about the program and recognition of compiler-dependent code generation idioms. In this paper we begin by investigating the run-time and disk space overhead of transformation strategies that do not require assumptions about the program's control flow or register usage. We then detail simple information about the binary program that can significantly reduce this overhead. For each type of information, we show how it enables a corresponding type of binary transformation. We call binary programs that contain such enabling information adaptable binaries. Because adaptable binary information is simple, any compiler can generate it. Despite its simplicity, adaptable binary information has the necessary and sufficient expressive power to support a rich set of binary transformations.

Low power and high speed multiplication design through mixed number representations

Abstract: A low power multiplication algorithm and its VLSI architecture using a mixed number representation is proposed. The reduced switching activity and low power dissipation are achieved through the Sign-Magnitude (SM) notation for the multiplicand and through a novel design of the Redundant Binary (RB) adder and Booth decoder. The high speed operation is achieved through the Carry-Propagation-Free (CPF) accumulation of the Partial Products (PP) by using the RB notation. Analysis showed that the switching activity in the PP generation process can be reduced on average by 90%. Compared to the same type of multipliers, the proposed design dissipates much less power and is 18% faster on average.

Planar multiple-valued decision diagrams

Abstract: In VLSI, crossings occupy space and cause delay. Therefore, there is significant benefit to planar circuits. We propose the use of planar multiple-valued decision diagrams to produce planar multiple-valued circuits. Specifically, we show conditions on 1) threshold functions, 2) symmetric functions, and 3) monotone increasing functions that produce planar decision diagrams. Our results apply to binary functions, as well. For example, we show that all two-valued monotone increasing threshold functions of up to five variables have planar binary decision diagrams.

A complex-number multiplier using radix-4 digits

Abstract: This paper describes the design of a 16/spl times/16 complex-number multiplier developed as part of the arithmetic datapath of a complex-number digital signal processor. The complex-number multiplier internally uses binary signed digits for fast multiplication and compact layout. It employs the traditional three-multiplication scheme while minimizing the logic and delay associated with the three extra pre-multiplication binary additions which that scheme requires. The minimization comes from producing the redundant binary sum for each of the pre-multiplication binary additions with minimal hardware, and then recoding the redundant sums as radix-4 multiplier operands. The radix-4 operands halve the number of summands to be added in each of the three real multiplier units. Furthermore, an additional factor of two reduction in the number of summands is effectuated by our coding scheme for representing binary signed digits. The result is a fast and compact complex-number multiplier. >

Applications of Multi-Terminal Binary Decision Diagrams

Abstract: Functions that map boolean vectors into the integers are important for the design and verification of arithmetic circuits. MTBDDs and BMDs have been proposed for representing this class of functions. We discuss the relationship between these methods and describe a generalization called hybrid decision diagrams which is often much more concise. The Walsh transform and Reed-Muller transform have numerous applications in computer-aided design, but the usefulness of these techniques in practice has been limited by the size of the boolean functions that can be transformed. Currently available techniques limit the functions to less than 20 variables. In this paper, we show how to compute concise representations of the Walsh transform and Reed-Muller transform for functions with several hundred variables. We show how to implement arithemetic operations efficiently for hybrid decision diagrams. In practice, this is one of the main limitations of BMDs since performing arithmetic operations on functions expressed in this notation can be very expensive. In order to extend symbolic model checking algorithms to handle arithmetic properties, it is essential to be able to compute the BDD for the set of variable assignments that satisfy an arithmetic relation. Bryant and Chen do not provide an algorithm for this. In our paper, we give an efficient algorithm for this purpose. Moreover, we prove that for the class of linear expressions, the time complexity of our algorithm is linear in the number of variables. Our techniques for handling arithmetic operations and relations are used intensively in the verification of an SRT division algorithm similar to the one that is used in the Pentium.

Half tone display method

Abstract: PROBLEM TO BE SOLVED: To prevent deterioration in picture quality of dynamic images in the case of using the sub-field method. SOLUTION: In the half-tone display method which concurrently displays plural binary digital images that are formed by weighting half-tone dynamic images depending on the time width or the number of pulses, the portion corresponding to high-order plural bits of the half-tone represented by binary notation is displayed by continuous time-width- or pulse-number modulation using plural binary images roughly equally weighted and the portion corresponding to the remaining low-order bits is displayed by binary images weighted in compliance with binary notation.

Application of SKIPSM to binary correlation

Abstract: Binary correlation is often used for finding specified patterns in complex binary images, especially in industrial inspection tasks such as locating the corners and/or edges of parts. As such, it is an important tool for higher-level 'intelligent' vision systems. Binary correlation is a form of binary template matching which provides a numerical value corresponding to 'degree of fit' rather than an 'all or nothing' answer. Commercially available high-speed image processing systems can readily perform this operation using linear convolvers, but such convolvers are very expensive except for very small kernels. Furthermore, linear convolvers constitute a gross 'overkill' for the relatively simple operation of binary correlation. Specialized binary convolvers have been built, but are not part of standard commercial systems. This paper describes a new pipelined implementation of binary correlation which fits into the standard SKIPSM (separated-kernel image processing using finite state machines) architecture and which can be built using standard ICs costing less than $500 total. The same approach can also be implemented in software, providing an order-of-magnitude increase in speed at no extra cost. Furthermore, this same SKIPSM architecture is highly versatile and programmable, allowing it to be software-reconfigured to perform hundreds of other pipelined image processing operations.© (1995) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

On the conversion between binary code and binary-reflected Gray code on binary cubes

Abstract: We present a new algorithm for conversion between binary code and binary-reflected Gray code that requires approximately 2 K/3 element transfers in sequence for K elements per node, compared to K element transfers for previously known algorithms. For a binary cube of n=2 dimensions the new algorithm degenerates to yield a complexity of 2 K/+1 element a transfers, which is optimal. The new algorithm is optimal to within a multiplicative factor of 4/3 with respect to the best known 3 lower bound for any routing strategy. We show that the minimum number of element transfers for minimum path length routing is K with concurrent communication on all channels of every node of a binary cube. >