Showing papers on "Binary number published in 1996"

Long-term Stability of Planets in Binary Systems

Abstract: A simple question of celestial mechanics is investigated: in what regions of phase space near a binary system can planets persist for long times? The planets are taken to be test particles moving in the field of an eccentric binary system. A range of values of the binary eccentricity and mass ratio is studied, and both the case of planets orbiting close to one of the stars, and that of planets outside the binary orbiting the systems center of mass, are examined. From the results, empirical expressions are developed for both (1) the largest orbit around each of the stars and (2) the smallest orbit around the binary system as a whole, in which test particles survive the length of the integration (10A4 binary periods). The empirical expressions developed, which are roughly linear in both the mass ratio mu and the binary eccentricity e, are determined for the range 0.0=e=0.7-0.8 and 0.1=mu=0.9 in both regions and can be used to guide searches for planets in binary systems. After considering the case of a single low-mass planet in binary systems, the stability of a mutually interacting system of planets orbiting one star of a binary system is examined, though in less detail.

An efficient tree architecture for modulo 2 n + 1 multiplication

Abstract: Modulo 2n+1 multiplication plays an important role in the Fermat number transform and residue number systems; the diminished-1 representation of numbers has been found most suitable for representing the elements of the rings. Existing algorithms for modulo (2n+1) multiplication either use recursive modulo (2n+1) addition, or a regular binary multiplication integrated with the modulo reduction operation. Although most often adopted for largen, this latter approach requires conversions between the diminished-1 and binary representations. In this paper we propose a parallel fine-grained architecture, based on a Wallace tree, for modulo (2n+1) multiplication which does not require any conversions; the use of a Wallace tree considerably improves the speed of the multiplier. This new architecture exhibits an extremely modular structure with associated VLSI implementation advantages. The critical path delay and the hardware requirements of the new multiplier are similar to that of a correspondingn×n bit binary multiplier.

Multi-Terminal Binary Decision Diagrams and Hybrid Decision Diagrams

Abstract: Functions that map vectors with binary values into the integers are important for the design and verification of arithmetic circuits We demonstrate how multi-terminal binary decision diagrams (MTBDDs) can be used to represent such functions concisely The Walsh transform and Reed-Muller transform have numerous applications in computer-aided design, but the usefulness of these techniques in practice has been limited by the size of the binary valued functions that can be transformed We show how to compute the MTBDD representations of the Walsh transform and Reed-Muller transform for functions with several hundred variables Bryant and Chen have proposed binary moment diagrams (BMDs) for representing the class of functions that we have considered We discuss the relationship between these methods and describe a generalization called hybrid decision diagrams which is often much more concise

Optimum decision scheme with a unitary control process for binary quantum-state signals.

Abstract: A scheme for distinguishing between binary signals of nonorthogonal coherent states with the minimum average error is proposed. In contrast to the well-known Dolinar scheme, it does not use a feedback process. Instead, it achieves the same minimum error bound by only unitary transformations and photon number counting. It is shown that the required transformation should produce the appropriate Schr\"odinger-cat states. An example of the Hamiltonian generating such a process is derived from a multiphoton nonlinear optical process. \textcopyright{} 1996 The American Physical Society.

Conservative arrays: multidimensional modulation codes for holographic recording

Abstract: In holographic storage, two-dimensional arrays of binary data is optically recorded in a medium via an interference process. To ensure optimum operation of a holographic recording system, it is desirable that the patterns of 1s (light) and 0s (no light) in the recorded array satisfy the following modulation constraint: in each row and column of the array there are at least t transitions of the type 1/spl rarr/0 or 0/spl rarr/1, for a prescribed integer t. A two-dimensional array with this property is said to be a conservative array of strength t. In general, an n-dimensional conservative array of strength t is a binary array having at least t transitions in each column, extending in any of the n dimensions of the array. We present an algorithm for encoding unconstrained binary data into an n-dimensional conservative array of strength t. The algorithm employs differential coding and error-correcting codes. Using n binary codes-one per dimension-with minimum Hamming distance d/spl ges/2t-3, we apply a certain transformation to an arbitrary information array which ensures that the number of transitions in each dimension is determined by the minimum distance of the corresponding code.

A binary block matching architecture with reduced power consumption and silicon area requirement

Abstract: Motion estimation is essential for reducing bit rate by exploiting the temporal redundancy existent in image sequences. MPEG, one of the current standards for video coding, specifies the use of block matching (BM) for motion estimation. Conventional block matching is based on the mean-absolute difference (MAD) distortion metric, which requires a large number of 8-bit arithmetic computations and thereby limits wider usage. This paper examines the possibility of using a binary distortion metric based on contour data to reduce the silicon area and power consumption of the block matching chip by a factor of 5 or more. Our simulation results indicate that the performance of the proposed binary system for a restricted class of sequences, such as "head-and-shoulder" images, is very close to that of conventional gray level methods. Detailed design of the binary block matching (BBM) chip is currently underway. Potential applications include low power, portable video devices and machine vision applications such as stereo matching and template matching.

Detection of binary Markov sources over channels with additive Markov noise

Abstract: We consider maximum a posteriori (MAP) detection of a binary asymmetric Markov source transmitted over a binary Markov channel. The MAP detector observes a long (but finite) sequence of channel outputs and determines the most probable source sequence. In some cases, the MAP detector can be implemented by simple rules such as the "believe what you see" rule or the "guess zero (or one) regardless of what you see" rule. We provide necessary and sufficient conditions under which this is true. When these conditions are satisfied, the exact bit error probability of the sequence MAP detector can be determined. We examine in detail two special cases of the above source: (i) binary independent and identically distributed (i.i.d.) source and (ii) binary symmetric Markov source. In case (i), our simulations show that the performance of the MAP detector improves as the channel noise becomes more correlated. Furthermore, a comparison of the proposed system with a (substantially more complex) traditional tandem source-channel coding scheme portrays superior performance for the proposed scheme at relatively high channel bit error rates. In case (ii), analytical as well as simulation results show the existence of a "mismatch" between the source and the channel (the performance degrades as the channel noise becomes more correlated). This mismatch is reduced by the use of a simple rate-one convolutional encoder.

A combinatorial approach to trajectory planning for binary manipulators

Abstract: Binary manipulators are powered by actuators which have only two stable states. Therefore, they can reach only a discrete (but possibly large) number of locations. Compared to a manipulator built with continuous actuators, a binary manipulator provides reasonable performance, and is relatively inexpensive (up to an order of magnitude cheaper). The number of states of a binary manipulator grows exponentially with the number of actuators. This makes the calculation of its inverse kinematics quite difficult. This paper presents a combinatorial method for computing the inverse kinematics of a binary manipulator that reduces the search space to a manageable size. It also creates reasonably smooth motions that follow a specified trajectory accurately (in both position and orientation), despite the discrete nature of binary actuation.

An efficient method for computing the forward kinematics of binary manipulators

Abstract: Binary actuators have only two discrete states (denoted '0' and '1'), both of which are stable without feedback. As a result, manipulators built with binary actuators have a finite number of states. Compared to a manipulator built with continuous actuators, a binary manipulator provides good performance, and is also relatively inexpensive. However, the number of states of a binary manipulator grows exponentially with the number of actuators. While this makes the calculation of its inverse kinematics quite difficult, the discrete nature of a binary manipulator makes it possible to compute its forward kinematics more efficiently than for a continuously actuated manipulator. By pre-computing all possible configurations of each module of a binary manipulator (a finite and usually small number) it is possible to compute the forward kinematics from a set of joint parameters without using any transcendental functions.

Improved binary codes and sequence families from Z/sub 4/-linear codes

Abstract: A bound on exponential sums over Galois rings is used to construct a nested chain of Z/sub 4/-linear binary codes and binary sequences. When compared with the chain of Delsarte-Goethals'(1975) codes, the codes in the new chain offer a larger minimum distance for the same code size. The binary sequence families constructed also make use of Nechaev's (1991) construction of a cyclic version of the Kerdock code. For a given value of maximum correlation, the binary sequences are shown to have a family size considerably larger than the best sequence families known.

ACV: an arithmetic circuit verifier

Abstract: Based on a hierarchical verification methodology, we present an arithmetic circuit verifier ACV, in which circuits expressed in a hardware description language, also called ACV, are symbolically verified using Binary Decision Diagrams for Boolean functions and multiplicative Binary Moment Diagrams (*BMDs) for word-level functions. A circuit is described in ACV as a hierarchy of modules. Each module has a structural definition as an interconnection of logic gates and other modules. Modules may also have functional descriptions, declaring the numeric encodings of the inputs and outputs, as well as specifying their functionality in terms of arithmetic expressions. Verification then proceeds recursively, proving that each module in the hierarchy having a functional description, including the top-level one, realizes its specification. The language and the verifier contain additional enhancements for overcoming some of the difficulties in applying *BMD-based verification to circuits computing functions such as division and square root. ACV has successfully verified a number of circuits, implementing such functions as multiplication, division, and square root, with word sizes up to 256 bits.

A new method for conversion of a 2's complement to canonic signed digit number system and its representation

Abstract: A new technique is developed to generate canonic sign digit numbers. The technique is shown to be computationally simple and fast. In addition, a binary representation of CSD numbers, known as binary coded CSD (BCSD) number, is also presented. It is shown that a BCSD number uniquely represents its equivalent 2's complement number in the same size data-word. This property allows conversion of the number onto itself with no extra space added. An algorithm is developed to directly convert a 2's complement number to its BCSD equivalent.

Recurrent adrithmetical computation using carry-save arithmetic

Abstract: An arithmetic unit keeps a result in carry-save form and uses this form of the result as an input to the next iteration in recurrent computations. The full adder in the recurrent path is eliminated by implementing multiplication by Y(i), where Y(i) is available only in carry-save form. The carry-save arithmetic unit generates a plurality of partial products whose sum is the product AXB, where A is one binary input and B is either a second binary input B' or the sum C'+S' of two binary inputs C' and S'. A selection is made as to whether B is equal to B' or C'+S'. The plurality of partial products and an addition input Z are compressed to two partial products C and S whose sum C+S equals the sum of the plurality of partial products and Z. The partial products C and S are added to produce a binary result X equal to A×B+Z. The full adder in the recurrent path is eliminated by a feedback path which returns the partial products C and S to the inputs C' and S' for a next iteration.

Low cost sorting circuit for VLSI

Abstract: A new circuit for sorting binary numbers is presented. The new circuit is developed to implement a parallel bubble sort from one recently proposed for determining the maximum of n binary numbers.

On the estimation of parameters of the gravitational-wave signal from a coalescing binary by a network of detectors

Abstract: Estimation of parameters of the gravitational-wave signal from a coalescing binary by a network of laser interferometers is considered. A solution of the inverse problem for the network of three detectors is generalized to the network of N detectors. This enables, from measurements at individual detectors of the network, optimal estimation of the astrophysically interesting parameters of the binary system: its distance from Earth, its position in the sky, and the chirp mass of the system. Maximum likelihood and least-squares methods are used to obtain the solution. The existence of the solution in view of the nonlinear nature of the problem and the noise in the detectors is discussed. An alternative solution of the inverse problem that circumvents the singularities present in the problem is proposed. Accuracy of the estimation of the parameters is assessed from the inverse of the Fisher information matrix. The variance of the maximum likelihood estimator of the distance is calculated for a simple model and compared with the approximate one obtained from the Fisher matrix. Extensive Monte Carlo simulations are performed to assess the accuracy of the estimation of the astrophysical parameters by networks of three and four detectors. Addition of the fourth detector to the network markedly improves the performance of the network. Adding the fourth node in Australia to the LIGO/VIRGO network increases the number of detectable events roughly twofold. For the four-detector network one can find among all detectable events again roughly twice the number of events for which accurate determination of the binary distance is possible. Moreover, the position of the binary in the sky can be typically determined three to four times more accurately for the enhanced LIGO/VIRGO network.

4 bit based binary encoding technique

Abstract: An encoding method employs sixteen basic values, twelve numerical magnitudes and four directional modifiers. These values are the result combining binary digits in sets of 4 bits. The encoding method is utilized for encoding letters, symbols and programming commands. Letters are defined as numerical magnitudes altered by a directional modifier, symbols and commands are addressed as numerical magnitudes altered by two or more directional modifiers. An analog to digital encoding technique converts analog data into binary form by means of "breaking" an analog wave into a multitude of periodic waves, each wave with a particular wave-break, wave length and amplitude, supplying hence, an efficient and economical method for processing and storing binary information. An analog device describes the particular position of the sun at a given time, supplying therefor an apparatus that not only measures time but also describes space.

VLSI architectures for multiplication in GF(2/sup m/) for application tailored digital signal processors

Abstract: Finite field arithmetic plays an important role in coding theory, cryptography and their applications. Several hardware solutions using finite field arithmetic have already been developed but none of them are user programmable. This is probably one reason why BCH codes are not commonly used in mobile communication applications even though these codes have very desirable properties regarding burst error correction. This article presents architectures for multiplication in GF(2/sup m/) applicable to digital signal processors. First a method is proposed to build an array of gates for hardware multiplication in GF(2/sup m/). Then an approach is shown that combines the hardware of a typical standard binary arithmetic multiplier with a GF(2/sup m/) multiplier. Using this approach saves a considerable number of gates and decreases the bus load while increasing the latency of the standard binary multiplier unit only marginally. Finally, a solution of a combined 17/spl times/17 integer/GF(2/sup m/spl les/8/) multiplier is presented and discussed.

A fast, efficient parallel-acting method of generating functions defined by power series, including logarithm, exponential, and sine, cosine

Abstract: A fundamental parallel procedure of implementing certain algorithms is by means of trees and arrays. A method of generating any function defined by a power series in a fast, efficient parallel-acting manner using trees and arrays is described. The power series considered can be written as f(Y)=a/sub 0/+a/sub 1/Y+a/sub 2/Y/sup 2/+...where Y=v/sub 1/x+V/sub 2/x/sup 2/+...+v/sub k/x/sup k/,v/sub i/=(0, 1), is a binary fraction when x=1/2. The power series must be expanded into individual terms cx/sup 1/. These terms are then transformed into weighted binary terms. Two methods are given to obtain all the individual terms (including coefficients) associated with each power of x. The hardware required for implementation is a tree similar to a Wallace or Dadda tree used for parallel multiplication of two binary numbers. Despite the multiplicity of terms required, Boolean logic methods reduce the tree dimensions in many cases so that the total tree required is smaller than an existing multiplier tree. In that case, Schwarz and Flynn (1993), have shown that the required tree can be superimposed on the existing multiplier tree in a multiplexed manner with relatively little increase in hardware. The generation of the logarithmic function is described in detail. Comparisons with other methods are made for the case of 11 bit accuracy of the logarithm. Using a figure of merit of latency times area (number of transistors), estimates show that the superposition scheme gives the best (smallest) figure of merit. For 11 bit accuracy, the superposition scheme requires only about 480 additional gates to be superimposed upon a 41 bit or larger multiplier, and the speed of operation is that of the multiplier.

Punctured Elias Codes for Variable-Length Coding of the Integers

Abstract: The compact representation of integers is an important problem in areas such as data compression, especially where there is a nearly monotonic decrease in the likelihood of larger integers. While many different representations have been described, it is not always clear in which circumstances a particular code is to be preferred. This report introduces a variant of the Elias γ code which is shown to be better than other codes for some distributions. 1. Compact integer representations The efficient representation of symbols of differing probabilities is one of the classical problems of information theory and coding theory, with efficient solutions known since the early 1950’s (Shannon-Fano and Huffman codes[9]). In traditional, non-adaptive, coding we assume a priori probabilities of the input symbols and construct suitable codes to represent those symbols efficiently. There is no necessary or simple relation between a symbol and its representation. Here we are concerned with a different problem, especially as the symbol alphabet (integers of arbitrary upper bound) may be so large as to preclude the formal construction of an efficient code. Given an arbitrary integer we wish to represent it as compactly as possibly, preferably by an algorithm which recognises only the magnitude and bit pattern of the integer (no table lookup or mapping needed). Equally, a simple algorithm should be able to recover an integer from an input bit stream, even if that particular integer has never been seen before. The binary representation of the integer is often visible within the representation and other information is appended to indicate the length or precision. Many variable-length representations have been described; here we concentrate on just a few, emphasising those which have a simple relation between code and value and are instantaneous or nearly so. Following Elias[3], we first introduce two preliminary representations which are relatively unimportant per se, but are used in many other codes. • α(n) is the unary representation, n 0’s followed by a 1 (or 1’s followed by a 0) • β(n), is the natural binary representation of n, from the most significant 1. 1.1 Levenstein and Elias γ Codes These codes were first described by Levenstein[11], but the later description by Elias[3] is generally used in the English language literature. Elias describes a whole series of codes, with the α and β codes already described. His γ code writes the bits of the β code (the binary representation) in reverse order, with each preceded by a flag bit. All except the last flag bit are 0, with the last flag bit a 1 and implying the most-significant 1. Thus 13 is represented as 0100011, with the flag bits underlined. The γ' code is permutation of the γ code, with the flag bits (an α code) preceding the data bits (a β code). With this code, 13 is written as 0001101 (the terminator of the α code doubles as the first bit of the β code). For most of this document the term “Elias γ code” will be used interchangeably for the two variants; often it will actually mean the γ' code. An integer of N significant bits is represented in 2N+1 bits, or an integer n is represented by 2log n+1 bits 1 . (It is convenient to ignore the floor and ceiling operators in future discussions 1 All logarithms will be to base 2, without stating an explicit base. Tech Rep 137 December 5, 1996 page 1 to simplify the mathematics. Most of the discussion involves only order of magnitude considerations, or averages over many symbols so that precise values are relatively unimportant. We therefore say that an Elias code represents an integer n in 2 log n+1 bits.) n code n code 1 1 11 0001011 2 010 12 0001100 3 011 13 0001101 4 00100 14 0001110 5 00101 15 0001111 6 00110 16 000010000 7 00111 17 000010001 8 0001000 18 000010010 9 0001001 19 000010011 10 0001010 20 000010100 100 0000001100100 250 000000011111010 Table 1. Example of Elias' γ' code. The γ code can be extended to higher number bases where such granularity is appropriate. For example, numbers can be held in byte units, with each 8-bit byte containing 1 flag bit (lastbyte/more-to-come) and 7 data bits, to give a base-128 code. 1.2 Elias ω and Even-Rodeh codes All of the codes described here have a length part and a value part. In the γ code the length is given in unary; a natural progression is to specify the length itself in a variable-length code. Elias does this with his δ code, using a γ code for the length, but quickly proceeds to his ω codes. Some very similar codes were described by Even and Rodeh[4] and it is convenient to treat the two in parallel. Both of the codes have the value (as a β code) preceded by a series of length indications and followed by a 0 as a terminating comma. Value Elias ω code Even-Rodeh code 0 — 000 1 0 001 2 10 0 010 3 11 0 011 4 10 100 0 100 0 7 10 111 0 111 0 8 11 1000 0 10

Parallel canonical recoding

Abstract: The author introduces a parallel algorithm for generating the canonical signed-digit expansion of an n-bit number in O(logn) time using O(n) gates. The algorithm is similar to the computation of the carries in a carry look-ahead circuit. It is also proven that if the binary number x + ⌋x/2⌊ is given, then the canonical signed-digit recoding of x can be computed in O(1) time using O(n) gates.

VLSI Architectures and Arithmetic Operations with Application to the Fermat Number Transform

Abstract: Theproperties of arithmetic operations in Fermat integer quotient ringsZ m , where m , are investigated. The arithmetic operations considered are mainly those involved in the computation of the Fermat number transform. We consider somewaysof representing the binary coded integers in such rings and investigate VLSI architectures for arithmetic operations, with respect to the different element representations. The VLSI architectures are mutually compared with respect to area (A) and time (T ) complexity and area-time performance (AT ). The VLSI model chosen is a linear switch-level RC model. In the polar representation, the nonzero elements of a field are represented by the powers of a primitive element of the field. In the thesis we particularly investigate the properties of arithmetic operations and their corresponding VLSI architectures with respect to the polar representation of the elements of Fermat prime fields. Some new results regarding the applicability of the Fermat number transform when using the polar representation are also presented.

Tree structured binary arithmetic coder

Abstract: An N valued input symbol is encoded by using a tree structured binary arithmetic coder wherein N is an integer larger than 2M-1 but not greater than 2M with M being a non-negative integer. First, the input symbol is converted into M bits of binary symbols. Thereafter, a context for a kth bit of the binary symbols is selected among a kth groups of contexts, each of the contexts in a group representing a different probability model of a binary symbol. The kth group of contexts includes 2k-1 contexts therein and a larger value of k represents a lower bit of the binary symbols, k being an integer from 1 to M. A context corresponding to an Lth bit is selected among an Lth group of contexts based on one or more upper bits thereof, L being an integer ranging from 2 to M. Finally, each of the M bits of the binary symbols is encoded serially based on its corresponding context by using a binary arithmetic coding method.

Fast carry-sum form booth encoder

Abstract: A fast carry-sum form Booth encoder is used in a multiplicative divider to iteratively multiply one number by a series of numbers to produce the result of a divide or square root operation. The fast Booth encoder inputs a binary sum and a binary carry row representing the first number. The encoder adds the two numbers and at the same time Booth-encodes the result and outputs this result to a partial product generator to be combined with one of the series of numbers. Included in the fast Booth encoder are a multiplicity of interconnected logic cells. Each logic cell receives a number of distinct sequential bits from each of the binary sum and carry rows. The sequential bits from one binary number correspond to sequential bits in the other binary number. Each cell then produces an associated cell output. Each logic cell includes a carry bit generator for producing a number of carry bits to transmit to a next interconnected logic cell. Each cell also has an output generator for producing the cell output associated with the logic cell. Together, the cell outputs produced by each logic cell are at least a portion of a Booth encoded form of the sum of the pair of binary numbers. The logic is optimized so that a carry ripple passes through no more than two of the logic cells before being output, so that a carry ripple through all of the logic cells is avoided.