Showing papers on "Binary number published in 2009"

Logistic chaotic maps for binary numbers generations

Abstract: Two pseudorandom binary sequence generators, based on logistic chaotic maps intended for stream cipher applications, are proposed. The first is based on a single one-dimensional logistic map which exhibits random, noise-like properties at given certain parameter values, and the second is based on a combination of two logistic maps. The encryption step proposed in both algorithms consists of a simple bitwise XOR operation of the plaintext binary sequence with the keystream binary sequence to produce the ciphertext binary sequence. A threshold function is applied to convert the floating-point iterates into binary form. Experimental results show that the produced sequences possess high linear complexity and very good statistical properties. The systems are put forward for security evaluation by the cryptographic committees.

Evolution of the binary fraction in dense stellar systems

Abstract: Using our recently improved Monte Carlo evolution code, we study the evolution of the binary fraction in globular clusters. In agreement with previous N-body simulations, we find generally that the hard binary fraction in the core tends to increase with time over a range of initial cluster central densities for initial binary fractions 90%. The dominant processes driving the evolution of the core binary fraction are mass segregation of binaries into the cluster core and preferential destruction of binaries there. On a global scale, these effects and the preferential tidal stripping of single stars tend to roughly balance, leading to overall cluster binary fractions that are roughly constant with time. Our findings suggest that the current hard binary fraction near the half-mass radius is a good indicator of the hard primordial binary fraction. However, the relationship between the true binary fraction and the fraction of main-sequence stars in binaries (which is typically what observers measure) is nonlinear and rather complicated. We also consider the importance of soft binaries, which not only modify the evolution of the binary fraction, but can also drastically change the evolution of the cluster as a whole. Finally, we briefly describe the recent addition of single and binary stellar evolution to our cluster evolution code.

A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format

Abstract: The IEEE Standard 754-1985 for binary floating-point arithmetic [19] was revised [20], and an important addition is the definition of decimal floating-point arithmetic [8], [24]. This is intended mainly to provide a robust reliable framework for financial applications that are often subject to legal requirements concerning rounding and precision of the results, because the binary floating-point arithmetic may introduce small but unacceptable errors. Using binary floating-point calculations to emulate decimal calculations in order to correct this issue has led to the existence of numerous proprietary software packages, each with its own characteristics and capabilities. The IEEE 754R decimal arithmetic should unify the ways decimal floating-point calculations are carried out on various platforms. New algorithms and properties are presented in this paper, which are used in a software implementation of the IEEE 754R decimal floating-point arithmetic, with emphasis on using binary operations efficiently. The focus is on rounding techniques for decimal values stored in binary format, but algorithms are outlined for the more important or interesting operations of addition, multiplication, and division, including the case of nonhomogeneous operands, as well as conversions between binary and decimal floating-point formats. Performance results are included for a wider range of operations, showing promise that our approach is viable for applications that require decimal floating-point calculations. This paper extends an earlier publication [6].

Algebraic foundation of self adjusting Switched Capacitors Converters

Abstract: An algebraic model that describes the operation of binary Switched-Capacitor Converters (SCC) was developed and generalized to any radix case. The proposed approach reduces the power loss by increasing the number of target voltages. In the binary case, the flying capacitors are automatically kept charged to binary weighted voltages and consequently, the resolution of the possible target voltages is binary. The paper presents the underlining theory of the proposed SCC and two new control methods to regulate the output voltage. It is shown that the theoretical formulation of the new number systems can describe many SCC circuits on the market and can help design new SCC with a larger number of target voltages. The theoretical results were verified for the binary case by simulation and experimentally. Excellent agreement was found between the theory and experimental results. The down side of the proposed SCC schemes is the relatively large number of switches which makes the approach more suitable for low power applications.

Characteristics of Fast Physical Random Bit Generation Using Chaotic Semiconductor Lasers

Abstract: We investigate the characteristics of fast random bit generation using chaotic semiconductor lasers. The optical amplitudes of two lasers with chaotic oscillations induced by optical feedback are each sampled at a fixed rate to extract binary bit sequences which are then combined by an exclusive-OR operation to obtain a single random bit sequence. Bit sequences generated at rate of 1 Giga bit per second are verified to pass statistical tests of randomness. We describe the dependence of randomness on laser parameters, in particular the injection current, the external cavity length and the feedback strength. The results provide clear empirical guidelines for tuning the chaotic laser parameters to achieve random bit sequences. This study shows that chaotic laser devices can be fast and reliable sources of physical entropy for computing and communication applications.

A New Redundant Binary Booth Encoding for Fast $2^{n}$ -Bit Multiplier Design

Abstract: The use of redundant binary (RB) arithmetic in the design of high-speed digital multipliers is beneficial due to its high modularity and carry-free addition. To reduce the number of partial products, a high-radix-modified Booth encoding algorithm is desired. However, its use is hampered by the complexity of generating the hard multiples and the overheads resulting from negative multiples and normal binary (NB) to RB number conversion. This paper proposes a new RB Booth encoding scheme to circumvent these problems. The idea is to polarize two adjacent Booth encoded digits to directly form an RB partial product to avoid the hard multiple of high-radix Booth encoding without incurring any correction vector. The proposed method leads to lower encoding and decoding complexity than the recently proposed RB Booth encoder. Synthesis results using Artisan TSMC 0.18-mum standard-cell library show that the RB multipliers designed with our proposed Booth encoding algorithm exhibit on average 14% higher speed and 17% less energy-delay product than the existing multiplication algorithms for a gamut of power-of-two word lengths from 8 to 64 b.

Multiclass, Multistage, and Multilevel Fiber-Optic CDMA Signaling Techniques Based on Advanced Binary Optical Logic Gate Elements

Abstract: In this paper we introduce and propose novel signaling methods and receiver structures based on advanced binary optical logic gates for fiber-optic code division multiple access (FO-CDMA) systems using all-optical signal processing. In the proposed system the users of the network are categorized into multiple classes. Users of each class transmit at the same power level but different from the levels of the other classes' users. Using a combination of optical OR, AND and XNOR logic gates for the receiver structure we show that such a network not only takes the full advantages of all-optical signal processing but also demonstrates a considerable throughput efficiency when compared to ordinary FO-CDMA systems. The proposed receiver structure mitigates the effect of interfering users from the other classes by rejecting some specified power level combinations from the other classes. The depth of interference cancellation is a function of the corresponding number of power levels and the number of stages applied to the optical logic gates in use. In our analysis we choose the generalized form of optical orthogonal codes (OOC), i.e., OOCs with cross-correlation value greater than one, as the signature sequence. We begin by emphasizing on two-level systems, that is, when the users can select one out of two power levels for signal transmission. However, for multilevel FO-CDMA we obtain a closed-form relation for the upper bound on the probability of error.We will show that under the ideal case the increase in throughput resulting from the proposed multilevel system is proportional to the number of classes or power levels in use. Our analytical results are compared to the results of an extensive system simulation. The numerical closeness between, the analytical and system simulation, indicates the accuracy with which we have modeled mathematically our proposed signaling using advanced binary optical logic gates in FO-CDMA.

Finding Efficient Circuits Using SAT-Solvers

Abstract: In this paper we report preliminary results of experiments with finding efficient circuits (over binary bases) using SAT-solvers. We present upper bounds for functions with constant number of inputs as well as general upper bounds that were found automatically. We focus mainly on MOD-functions. Besides theoretical interest, these functions are also interesting from a practical point of view as they are the core of the residue number system. In particular, we present a circuit of size 3n + c over the full binary basis computing ${\rm MOD}_3^n$.

Minimization and optimization of reversible bcd-full adder/subtractor using genetic algorithm and don't care concept

Abstract: Reversible logic and binary coded decimal (BCD) arithmetic are two concerning subjects of hardware. This paper proposes a modular synthesis method to realize a reversible BCD-full adder (BCD-FA) and subtractor circuit. We propose three approaches to design and optimize all parts of a BCD-FA circuit using genetic algorithm and don't care concept. Our first approach is based on the Hafiz's work, and the second one is based on the whole BCD-FA circuit design. In the third approach, a binary to BCD converter is presented. Optimizations are done in terms of number of gates, number of garbage inputs/outputs, and the quantum cost of the circuit. We present four designs for BCD-FA with four different goals: minimum garbage inputs/outputs, minimum quantum cost, minimum number of gates, and optimum circuit in terms of all the above parameters.

The Analysis and Improvement of Binary Particle Swarm Optimization

Abstract: In this paper, the binary Particle Swarm Optimization (PSO) is analyzed with bit change rate and velocity expected value, which results is that binary PSO is more and more stochastic, has the powerful ability of global search, but cannot converge to the optimal particle of swarm. So the Binary PSO is lack of local exploration which instructs the improvement of BPSO. Based on the analysis, an improved Binary PSO is proposed which changes the formula of its probability mapping and the formula of bit obtaining value. The new formulas are favorable of particle’ s convergence to the optimal particle and to intensify the local exploration of binary PSO. With 0/1 knapsack problem, the experiment conducted in this paper shows that the improved binary PSO is outperformed to original binary PSO.

An all-optical technique for a binary-to-quaternary encoder and a quaternary-to-binary decoder

Abstract: A polarization encoded all-optical scheme for a binary-(radix = 2)-to-quaternary (radix = 4) encoder and a quaternary-to-binary decoder is proposed and described. The performance of the proposed circuit is verified through numerical calculation. In this all-optical scheme, the numbers are represented by different discrete polarized states of light. The model is simple, practical and useful for future all-optical information processing.

All-optical conversion scheme: Binary to quaternary and quaternary to binary number

Abstract: To achieve the inherent parallelism in optics a suitable number system and efficient encoding/decoding scheme for handling the data are very much essential. Binary number is accepted as the best representing number system in almost all types of existing electronic computers. But, binary number (0 and 1) is insufficient in respect to the demand of the coming generation. Multi-valued logic (with radix >2) can be viewed as an alternative approach to solve many problems in transmission, storage and processing of large amount of information in digital signal processing. Here, in this paper all-optical scheme for the conversion of binary to quaternary number and vice versa have been proposed and described. Simulation has also been done. In this all-optical scheme the numbers are represented by different discrete polarized state of light.

A Combined Decimal and Binary Floating-Point Multiplier

Abstract: In this paper, we describe the first hardware design of a combined binary and decimal floating-point multiplier, based on specifications in the IEEE 754-2008 Floating-point Standard. The multiplier design operates on either (1) 64-bit binary encoded decimal floating-point (DFP) numbers or (2) 64-bit binary floating-point (BFP) numbers. It returns properly rounded results for the rounding modes specified in IEEE 754-2008. The design shares the following hardware resources between the two floating-point datatypes: a 54-bit by 54-bit binary multiplier, portions of the operand encoding/decoding, a 54-bit right shifter, exponent calculation logic, and rounding logic. Our synthesis results show that hardware sharing is feasible and has a reasonable impact on area, latency, and delay. The combined BFP and DFP multiplier occupies only 58% of the total area that would be required by separate BFP and DFP units. Furthermore, the critical path delay of a combined multiplier has a negligible increase over a standalone DFP multiplier, without increasing the number of cycles to perform either BFP or DFP multiplication.

Distribution of Distributed Arithmetic Codewords for Equiprobable Binary Sources

Abstract: Distributed Arithmetic Coding (DAC) is an effective implementation of Slepian-Wolf coding, especially for short data blocks. However, the properties of DAC codewords have not yet been studied so far. This paper researches DAC codeword distribution over interval [0, 1] for equiprobable binary sources. Some simulation results are given to verify theoretical analyses.

Binary-arithmetic approach to observability checking in state estimation

Abstract: An efficient and robust technique for observability checking in power system state estimation based on Gaussian elimination and binary arithmetic is provided. Since the proposed technique uses binary arithmetic, no rounding error, numerical instability or zero identification problems occur. In some cases, the technique may not identify all observable state variables, requiring an additional numerical analysis over a matrix of dimension that is highly reduced. An illustrative example of small size and a realistic case study are used to demonstrate the features of the proposed technique. Adequate conclusions are finally drawn.

Elliptic Curve Scalar Multiplication Combining Yao's Algorithm and Double Bases

Abstract: In this paper we propose to take one step back in the use of double base number systems for elliptic curve point scalar multiplication. Using a modified version of Yao's algorithm, we go back from the popular double base chain representation to a more general double base system. Instead of representing an integer k as $\sum^n_{i=1}2^{b_i}3^{t_i}$ where (b i ) and (t i ) are two decreasing sequences, we only set a maximum value for both of them. Then, we analyze the efficiency of our new method using different bases and optimal parameters. In particular, we propose for the first time a binary/Zeckendorf representation for integers, providing interesting results. Finally, we provide a comprehensive comparison to state-of-the-art methods, including a large variety of curve shapes and latest point addition formulae speed-ups.

Binary representations of algebras with at most two binary operations. a cayley theorem for distributive lattices

Abstract: The notion of binary representation of algebras with at most two binary operations is introduced in this paper, and the binary version of Cayley theorem for distributive lattices is given by hyperidentities. In particular, we get the binary version of Cayley theorem for DeMorgan and Boolean algebras.

On the distribution of runs of ones in binary strings

Abstract: In this paper, we derive the number of binary strings which contain, for a given i"k, exactly i"k runs of 1's of length k in all possible binary strings of length n, [email protected][email protected]?n. Such a knowledge about the distribution pattern of runs of 1's in binary strings is useful in many engineering applications - for example, data compression, bus encoding techniques to reduce crosstalk in VLSI chip design, computer arithmetic using redundant binary number system and design of energy-efficient communication schemes in wireless sensor networks by transformation of runs of 1's into compressed information patterns, among others. We present, here, a generating function based approach to derive a solution to this counting problem. Our experimental results demonstrate that, for most commonly used file formats, the observed distributions of exactly i"k runs of length k, [email protected][email protected]?n, closely follow the theoretically derived distributions, for a given n. For n=8, we find that the experimentally obtained values for most file formats agree within +/-5% of the theoretically obtained values for all i"k runs of length k, [email protected][email protected]?n. Also, the root mean square (RMS) values of these deviations across all file types studied in this paper are less than 5% for n=8. In view of these facts, the results presented in this paper could be useful in various application domains, like the ones mentioned above.

Physical parameters of close binary systems: VI

Abstract: We present results of modelling of multicolour light curves of ten contact binary systems: V376 And, V523 Cas, CC Com, BX Dra, FG Hya, UZ Leo, XY Leo, AM Leo, EX Leo, and RT LMi. The solutions resulted in a contact configuration for all systems. We found only FG Hya and UZ Leo to be in deep contact, the latter almost filling the outer critical lobe. The absolute parameters of the components have been determined with an accuracy of about w few percent based on combined photometric and radial velocity curves, enlarging to 58 the sample of systems for which the physical parameters have been obtained in a uniform way. All but three systems (BX Dra, AM Leo and RT LMi) show asymmetries and peculiarities in the observed light curves, interpreted as resulting from their magnetic activity.

A binary Self-Organizing Map and its FPGA implementation

Abstract: A binary Self Organizing Map (SOM) has been designed and implemented on a Field Programmable Gate Array (FPGA) chip. A novel learning algorithm which takes binary inputs and maintains tri-state weights is presented. The binary SOM has the capability of recognizing binary input sequences after training. A novel tri-state rule is used in updating the network weights during the training phase. The rule implementation is highly suited to the FPGA architecture, and allows extremely rapid training. This architecture may be used in real-time for fast pattern clustering and classification of binary features.

A binary Self-Organizing Map and its FPGA implementation.

Abstract: A binary Self Organizing Map (SOM) has been designed and implemented on a Field Programmable Gate Array (FPGA) chip. A novel learning algorithm which takes binary inputs and maintains tri-state weights is presented. The binary SOM has the capability of recognizing binary input sequences after training. A novel tri-state rule is used in updating the network weights during the training phase. The rule implementation is highly suited to the FPGA architecture, and allows extremely rapid training. This architecture may be used in real-time for fast pattern clustering and classification of binary features.

Compressed Binary Bit Trees: A New Data Structure For Accelerating Database Searching

Abstract: Molecules are often represented as bit string fingerprints in databases. These bit strings are used for similarity searching using the Tanimoto coefficient and rapid indexing. A new data structure is introduced, the compressed bit binary tree, that rapidly increases search and indexing times by up to a factor of 30. Results will be shown for databases of up to 1 M compounds with a variety of search parameters.

Two Kinds of Ideal Contrast Visual Cryptography Schemes

Abstract: The (k, n) visual cryptography schemes (VCS) is a perfect secure method that encrypts a secret image by breaking it into shadow images. A Visual Crypto (VC) system based on the polarisation of light which has good resolution, contrast and color properties is introduced. Mathematically, the VC system is described by the XOR operation, which just mean modulo two addition and is equivalence of addition in the finite field GF(2). In this paper, we investigate threshold visual secret sharing schemes mixed XOR and OR operation with reversing and based on binary linear error-correcting code. Firstly, we show that 2 out of 2 schemes mixed on XOR and OR operation with reversing where the reconstruction of both black and white pixels is perfect. It turns out that scheme have much better resolution than their OR-based counterparts. Secondly, we provide one construction for general k out of n schemes based on binary linear error-correcting code. And we show these two schemes are ideal contrast.

Decimal Transcendentals via Binary

Abstract: We describe the design and implementation of a comprehensive library of transcendental functions for the new IEEE decimal floating-point formats. In principle, such functions are very much analogous to their binary counterparts,though with a few additional subtleties connected with `scale' (preferred exponent). But our approach has been not to employ direct techniques, but rather to re-use existing binary functions as much as possible, both for greater efficiency and ease of implementation. For some functions the most straightforward approach (convert from decimal to binary, perform binary operation, convert back) works well. In many cases, however, these are insufficiently accurate, and subtler approaches must be used.

Decimal addition in FPGA

Abstract: This paper presents a study of the classical BCD adders from which a carry-chain type adder is redesigned to fit within the Xilinx FPGAs. Some new concepts are presented to compute the P and G functions for carry-chain optimization purposes. Several alternative designs are then presented with the corresponding time performances and area consumption figures. In order to compare the results, the straight implementation of a decimal ripple-carry adder and the FPGA optimized base 2 adder for the same range are implemented. Results for big operands show that the decimal adder works faster than an equivalent binary implementation and furthermore the coding / decoding processes are no more needed.

Arithmetic decoding apparatus and method

Abstract: The decoding apparatus enabling high-speed arithmetic decoding in decoding data coded using CABAC is an arithmetic decoding apparatus which receives, as input, coded data obtained by converting multivalue information of syntax into binary data then performing Context-based Adaptive Binary Arithmetic Coding on the binary data, and which decodes the coded data into the original multivalue information. During the reconstruction of the current binary data, the arithmetic decoding apparatus, parallelly calculates, in the same cycle, “next-next identifier code” candidates and “context index” candidates corresponding to the “next-next identifier code” candidates, and, in the next cycle, parallelly calculates, in the same cycle, a “next identifier code”, context index candidates corresponding to the next identifier code, and “probability variable” candidates corresponding to the “context index” candidates, and, when the current binary data reconstruction result is known, selects the respective calculation results according to the reconstruction result.