Showing papers on "Bit error rate published in 1977"

Mobile fading—Rayleigh and lognormal superimposed

Abstract: A closed solution is presented showing the composite probability distribution of power levels derived from short term Rayleigh fading with superimposed long term lognormal variations of mean value. An example shows how the results can be applied to the prediction of bit error rates in a mobile radio data transmission channel, and how the error rate will vary with standard deviation of the lognormal distribution.

Theoretical and Measured Performance of a DFE Modem on a Fading Multipath Channel

Abstract: A decision-feedback equalizer (DFE) is the basis of a recent development of a quadruple diversity troposcatter modem which can operate up to a data rate of 12.6 Mbit/s in a 99% bandwidth of 15 MHz. In this paper a theoretical approach is developed for the calculation of average bit error rate (ABER), including the effects of intersymbol interference due to multipath and the finiteness of the transversal filters used to realize the DFE. By omitting the intersymbol interference effect, the calculation provides a lower bound which can be used to assess the intersymbol interference penalty for a particular DFE structure. The paper includes calculations of a DFE configuration which has a three tap forward filter with tap spacing equal to one-half a symbol interval. Measured performance results from fading channel simulator tests of a three tap forward filter DFE are presented for data rates from 1.5 to 12.6 Mbit/s and for a wide range of multipath statistical conditions. The results for this DFE configuration show (1) excellent agreement between calculated and measured ABER, (2) a small intersymbol interference penalty when the 2σ multipath spread is less than approximnately one-half the data symbol interval, and (3) successful operation at values of multipath spread up to twice the data symbol interval. In a sequel to this paper, the results of a field test of the DFE modem are presented. These live links test results are consistent with both the calculated and simulator measured data presented here.

System for controlling synchronization in a digital communication system

Abstract: A technique and implementation of generating and supplying synchronization and error checking signals to a serially transmitted data stream includes the generation of flag bytes which define the end boundaries of the serial data stream, an abort character for aborting the transmission of a frame of data in response to certain conditions, and a diagnostic evaluation character inserted into the data stream. In addition, the invention provides a technique for ensuring that the unique binary code by which a flag byte is defined occurs in the transmitted data stream only where intended. The flag code has been chosen to contain a prescribed number of consecutive one bits, (i.e. -- six) flanked by zeroes, and circuitry monitors the contents of a data frame as it is being serialized out for transmission to a remote terminal at times other than during flag transmission. When five consecutive one bits are detected, serializing out of the next bit in the data is interrupted, and a dummy zero bit is inserted prior to the next bit. As a result, the transmitted frame of data will contain no more than five consecutive one bits, except during the flag bytes, (or an abort character) thus ensuring proper synchronization of the end points of the frame. At the receiver terminal, detection and decoding circuitry also monitors the number of consecutive one's in the received data stream. When five consecutive one's are detected, the receiver decoder circuitry checks to see whether the next bit is a dummy zero bit. If the next bit is a zero bit, it is deleted so that the intended data will be correctly reassembled.

Theoretical and measured performance of a DFE modem on a fading multipath channel

Abstract: A decision-feedback equalizer (DFE) is the basis of a recent development of a quadruple diversity troposcatter modem which can operate up to a data rate of 12.6 Mbit/s in a 99% bandwidth of 15 MHz. In this paper a theoretical approach is developed for the calculation of average bit error rate (ABER), including the effects of intersymbol interference due to multipath and the finiteness of the transversal filters used to realize the DFE. By omitting the intersymbol interference effect, the calculation provides a lower bound which can be used to assess the intersymbol interference penalty for a particular DFE structure. The paper includes calculations of a DFE configuration which has a three tap forward filter with tap spacing equal to one-half a symbol interval. Measured performance results from fading channel simulator tests of a three tap forward filter DFE are presented for data rates from 1.5 to 12.6 Mbit/s and for a wide range of multipath statistical conditions. The results for this DFE configuration show (1) excellent agreement between calculated and measured ABER, (2) a small intersymbol interference penalty when the 2σ multipath spread is less than approximnately one-half the data symbol interval, and (3) successful operation at values of multipath spread up to twice the data symbol interval. In a sequel to this paper, the results of a field test of the DFE modem are presented. These live links test results are consistent with both the calculated and simulator measured data presented here.

Multiplex/demultiplex apparatus

Abstract: An encoding scheme for simplifying frame acquisition and access to an auxiliary channel information bit stream and apparatus for implementing same. A pair of incoming data channels are multiplexed onto three communicating data channels wherein one of the channels contains overhead bits and high speed data bits, a second channel contains auxiliary channel bits and high speed data bits and a third channel contains only high speed data bits. With this format, the operational frequency of the frame acquisition circuit is reduced compared to multiplexing to a single channel and the channel containing only high speed data can be used directly for bit error rate (BER) measurements.

Memory error logger which sorts transient errors from solid errors

Abstract: A method of and an apparatus for distinguishing between transient and solid errors within a single-error-correcting semiconductor memory storage unit (MSU) comprised of a plurality of large scale integrated (LSI) bit planes and for notifying the associated data processing system of required maintenance action. The method utilizes an error logging store (ELS) that is comprised of a plurality of memory error registers one for each separately associated word group within the MSU. Each memory error register contains storage for: (1) the Error Correction Code (ECC) defined, failing bit position; (2) the single bit error counter; (3) the multiple single bit error tag; and (4) the multiple bit error tag. Upon detection of an error within a word group, the associated memory error register is accessed to determine the history of previously detected errors within that word group. The central processing unit (CPU) is notified by a priority interrupt of the error status of that word group if: (1) the number of consecutive errors within a word group at the same bit position reaches a set threshold indicating the high probability of a solid single bit error; or (2) the error detected is in a different bit position from that previously identified as a solid single bit error indicating the high probability of a future uncorrectable multiple-bit error. This method and apparatus notifies the CPU of the likelihood of imminent uncorrectable errors and maintains a history of the error indications that lead to that conclusion.

Error correction for signals employing the modified duobinary code

Abstract: Single errors can be detected and corrected in a signal employing a 3-level modified duobinary code. Error correction is predicated on the concept of maximum likelihood of error for the bit having the maximum departure from normal amplitude (error differential). A converter accepts the modified duobinary signal, decodes the signal to obtain a binary output signal and determines the error differential for each bit. Bits of the binary output signals are temporarily stored in a sequential storage device. The error differential is applied to an input of an error analyzer. An error detector determines if an error has occurred during an error correction interval which interval is established by successive extreme levels of the modified duobinary signal. The error analyzer tracks the location of the bit having the largest error differential during each error correction interval. A plurality of bit correctors, one for each time slot of the sequential storage device, operate in combination with the error detector and the error analyzer to alter the bit having the highest error differential following detection of an error.

Apparatus for digital data synchronization

Abstract: A system, including an encoder and decoder, for the transmission of digital information over a transmission medium. The encoder processes a data stream of length M and generates a transmission bit stream. The processing includes combination of the M data bits with N predetermined sync bits, via a modulo-2 adder. The resulting transmission stream has a total length less than M+N, thereby substantially minimizing the number of bits otherwise required. The decoder regenerates the data bit stream by modulo-2 subtraction of the transmission bit stream with said N sync bits, stored within the decoder. The resulting system thereby provides optimum synchronization and, therefore, data recovery, while requiring a minimum of transmission bits.

Double bit error correction using single bit error correction, double bit error detection logic and syndrome bit memory

Abstract: A method of and an apparatus for obtaining double bit error correction capabilities in a large scale integrated (LSI) semiconductor memory system using only single bit error correction, double bit error detection (SEC, DED) logic are disclosed. The method is based upon the statistical assumption that in a large scale integrated semiconductor memory, substantially all errors in the data bits that make up a data word are initially a single bit error and that increasing multiple, i.e., double, triple, etc., bit errors occur in a direct increasing ratio of the use or selection of the data word. In the present invention, all data words are priorly tested to be error free. Subsequent detection of single bit errors results in the correction of the single bit error and the storage of the single bit error correcting syndrome bits in a syndrome bit memory. Subsequent detection of double bit errors, in the previously single bit error detected and corrected data words, results in the correction, by single bit error correcting syndrome bits, of the previously detected single bit error. This single bit error corrected data word is then again single bit error corrected, i.e., two successive single bit error corrections, to provide a twice corrected double bit error data word.

Error detection and correction

Abstract: An error detection and correction system in which at least the highest order bit of each data word is given a greater protection against errors in transmission than lower order bits. Useful for digitized TV signals where errors in received high order bits have much worse effect on picture quality than errors in low order bits. A parity is generated for each data word in accordance with a self-orthogonal convolutional code constructed by the use of the base elements of a difference triangle for each bit of the data word, the difference triangles being disjoint, the triangle associated with the highest order bit or bits having a large number or numbers of base elements, and the triangles associated with the lowest order protected bit or bits consisting of a single base element. Errors in received code words are detected and corrected in a decoder including majority logic threshold detectors. Error correcting feedback to the syndrome shift register is limited to errors detected in the high order bits.

Bit error rate measurement above and below bit rate tracking threshold

Abstract: Bit error rate is measured by sending a pseudo-random noise (PRN) code test signal simulating digital data through digital equipment to be tested An incoming signal representing the response of the equipment being tested, together with any added noise, is received and tracked by being compared with a locally generated PRN code Once the locally generated PRN code matches the incoming signal a tracking lock is obtained The incoming signal is then integrated and compared bit-by-bit against the locally generated PRN code and differences between bits being compared are counted as bit errors

Error detection and correction

Abstract: An error detection and correction system in which at least the highest order bit of each data word is given a greater protection against errors in transmission than lower order bits. Useful for digitized TV signals where errors in received high order bits have much worse effect on picture quality than errors in low order bits. A parity is generated for each data word in accordance with a self-orthogonal convolutional code constructed by the use of the base elements of a difference triangle for each bit of the data word, the difference triangles being disjoint, the triangle associated with the highest order bit or bits having a large number or numbers of base elements, and the triangles associated with the lowest order protected bit or bits consisting of a single base element. Errors in received code words are detected and corrected in a decoder including majority logic threshold detectors.

Bit error rate performance monitor units in digital transmission links

Abstract: A bit error performance monitor in which the input signal is equally shared by two substantially identical monitors whose outputs in turn are connected to an adder. The output of the adder passes through a divider-by-2 to a counter.

Averaged threshold receiver for direct detection of optical communications through the lognormal atmospheric channel.

Abstract: An averaged threshold receiver is developed for an optical communication system consisting of a symmetric binary, pulse-code modulated transmitter, a lognormal channel, and an array of independent photocounting detectors. When compared to previously described receivers, it is shown to be a much simpler structure to implement and to provide generally lower bit error rates. Probability of error curves demonstrating this improved performance are presented for various combinations of turbulence strength, background radiation level, SNR, number of diversity channels, and, in the newly developed processor, number of bits used for threshold averaging.

4-phase p.s.k. differential demodulator using a.s.w. delay lines

Abstract: The letter describes a cheap and reliable solution, using acousticsurface-wave delay lines, for the differential demodulation of phase-shift-keyed digital signals at low digital rates (up to 20 Mbit/s). Results on 4-phase p.s.k. differential demodulators operating at 2.048 Mbit/s are reported in terms of bit error rate against energy per bit/noise spectral density ratio. In addition, using the same technology, a new multidifferential demodulator has been implemented. Owing to multiple differential demodulations carried out on the same signal, a significant improvement in both theoretical and experimental bit error rate is obtained.

SDLC and BSC on satellite links: a performance comparison

Abstract: The emergence of satellite communication links offers the data communication designer increased throughput, but at the same time forces him to deal with greatly increased signal transmit time which may eliminate all potential throughput increases. Using a mathematical model, this paper compares batch throughput efficiency of two IBM line control methods, Binary Synchronous Communications (BSC) and Synchronous Data Link Control (SDLC), along with some hypothetical extensions to SDLC. Although the model treats links of any description, the focus here is on links with long signal transit time and low bit error rate, such as satellite links. Classic analog terrestrial links are included for comparison.The model consists of an information source with an infinite supply of data transmitting to an information sink which transmsits no data but does acknowledge received frames as defined in the various protocols. Throughput efficiency is defined as the ratio of the time spent by the data source transmitting original information bytes (i.e., bytes in the SDLC or BSC Information Field, excluding those bytes retransmitted due to errors) to the time spent transmitting all bytes (i.e., information, control, and error recovery) plus time taken by any gaps in continuous transmission.The comparison applies to steady-state batch transmission, so the link is assumed to be point-to-point. Both full duplex and half duplex protocols are considered in SDLC, but only half duplex protocols are contained in BSC. A hypothetical extension to SDLC, Asynchronous Response Mode (ARM), and SDLC Normal Response Mode (NRM) are included in full duplex. The model shows no difference in throughput efficiency between half duplex NRM and ARM, so only one result is presented for half duplex SDLC. Both SDLC and BSC are data link control architectures; for details concerning a particular implementation, the reader should consult the product description. More detail on SDLC and BSC is available in References 1-4.Two transmission links are considered. The terrestrial analog link consists of traditional analog facilities, while the satellite link consists of only a satellite connection between the end points (i.e., the end points are very close to the satellite earth stations, such that negligible transit time and link errors are introduced in the terminal-to-earth station links). Each link is characterized by its bit error rate (BER) and round trip delay (RTD). Bit error rate is the long-term average of bit errors per bit transmitted, while round trip delay is defined as the amount of time between the last bit of a given SDLC frame or BSC block being transmitted and the first bit of its response being received at the source. RTD includes the time (in seconds) necessary to generate and transmit a line-control response at the receiving end, as well as any delay in equipment between the end points. Results are obtained using a simple bit-independent error model.The next section describes the applicable equations, while the following section discusses results.

Signal process system

Abstract: PURPOSE:To secure transmission of much amount of information with a small number of the bit in the range bit system by ensuring an effective use of the signal bit to increase practically the range number.

System for reducing transmission problems in a parallel digital data transmission system

Abstract: A digital transmission system wherein a signal to be transmitted is represented by a plurality of parallel data bits, each of said data bits having a positional significance ranging from a most significant data bit to a least significant data bit. Each of said data bits are assigned to one of a plurality of data transmission highways based on the positional significance of the data bit. Failure of a particular highway results in a reassignment of the data bits to the highways so that transmission degradation is minimized.

Wideband 1.064 micrometer detector evaluation

Abstract: Several types of communications detectors for use in a 400 Mbps 1.064 micrometer laser communication system were evaluated and characterized. The communication system Bit Error Rate (BER) performance was measured, and test results for the best detector of each type are summarized. The complete BER curves are presented. The 400 Mbps 1.064 micrometer communication system receiver test bed is described. The best performance levels which can be achieved by focusing the signal to diffraction limited spots on the photosensitive area are cited.

A direct access terabit archival memory

Abstract: This paper addresses recent developments in terabit-level laser archival memory storage technology. The laser memory employs a 500 milliwatt 514.5 nanometer wavelength argon-ion optical laser source to melt permanent bit patterns into a rhodium-coated flexible plastic data storage strip. The same laser, operated at an order of magnitude less power output, is used to read the stored binary data. Information densities of 2.5 × 107 bits per square inch are achieved as limited by tracking and beam spot size. Because each data record is permanent, truly archival storage (∼25 years) is only limited by dust build-up. Extensive error correction codes enable performance at the 10-10 bit error rate level. The system is supported by extensive software that provides call-by-name file access. Operating at peak data rates of 5 megabits/second, the system behaves as an on-line direct-access file, with an on-line capacity equivalent to several thousand 1600 BP1 2400-foot rolls of magnetic tape. Worst case access time to any record is of the order of seconds. Average user-data transfer rates can be as high as 2.86 megabits per second with full data redundancy.

Automatic training circuit

Abstract: PURPOSE:To improve bit error ration as well as to ecure regular phase lead-in point for reproduction carrier by performing an automatic setting at early time in the case of lowering of bit error ratio and phase lead-in point error of the reproduction carrier.

Bit timing with pulse distortion and intersymbol interference

Abstract: Pulse distortion and intersymbol interference due to insufficient filtering in PCM and PSK channels cause performance degradation in terms of both bit error probabilities and timing errors. This paper reports the results of a study analyzing these effects on bit timing subsystems. Consideration is given to both the filter-rectifier and transition tracking type of timing subsystem. Although both these systems perform similarly in high SNR and ideal pulse models, pulse distortion and intersymbol affects each differently. The primary effects in both systems is to cause the presence of an irreducible mean squared timing error due to the intersymbol which limits the ultimate performance. Design procedures to minimize the anomalies of both systems are presented, and indicate modifications of the standard timing subsystems. It is found that specific design directions depend on whether the intersymbol or the receiver noise tends to dominate.

Performance Comparison of Bipolar Alternate Mark Inversion and Conditioned Diphase Waveforms Over Wireline Media

Abstract: : This report was prepared for the Defense Communications Agency to study the performance of two waveforms competing for implementation in the Defense Communications System. The waveforms, Bipolar Alternate Mark Inversion (BAMI) and Conditioned Diphase (CDtheta), were studied both from a theoretical standpoint and with experimental breadboard hardware designed and built in- house. Theoretical performance curves for both waveforms operating in wideband gaussian noise were developed and the hardware was tested against wideband gaussian noise. The results of testing the waveform over Griffiss AFB cable plant are presented along with computer-generated distributions of data bit errors encountered. The effects and problems involved in recovering timing information from two waveforms are not covered in this report. The results indicate that, with white gaussian noise as the only transmission impairment, the two waveforms perform nearly identically. Their performances are also close when operation is over cables with moderate amounts of intersymbol interference and attenuation. However, when intersymbol interference and attenuation are severe (long calbes, high data rates, and poor-condition cables), BAMI has an advantage of approximately 30 percent, expressed in terms of maximum usable bit rate for a given length of cable. Another conclusion reached was that impulse noise is the limiting impairment of the Griffiss AFB cable plant.

Intelligibility Performance of Narrowband Linear Predictive Vocoders in the Presence of Bit Errors

Abstract: : Diagnostic speech intelligibility tests were evaluated to assess vulnerability of two different 2400 bit-per-second linear predictive vocoder algorithms to random bit errors imposed on the data stream. Listening tests with crews of eight subjects yielded diagnostic intelligibility scores at zero, 1%, 3% and 5% bit error rates. These data were analyzed to establish linear regression models relating intelligibility performance and bit error rate. Piecewise-linear prediction coding (PLPC) was confirmed to have a small but significant advantage through being less vulnerable to bit errors than conventional linear prediction coding (LPC), an advantage that had been hypothesized from the inherent redundancy that is added by transmitting separate LPC coefficients for low-frequency and high-frequency speech bands. A small but consistent improvement in intelligibility was also found for the error-free case, believed to result from improved spectrum modeling that is a consequence of the piecewise approach. Significant differences in susceptibilities to bit errors were found among individual intelligibility scores for speakers as well as for intelligibility features. Tables for predicting average intelligibility performance, and confidence limits, were constructed from the regression models. The findings provide guidance for further research towards the goal of minimizing susceptibility of narrowband LPC vocoders to jamming and interference. They also highlight a need for further studies to obtain better understanding of causes of the typical large dispersion in intelligibility scores for individual speakers, obtained in these and many other tests.

An Optimal Frame Synchronization Technique Using an Associative Processor

Abstract: Data loss resulting from the time to regain frame synchronization following detection of an out-of-frame condition on a synchronous time-division multiplexed bus or line, such as the Bell System T1 digital line, can be substantial. Most current sequential schemes require many frame times to separate with high probability the true frame pattern from identical patterns occurring temporarily in random data. A parallel search technique and a special purpose associative processor implementation which can eliminate loss of frame synchronization due to frame pattern bit errors and reduce frame synchronization time to its minimum value by eliminating the time spent dwelling at false frame positions is presented.

A Comparison of Digital Transmission Techniques for Standard FM Mobile Radio Sets

Abstract: Digital transmission for existing standard FM mobile radio sets is discussed. The transmission properties of such standard sets are presented. Various data pre-encoding techniques and the corresponding decoders are considered and their performances compared, The comparison includes consideration of the radiated FM spectra, the measured bit error rate curves, and the necessary complexity.