Showing papers on "Block cipher published in 1986"

Is DES a pure cipher? (Results of more cycling experiments on DES)

Abstract: During summer 1985, we performed eight cycling experiments on the Data Encryption Standard (DES) to see if DES has certain algebraic weaknesses. Using special-purpose hardware, we applied the cycling ciosure test described in our Eurocrypt 85 paper to determine whether DES is a pure cipher. We also carried out a stronger version of this test, (A cipher is pure if, for any keys i,j,k, there exists some key l such that TiTj-1Tk = Tl, where Tw denotes encryption under key w.) In addition, we followed the orbit of a randomly chosen DES transformation for 236 steps, as well as the orbit of the composition of two of the "weak key" transformations. Except for the weak key experiment, our results are consistent with the hypothesis that DES acts like a set of randomly chosen permutations. In particular, our results show with overwhelming confidence that DES is not pure. The weak key experiment produced a short cycle of about 233 steps, the consequence of hitting a fixed point for each weak key.

Self-synchronizing type analog cipher synchronizing system

Abstract: PURPOSE:To secure a cipher synchronization even after communication has been suspended, by feeding back a part of an output code of a block cipher device of a transmitting device to an input code, and also transmitting it to a reception side, in a communication system for executing an encipherment by a transposition of a frequency spectrum. CONSTITUTION:A high speed Fourier converting part 19 converts an input signal to a frequency spectrum at every prescribed frame, and inputs it to a transposing part 10. A block cipher device 15 enciphers by a key K an input code which has been set in advance in an initial vector register (IVR)16, and sets an output code to an output register 17. By an output of the register 17, the transposing part 10 is controlled, and a part of the output of the register 17 is fed back to the IVR16. A part of the output of the register and an output of the transposing part 10 are transmitted through a reverse high speed Fourier transformer 12. In a reception side, a signal corresponding to a part of the output of the transmission side is extracted from a high speed Fourier transforming part 33, and supplied to an IVR36.