Booth's multiplication algorithm
About: Booth's multiplication algorithm is a research topic. Over the lifetime, 820 publications have been published within this topic receiving 9211 citations.
Papers published on a yearly basis
01 Jan 1961
TL;DR: Methods of obtaining high speed in addition, multiplication, and division in parallel binary computers are described and then compared with each other as to efficiency of operation and cost.
Abstract: Methods of obtaining high speed in addition, multiplication, and division in parallel binary computers are described and then compared with each other as to efficiency of operation and cost. The transit time of a logical unit is used as a time base in comparing the operating speeds of different methods, and the number of individual logical units required is used in the comparison of costs. The methods described are logical and mathematical, and may be used with various types of circuits. The viewpoint is primarily that of the systems designer, and examples are included wherever doing so clarifies the application of any of these methods to a computer. Specific circuit types are assumed in the examples.
TL;DR: In this article, the authors presented circuit techniques for CMOS low-power high-performance multiplier design using 0.8-/spl mu/m CMOS (in BiCMOS) technology.
Abstract: In this paper we present circuit techniques for CMOS low-power high-performance multiplier design. Novel full adder circuits were simulated and fabricated using 0.8-/spl mu/m CMOS (in BiCMOS) technology. The complementary pass-transistor logic-transmission gate (CPL-TG) full adder implementation provided an energy savings of 50% compared to the conventional CMOS full adder. CPL implementation of the Booth encoder provided 30% power savings at 15% speed improvement compared to the static CMOS implementation. Although the circuits were optimized for (16/spl times/16)-b multiplier using the Booth algorithm, a (6/spl times/6)-b implementation was used as a test vehicle in order to reduce simulation time. For the (6/spl times/6)-b case, implementation based on CPL-TG resulted in 18% power savings and 30% speed improvement over conventional CMOS.
TL;DR: This concise paper addresses the design of multipliers capable of accepting data in 2's complement notation, or both data and coefficients in 1's complement shorthand, and considers multiplier recoding techniques, such as the Booth algorithm.
Abstract: Digital filters and signal processors when realized in hardware often use serial transfer of data. Multipliers which are capable of accepting variable coefficients and data in sign and magnitude notation and producing serial products of the same length as the input data word have been known for some time. This concise paper addresses the design of multipliers capable of accepting data in 2's complement notation, or both data and coefficients in 2's complement notation. It also considers multiplier recoding techniques, such as the Booth algorithm. Specialized (fixed coefficient) multiplier designs are considered briefly. Finally, multiplier rounding and overflow characteristics are discussed, and a rough comparison is made between the complexity of the various designs.
TL;DR: The bit approximate radix-8 Booth multipliers are designed using the approximate recoding adder with and without the truncation of a number of less significant bits in the partial products.
Abstract: The Booth multiplier has been widely used for high performance signed multiplication by encoding and thereby reducing the number of partial products. A multiplier using the radix- $4$ (or modified Booth) algorithm is very efficient due to the ease of partial product generation, whereas the radix- $8$ Booth multiplier is slow due to the complexity of generating the odd multiples of the multiplicand. In this paper, this issue is alleviated by the application of approximate designs. An approximate $2$ -bit adder is deliberately designed for calculating the sum of $1\times$ and $2\times$ of a binary number. This adder requires a small area, a low power and a short critical path delay. Subsequently, the $2$ -bit adder is employed to implement the less significant section of a recoding adder for generating the triple multiplicand with no carry propagation. In the pursuit of a trade-off between accuracy and power consumption, two signed $16\times 16$ bit approximate radix-8 Booth multipliers are designed using the approximate recoding adder with and without the truncation of a number of less significant bits in the partial products. The proposed approximate multipliers are faster and more power efficient than the accurate Booth multiplier. The multiplier with 15-bit truncation achieves the best overall performance in terms of hardware and accuracy when compared to other approximate Booth multiplier designs. Finally, the approximate multipliers are applied to the design of a low-pass FIR filter and they show better performance than other approximate Booth multipliers.