scispace - formally typeset
Topic

Booth's multiplication algorithm

About: Booth's multiplication algorithm is a(n) research topic. Over the lifetime, 820 publication(s) have been published within this topic receiving 9211 citation(s).

...read more

Papers
  More


Journal ArticleDOI: 10.1109/JRPROC.1961.287779
O. L. Macsorley1Institutions (1)
01 Jan 1961-
Abstract: Methods of obtaining high speed in addition, multiplication, and division in parallel binary computers are described and then compared with each other as to efficiency of operation and cost. The transit time of a logical unit is used as a time base in comparing the operating speeds of different methods, and the number of individual logical units required is used in the comparison of costs. The methods described are logical and mathematical, and may be used with various types of circuits. The viewpoint is primarily that of the systems designer, and examples are included wherever doing so clarifies the application of any of these methods to a computer. Specific circuit types are assumed in the examples.

...read more

Topics: Logical conjunction (58%), Arithmetic logic unit (57%), Binary number (54%) ...read more

597 Citations


Journal ArticleDOI: 10.1109/4.540066
Abstract: In this paper we present circuit techniques for CMOS low-power high-performance multiplier design. Novel full adder circuits were simulated and fabricated using 0.8-/spl mu/m CMOS (in BiCMOS) technology. The complementary pass-transistor logic-transmission gate (CPL-TG) full adder implementation provided an energy savings of 50% compared to the conventional CMOS full adder. CPL implementation of the Booth encoder provided 30% power savings at 15% speed improvement compared to the static CMOS implementation. Although the circuits were optimized for (16/spl times/16)-b multiplier using the Booth algorithm, a (6/spl times/6)-b implementation was used as a test vehicle in order to reduce simulation time. For the (6/spl times/6)-b case, implementation based on CPL-TG resulted in 18% power savings and 30% speed improvement over conventional CMOS.

...read more

Topics: Adder (61%), CMOS (57%), BiCMOS (55%) ...read more

255 Citations


Journal ArticleDOI: 10.1109/TCOM.1976.1093315
Richard F. Lyon1Institutions (1)
Abstract: Digital filters and signal processors when realized in hardware often use serial transfer of data. Multipliers which are capable of accepting variable coefficients and data in sign and magnitude notation and producing serial products of the same length as the input data word have been known for some time. This concise paper addresses the design of multipliers capable of accepting data in 2's complement notation, or both data and coefficients in 2's complement notation. It also considers multiplier recoding techniques, such as the Booth algorithm. Specialized (fixed coefficient) multiplier designs are considered briefly. Finally, multiplier rounding and overflow characteristics are discussed, and a rough comparison is made between the complexity of the various designs.

...read more

Topics: Two's complement (59%), Booth's multiplication algorithm (58%), Multiplier (economics) (55%) ...read more

243 Citations


Proceedings ArticleDOI: 10.1109/ARITH.1987.6158706
18 May 1987-
Abstract: A high speed multiplier and divider for MOS LSI based on a new algorithm is presented. When we implement the multiplier and the divider in LSI, the features such as high speed operation, small number of transistors and easy layout are the most important factors. A computational algorithm using a redundant binary representation has several excellent features such as high speed addition operations. We improved the algorithm and the method of implementation, and designed an advanced multiplier and divider with the above mentioned features. We expect mat our multiplier and divider are excellent compared with multipliers using the Booth algorithm and the Wallace tree, and with divider using the SRT method, respectively.

...read more

Topics: Booth's multiplication algorithm (60%), Multiplier (economics) (59%), Wallace tree (59%) ...read more

159 Citations


Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202132
202031
201925
201848
201738
201655

Top Attributes

Show by:

Topic's top 5 most impactful authors

José Monteiro

11 papers, 95 citations

Yuan-Ho Chen

10 papers, 153 citations

Sergio Bampi

7 papers, 65 citations

Timothy D. Davis

5 papers, 38 citations

Fabrizio Lombardi

5 papers, 162 citations

Network Information
Related Topics (5)
Adder

24.9K papers, 200.7K citations

74% related
Discrete cosine transform

16.6K papers, 263.2K citations

72% related
Filter (video)

114.4K papers, 886.6K citations

72% related
Watermark

20.9K papers, 297.5K citations

71% related
Steganography

11.2K papers, 161.5K citations

71% related