Showing papers on "Breakdown voltage published in 1983"

High power MOSFET with low on-resistance and high breakdown voltage

Abstract: A high power MOSFET is disclosed in which two laterally spaced sources each supply current through respective channels in one surface of a semiconductor chip which are controlled by the same gate. The channels lead from the source electrodes to a relatively low resistivity region and from there to a relatively high resistivity epitaxially formed region which is deposited on a high conductivity substrate. The drain electrode may be either on the opposite surface of the chip or laterally displaced from and on the same side as the source regions. The epitaxially deposited semiconductor material immediately adjacent and beneath the gate and in the path from the sources to the drain has a relatively high conductivity, thereby to substantially reduce the on-resistance of the device without effecting the breakdown voltage of the device. The breakdown voltage of the device is substantially increased by forming a relatively deep p-type diffusion with a large radius in the n-type epitaxial layer beneath each of the sources.

Novel Mechanism for Tunneling and Breakdown of Thin SiO 2 Films

Abstract: L'effet tunnel resonnant via les etats de defauts est un important mecanisme pour l'injection de porteurs en champ intense dans les couches minces SiO 2 des structures MOS. Proposition d'un modele expliquant les faibles tensions disruptives observees en champ intense

Schottky diodes with high breakdown voltages

Abstract: The methods of increasing the breakdown voltages in silicon Schottky diodes is presented. In addition to a guarding ring, screen-diffusion regions were introduced. In this manner, the electrical field near the Schottky contact was lowered and, as a result, higher breakdown voltages were obtained. By using this method, the breakdown voltage can be increased by a factor of 3–5. However, a large device area is required for the same Schottky contact area and, therefore, the junction parasitic capacitance is greater.

An experimental and numerical investigation

Abstract: GaAs MESFETs wlth bth mlcron and submlcron gates were fabrlcated and evaluated. FETs wlth 1 .2~ gate show an extrlnslc transconductance of 225mS/mm at VGs=OV, cut-off frequencles around 2CGHz and a nolse flgure of 2dB at 8GHz with 9dB associated gam. Breakdown voltage is hlgher than 6V. FETs wlth 1.2~ and 0.4~ gates were smultaneously fabrlcated on the same wafer to investlgate short channel effects. The short channel devlces show a good saturation behavlour and no shlft In the threshold voltage compared to the long channel devices thus demonstratlng a pronounced allevlatlon of short channel effects. The dependence of devlce performance with micron and suhlcron gates upon doplng concentratlon is lnvestlgated by detailed computer simulatlons. Good agreement between theoretical and experimental results is obtamed.

Fully isolated lateral bipolar—MOS transistors fabricated in zone-melting-recrystallized Si films on SiO 2

Abstract: A four-terminal device that can be operated either as a lateral n-p-n bipolar transistor or as a conventional n-channel MOSFET has been fabricated in silicon-on-insulator films prepared by graphite-strip-heater zone-melting recrystallization. Common-emitter current gain close to 20 and emitter-base breakdown voltage in excess of 10 V have been obtained for bipolar operation. As a MOSFET, the device exhibits well-behaved enhancement-mode characteristics with a field-effect mobility of ∼ 600 cm2/V.s and drain breakdown voltage exceeding 15 V.

Qualitative model of breakdown in SF6 in inhomogeneous gaps

Abstract: The breakdown mechanism for an inhomogeneous field geometry in SF6 depends on the pressure and can be divided into a streamer dominated and a leader dominated region. Based on leader propagation criteria a model is given that qualitatively describes the pressure dependence of the breakdown voltage in inhomogeneous gaps as well as the influence of the pulse rise-time, polarity and gap geometry.

Microstructure, electrical properties, and failure prediction in low clamping voltage zinc oxide varistors

Abstract: Preparation and properties are described for ZnO varistors which clamp at sufficiently low voltages (≊10 V) for overvoltage protection of integrated circuits. The desired electrical characteristics have been obtained by microstructure control using alumina as a ZnO grain growth enhancer. Pulse degradation studies on these low voltage varistor compositions suggest that degradation occurs by premature failure of weak depletion layers and excessive current concentration at microstructural flaws. Capacitance–voltage measurements can be employed to detect these artifacts and predict the possibility of varistor failure during high current surges. A nondestructive scheme for varistor evaluation is outlined which utilizes the rate of change of capacitance and dissipation factor with dc bias voltage both above and below the varistor breakdown voltage.

Snap-Back: A Stable Regenerative Breakdown Mode of MOS Devices

Abstract: N-channel MOS transistors used in nMOS and in CMOS microelectronic circuits have a drain-to-source breakdown characteristic showing a negative resistance region. Activating this mode of operation leads to a drop in source-to-drain voltage and to a large drain current. Snap-back is not a four-layer (SCR, latch-up) phenomenon, but, like latch-up, can be initiated by current injection into the p-well, by avalanching junctions or by exposure to ionizing radiation. The sustaining voltage can be significantly below the drain-substrate avalanche voltage thereby limiting the maximum operating voltage. In this paper we present a qualitative model for snapback--local conductivity modulation occurring in the intrinsic base region of the parasitic bipolar transistor leading to regenerative feedback. Effects of process variations on the snap-back characteristics are presented as are triggering sensitivities to ionizing radiation.

Electrical Breakdown Characteristics and Testing of High Voltage XLPE and EPR Insulated Cables

Abstract: Threshold voltages and other basi c breakdown characteristics, spanning times from microseconds to cable life expectancy, were determined for cross-linked inked polyethyene ( XLPE) and ethylene propylene rubber (EPR) cables. These results are based upon measurements of 60Hz, high frequency, impulse, and impulse with d.c. bias voltages.

Initiation of Electrical Breakdown of Soil by Water Vaporization

Abstract: The predictions of a simple model of water vaporization in soil are determined and compared with previously published data for the time for the initiation of streamers which leads to soil breakdown under pulsed high-voltage excitation. This model is capable of predicting the relatively long initiation times which have been observed under certain experimental conditions and also provides an explanation for the strong, experimentally determined, dependence of the initiation time on electric field.

New grooved-gate MOSFET with drain separated from channel implanted region (DSC)

Abstract: A new grooved-gate MOSFET with its drain separated from channel implanted regions (DSC structure) is proposed for the purpose of obtaining higher breakdown voltages: drain sustaining voltage and highest applicable voltage placed by hot-carrier effects. Nonimplanted regions between channel implanted and source/drain regions are a unique feature of this device structure. The self-aligned nonimplanted region in the channel is obtained by using silicon dioxide and resist overhangs. These overhangs are fabricated by grooving the silicon substrate. The DSC structure helps reduce the electric field at the drain. Characteristics of experimental devices are presented and compared with those of conventional MOSFET's, from the viewpoint of overall VLSI device design. This device structure is shown to provide remarkable improvements, achieving a 3- or 4-V increase in drain sustaining voltage, as well as a 1- or 2-V increase in the highest applicable voltage as limited by hot-electron injection. In addition, the proposed device can alleviate such short-channel effects as V th lowering, and in particular, diminish narrow-channel effects. The influence of nonimplanted length on breakdown voltage is also clarified using the CADDET, two-dimensional analysis program.

Theoretical analysis of the DC avalanche breakdown in GaAs MESFET's

Abstract: The channel avalanche breakdown in GaAs MESFET's has been investigated using nonstationary electron dynamics and an ionization coefficient taken as a function of average electron energy. Stationary high-field domains of different shapes and peak-field localization are calculated at the breakdown, depending on technological parameters, device geometry or gate bias. Design rules are given to obtain maximum saturated output power and a full-channel current breakdown voltage comparable to the one near pinchoff. In particular, it is found that both a recessed channel geometry and an increased gate-drain distance should yield the best device performances with a doping level not higher than about 1.2-1017cm-3and a channel current I dss between 275 and 330 mA/mm.

Increased avalanche breakdown voltage and controlled surface electric fields using a junction termination extension (JTE) technique

Abstract: Extremely high breakdown voltages with very low leakage current have been achieved in plane and planar p-n junctions by using an ion-implemented junction extension for precise control of the depletion region charge in the junction termination. A theory is presented which shows a greatly improved control of both the peak surface and bulk electric fields in reverse biased p-n junctions. Experimental results show breakdown voltages greater than 95 percent of the ideal breakdown voltage with lower leakage currents than corresponding unimplanted devices. As an example, diodes with a normal breakdown voltage of 1050 V and a 0.5 mA leakage current become 1400 V (1450 ideal) devices with a 5 µA leakage current. Applications of the junction termination technique is feasible in MOS technology, but is more attractive in power devices where reduced surface fields are as important as the extremely high breakdown voltages. Reduced surface fields allow more flexibility in passivation techniques, two of which we have used to date. Our results also show that the implant can be activated at a variety of temperatures with a good degree of success; process flexibility being the goal of these tests.

Explosive Processes on the Cathode in a Vacuum Discharge

Abstract: Investigations concerning nanosecond processes in vacuum discharges are described The role of explosive processes at the cathode has been established Experimental results concerning breakdown voltage, discharge current temporal behavior, delay time, spark-to-arc transition time, X-ray radiation, and electrode erosion are reported The general characteristics of the fast breakdown process are discussed together with cathode explosions, emission, and erosion

A simplified model of short-channel MOSFET characteristics in the breakdown mode

Abstract: When a short-channel MOSFET is driven into the avalanche-induced breakdown region, the drain current increases rapidly and usually shows a snapback characteristic. Both the substrate current and the current collected by a nearby reverse-biased p-n junction also increases with increasing drain current in this region of operation. All of these effects are associated with minority-carrier injection from the source junction into the substrate. A model for the drain I-V characteristics is proposed. Also presented is a related model incorporating conductivity modulation that predicts linear relationships between the substrate and the collection currents and the drain current in this region of operation. Experimental results agree well with the models.

Cross linked polyethylene-insulated cable

Abstract: A cable insulated with a cross-linked polyethylene layer is described, wherein the cross-linked polyethylene is prepared by cross-linking with 2,5-dimethyl-2-5-di(tert-butylperoxy)hexane or 2,5-dimethyl-2,5-di(tert-butylperoxy)hexyne-3 as a cross-linking agent. Even if voltage is applied at high temperatures, the breakdown voltage of the cable can be maintained at a high level.

The Effect of Ionizing Radiation on the Breakdown Voltage of Power MOSFETS

Abstract: The drain-source breakdown voltage of power MOSFETs is shown to be a strong function of the total dose of ionizing radiation to which the device has been exposed. For the n-channel MOSFETS studied, the breakdown voltage after exposure is reduced from the unirradiated value. The cause for the effect is postulated to be the trapping of radiation-generated charge in the field oxide and the generation of interface traps at the field oxide-silicon interface. The devices studied varied in breakdown voltage between 60 and 500 V and used field plates and/or field rings to terminate the high voltage junction. The magnitude of the drain-source voltage applied to the device during irradiation is shown to have a strong influence on the total shift in breakdown voltage. It is also found that the method of junction termination has some influence on the total shift. These influences occur because the electric field in the oxide during irradiation depends both upon the applied drain-source voltage and the method of junction termination. Implications of the results of this work on device applications are briefly discussed.

Programmable read-only memory

Abstract: A semiconductor memory cell for a programmable read-only memory includes a polysilicon layer formed with laterally spaced surface regions which differ in impurity concentration and which form two back-to-back series diodes functioning as a programmable diode and an isolating diode. Because of the different impurity concentration, the diodes have different reverse-bias breakdown voltages. The programmable diode has the lower reverse-bias breakdown voltage. The high reverse-bias breakdown voltage of the isolating diode has the effect of blocking the parasitic current drain on the programming current.

Oxide isolation process for standard RAM/PROM and lateral PNP cell RAM

Abstract: An oxide-isolated RAM and PROM process is disclosed wherein a RAM circuit includes a lateral PNP transistor formed in the same island of silicon material as a vertical NPN device and further wherein contact is made to the base of the lateral PNP and to the collector of the vertical NPN through a buried contact region accessed through a sink region formed in an adjacent island of semiconductor material. A field implantation beneath the isolation oxide avoids implanting impurity along the sidewalls of the semiconductor material adjacent the field oxidation and therefore provides both vertical and lateral isolation from one silicon island to another. Substantial reductions in sink sizes and cell sizes are obtained by elminating the field diffusions from the sidewalls of the semiconductor islands. The lateral PNP transistor serves as an active load for a memory circuit constructed using the structure of this invention. The process also can be used to manufacutre PROMS from vertical NPN transistors. An LV CEO implant is used to increase the breakdown voltage of each vertical transistor from its collector-to-emitter thereby allowing junction avalanching of selected emitter-base junctions to program selected PROMs in the array even though the programming voltage is only a few volts beneath the breakdown voltage of the oxide isolated structure.

An Analysis of Combined Stress Degradation of Rotating Machine Insulation

Abstract: This paper presents a new method for estimating the life of rotating machine insulation under combined stresses. Since there already exist experimental formulae for each stress degradation (thermal, voltage, and mechanical), the method aims to derive a new formula for multiple stress degradation. The residual breakdown voltage should be a unified measure of degradation. In the method, the amounts of each single stress degradation are converted into that of voltage degradation, with the aid of the unified measure. The total degradation is estimated by summing up these amounts. When it attains the critical value of an insulation, the insulation loses its properties. Voltage endurance curves have been expressed as straight lines on either log-log or semi-log coordinate. Our new method of estimating the life of insulation under combined stresses is applicable to both cases. The interactive effects between stresses can be represented as the change of voltage degradation rate, and the residual breakdown voltage characteristics can be explained with no contradictions to the life characteristics.

Numerical comparison of DMOS, VMOS, and UMOS power transistors

Abstract: Two-dimensional simulation of breakdown voltage and on-resistance of DMOS, VMOS, and UMOS vertical power devices is performed. The three devices are evaluated for breakdown-voltage designs of 100, 550, and 1000 V.

MIS high-voltage element with high-resistivity gate and field-plate

Abstract: By the use of high-ohmic polycrystalline silicon(poly) in MIS elements, a depletion layer can be formed in the poly material which brings about an electric decoupling between the poly (gate) and the underlying semiconductor body. This effect can be utilized advantageously in various circuit elements, such as in CCD's, in order to obtain a favorable potential distribution in the substrate; in MOS transistors in order to reduce the parasitic capacities; and in high-voltage devices in order to increase the breakdown voltage at the edge of the field plate (resurf).

High voltage circuits in low voltage CMOS process

Abstract: A CMOS push-pull output buffer (171) is constructed utilizing a plurality of N channel transistors (74, 75, 76) and a plurality of P channel transistors (71, 72, 73) connected in series. The voltages applied to the gates of the N channel transistors and P channel transistors are selected to divide the high voltage (+V) substantially equally across the P channel transistors, when the P channel transistors are turned off, and substantially evenly divide the high voltage across the N channel transistors, when the N channel transistors are turned off. In another embodiment of this invention, selected ones of the N channel and P channel transistors are formed in order to have a high drain to bulk breakdown voltage. In another embodiment of this invention, a plurality of N channel and a plurality of P channel transistors are connected in series and driven by a single ended control voltage (CN), thus providing a first stage (101) which drives a second stage (100) having a plurality of P channel transistors and a plurality of N channel transistors (110, 111, 112), which provide the high voltage output voltage. In another embodiment of this invention, the first stage (101) is driven by a single ended control voltage (CN) and serves to drive a second stage (103) comprising a plurality of N channel transistors (110, 111, 112) and a plurality of bipolar transistors (120, 121), whereby said second stage provides the high voltage output signal.

Metal oxide varistor with controllable breakdown voltage and capacitance and method of making

Abstract: A metal oxide varistor with controllable breakdown voltage and capacitance characteristics is fabricated by controlled diffusion of lithium into conventional metal oxide varistor material at elevated temperature. The varistor layer containing lithium exhibits an increased breakdown voltage, lowered capacitance, and low leakage current while maintaining a high coefficient of nonlinearity.

Lowering of the breakdown voltage of silicon dioxide by asperities and at spherical electrodes

Abstract: The paper examines the assumption that asperites and corners in electrodes can be preferential sites for electrical breakdown of silicon dioxide capacitors. It was assumed for this purpose that asperities can be approximated by spherical surfaces, and the breakdown voltage was then calculated at such asperities. Calculations showed that the breakdown voltage of a planar silicon dioxide capacitor can be lowered by one half to two thirds by asperities, when their radius is less than about one half of the oxide thickness. Such a decrease in the breakdown voltage is widely observed in polysilicon oxide capacitors. The effect of asperities is alleviated by a trapped electron charge, which can increase the breakdown voltage significantly. The spherical asperity model accounted for the breakdown voltages observed on a wide range of polysilicon oxide capacitors with oxide thickness varying from 45 to 820 nm. The radius of asperities responsible for breakdown in these experiments was roughly estimated 25–35 nm.

InGaAs avalanche photodiodes for 1 μm wavelength region

Abstract: A low-noise, low-dark-current and high-speed InGaAs avalanche photodiode (APD) has been designed and fabricated. The diode has a planar structure and is composed of InP/InGaAsP/InGaAs/InP layers grown on (111)A oriented InP. At a multiplication of 10, the diode exhibited excess noise factor of 5 and cutoff frequency of more than 1 GHz. Dark current was 10 nA near breakdown voltage. The diode has been tested in an experimental optical receiver in the gigabit range (time slot 0.63 ns) and 1.3 μm. The receiver sensitivity of −29.2 dBm was obtained at an error rate of 10−11.

p-Channel MOSFET's in LPCVD PolySilicon

Abstract: p-channel MOSFET's have been fabricated in LPCVD polysilicon. A 5000-A n+poly acts as the gate electrode on which a 500-A thermal oxide is grown to act as the gate insulator. Then a 1500-A LPCVD polysilicon layer is deposited at 620°C and is subsequently boron doped to form the conductive channel. Devices with channel length as small as 2 µm show well-behaved transistor characteristics. The drive current and leakage current are as suitable for usage as load element in memory applications. At large gate voltages the accumulation hole mobility is 9 cm2/V.s. The drain-to-source breakdown voltage exceeds -20 V.

Voltage Breakdown in S-Band Linear Accelerator Cavities

Abstract: Voltage breakdown is one of the major limiting factors in the design of a high accelerating gradient linear accelerator structure. A multiple-use cavity test system was developed to establish the criteria for voltage breakdown in S-band pulsed electron linear accelerator cavities, in terms of cavity geometry, accelerating gradient, RF pulse shape and repetition rate, surface finish, temperature and external magnetic field. The experimental set-up and test procedure, as well as the experimental results, are presented.

Plasma jet ignition system

Abstract: An ignition system for an internal combustion engine having a capacitive plasma jet plug including a capacitor in parallel with the series combination of an auxiliary gap and a plasma cavity. The auxiliary gap increases the required breakdown voltage before the plasma cavity generates a spark and obtains supplemental energy from the energy stored in the capacitor.