Showing papers on "Breakdown voltage published in 1986"

Thermal cautery system

Abstract: A thermal cautery system having an endoscopically deliverable probe connected to a power supply and display unit. The power supply and display unit, when triggered by a footswitch, energizes a voltage regulator having a current limited output that supplies power to the probe. The current limiting function of the voltage regulator is disabled for a predetermined period that power is initially applied to said probe to minimize the heating time of said probe. The current through said probe is sensed and used to increase the voltage at the output of the voltage regulator as the current increases to compensate for the voltage drop in the conductors connecting the probe to the power supply. A manually selected portion of the sensed current through the probe is also integrated and used to terminate the flow of current through the probe when the integral of the current with respect to time has reached a predetermined value. A tone generator provides an audible indication when power is being applied to the probe and for a predetermined period thereafter to allow the probe to cool before the absence of the tone signals the removal of the probe from tissue being coagulated. The probe is heated by current flowing through an internal diode having a predetermined breakdown voltage at a predetermined temperature. The temperature of the probe is self-regulated by applying a voltage to the probe that is substantially equal to said predetermined voltage so that the current through the probe is reduced at said predetermined temperature.

A fractal model of dielectric breakdown and prebreakdown in solid dielectrics

Abstract: We introduce and discuss a fractal model for dielectric breakdown which exhibits a breakdown voltage and a region of stable prebreakdown structures. The model provides a unifying picture covering homogeneous space charge injection, treelike structures, and filamentary breakdown. A simple qualitative relation between the global form of the pattern and two simple physical parameters is found. The model illustrates the intricate relationship between local stochastic and global deterministic aspects of dielectric instablilities.

Hole trapping and breakdown in thin SiO 2

Abstract: The field dependence of the hole generation rate, also known as the impact ionization coefficient α, in thin SiO 2 ( \alpha = \alpha_{0}e^{-H/E} where H = 78 MV/cm for electric fields ranging from 7 to 14 MV/cm, which covers the field range from the onset of significant Fowler-Nordheim current to instant breakdown. The similar field dependences of α and charge-to-breakdown supports the model that hole generation and trapping leads to oxide wearout. Because of the fact that positive charge generation is observed for oxide voltage well below the SiO 2 bandgap, we propose that the generated holes arise from transition between band tails in the amorphous SiO 2 . It is also observed that α decreases rapidly when the applied oxide voltage is very low; thus α is a function of both oxide field and voltage in general. This suggests that ultra-thin oxide with low operating voltages might be a good candidate for high endurance E2PROM devices at very low oxide field.

Junction termination extension for near-ideal breakdown voltage in p-n junctions

Abstract: Extremely high breakdown voltages with very low leakage current have been achieved in plane and planar p-n junctions by using an ion-implanted junction extension for precise control of the depletion region charge in the junction termination. A theory is presented that shows a greatly improved control of both the peak surface and bulk electric fields in reverse biased p-n junctions. Experimental results show breakdown voltages greater than 95 percent of the ideal breakdown voltage with lower leakage currents than corresponding unimplanted devices. As an example, plane-junction moat-etch-terminated diodes with a normal breakdown voltage of 1050 V and a 0.5-mA leakage current become 1400 V (1450 ideal) devices with a 5-µA leakage current. Planar junctions, which broke down at 300 V, blocked as much as 1400 V if JTE terminated. Since planar junctions are of the greatest interest, we incorporated multiple field ring, field plate, and JTE terminations on a mask set and fabricated and tested thousands of devices. The results clearly showed that the ideal breakdown voltage can be achieved with less than 200 µm with JTE, where the same area would lead to 30 to 45 percent of the ideal with field rings and up to 40 to 50 percent of the ideal when used with field rings combined with field plates. Eight rings, even combined with a field plate, yielded less than 80 percent of the ideal breakdown voltage and required about 400 µm of device periphery.

Method of fabricating a MOSFET with graded source and drain regions

Abstract: A method of forming metal oxide semiconductor field-effect transistors (MOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effect, to increase punch through voltage and to increase gate-aided breakdown voltage.

High breakdown voltage semiconductor device

Abstract: A precisely formed region of semiconductor material which correspondingly contains a precisely controlled amount of charge when depleted is provided in the proximity of a p-n junction in several kinds of semiconductor devices. This region is located within the selected semiconductor device in such a manner as to increase avalanche breakdown voltage of a p-n junction to near its ideal value and to reduce both peak bulk and peak surface electric fields.

High voltage depletion mode MOS power field effect transistor

Abstract: A vertical depletion mode power field effect transistor having a greatly increased drain-to-source breakdown voltage. The drain region is formed in the substrate and separated from the channel by a first insulative layer having apertures which allow the passage of electrical currents. The channel, which is formed between the first insulative layer and a second insulative layer parallel to the substrate surface, contains both a source region, formed by implantation of impurities of the same type as are used to form the drain region, and a gate region. In this configuration, the normally high voltage which exists between the gate and drain is imposed over a greater distance than in conventional depletion mode vertical FETs, so that this new configuration produces vertical power FETs having much higher breakdown voltages than do conventional depletion mode vertical FETs. Islands having a conductivity type opposite to that used to form the source region are formed immediately below the second insulative layer and serve to prevent the creation of a charge inversion layer in the channel, where the inversion layer adversely affects the turn off characteristic of the j-MOS power transistor.

Field effect semiconductor device having improved voltage breakdown characteristics

Abstract: A semiconductor device including a field effect transistor of the D-MOS type which is composed of substructures and in which further surface zones are provided in the intermediate spaced between the regularly arranged substructures in order to improve the field distribution in the semiconductor body, as a result of which the breakdown voltage of the transistor is increased. The further surface zones can be provided without additional processing steps being required and need not be contacted at the main surface.

A high-current drivability i-AlGaAs/n-GaAs doped-channel MIS-Like FET (DMT)

Abstract: A high-current drivability doped-channel MIS-like FET (DMT) has been proposed. The DMT takes advantage of high saturation current with large transconductance and high breakdown voltage, in regard to its operating principle. The fabricated 0.5-µm gate DMT showed 310-mS/mm (410-mS/mm) transconductance and 650-mA/mm (800-mA/mm) maximum saturation current at room temperature (at 77 K). Output current values are about three or four times those for conventional two-dimensional electron gas (2DEG) FET's. Estimated average electron velocity is rather high, 1.5 × 107cm/s (2 × 107cm/s) at room temperature (77 K). In addition, f_{\max} is as high as 41 GHz. f T is 45 GHz, which is the best data ever reported in 0.5-µm gate FET's.

Dc power cable

Abstract: PURPOSE:To increase the DC breakdown voltage by providing space charge mitigating layers at least between an inside semiconductive layer and an insulator or between an outside semiconductive layer and the insulator. CONSTITUTION:Space charge mitigating layers 4-7 preventing the accumulation of space charges are provided at least between an inside semiconductive layer 1 located around a conductor N and an insulator 2 or between an outside semiconductive layer 3 and the insulator 2. The space charge mitigating layer 4 is provided between the inside semiconductive layer 1 and the insulator 2, and the space charge mitigating layer 5 is provided between the outside semiconductive layer 3 and the insulator 2, and space charge mitigating layers 6, 7 are provided both between the inside semiconductive layer 1 and the insulator 2 and between the outside semiconductive layer 3 and the insulator 2. The accumulation of space charges giving an adverse effect to the insulator 2 is thereby reduced, and a DC power cable with the high dielectric strength is obtained.

DC Flashover Voltage Characeteristics and Their Calculation Method for Oil-Immersed Insulation Systems in HVDC Transformers

Abstract: The effects of the laminated paper layer direction on the conductivity and the dc breakdown strength in oil-impregnated paper were experimentally clarified. It was confirmed that not only oil and paper discharges through the laminated paper layers, but also paper discharges along them triggered total flashover in oil and oil-impregnated paper composite insulation. Analyses verified the usefulness of the dc flashover voltage calculation method, based on a non-linear directional field calculations and the lowest flashover voltage estimations between paper discharges along the laminated paper layers and oil and paper discharges through them.

A new low-noise AlGaAs/GaAs 2DEG FET with a surface undoped layer

Abstract: A high-performance N-AlGaAs/GaAs selectively doped two-dimensional electron gas (2DEG) FET with a surface undoped layer has been designed and demonstrated. Simple analysis based on the short-channel approximation revealed that an increase in a total layer thickness between a gate electrode and 2DEG at a hetero-interface results in a higher cutoff frequency and a lower noise figure than conventional 2DEG FET's. This is because the gate capacitance can be markedly reduced without a significant decrease in the transconductance owing to a parasitic source resistance. The surface undoped layer intentionally employed in this work can permit the total layer thickness to increase, i.e., the gate capacitance to reduce, without changes in the 2DEG density and in the source resistance. This structure also gives high gate breakdown voltage because of a small neutral region in n- (AlGa)As and a low surface electron field, which possibly yields excellent performance 2DEG FET's for practical use. Fabricated (AlGa)As/ GaAs 2DEG FET's exhibited noticeable room-temperature performances of 0.95-dB noise figure with 10.3-dB associated gain at 12- and 45-GHz cutoff frequency. These are the best data ever reported for 0.5-µm gate length FET's.

Microwave power double-heterojunction HEMT's

Abstract: The RF and dc characteristics of microwave power double-heterojunction HEMt's (DH-HEMT's) with low doping density have been studied. Small-signal RF measurements indicated that the cutoff frequency and the maximum frequency of oscillation in DH-HEMT's with 0.8-1 µm gate length and 1.2 mm gate periphery are typically 11- 16 GHz and 36-41 GHz, respectively. However, the cutoff frequency in DH-HEMT's degrades strongly with increasing drain bias voltage. This may be caused by both effects of increasing effective transit length of electrons and decreasing average electron velocity, due to Gunn domain formation. In large-signal microwave measurement, the DH-HEMT (2.4 mm gate periphery) delivered a maximum output power of 1.05 W with 2.8 dB gain and 0.58 W with 1.6 dB gain at 20 and 30 GHz, respectively. These are the highest output powers yet reported for HEMT devices. For the dc characteristics, the onset of two-terminal gate breakdown voltage is found to correlate with the drain current I dss and recessed length, and three-terminal source-drain breakdown characteristics near pinchoff are limited by the gate-drain breakdown. A simple model on gate breakdown voltage in HEMT is also presented.

Temperature dependence of charge generation and breakdown in SiO 2

Abstract: Experimental results are presented to show that, for temperatures ranging from 27°C to 110°C, the generation of the positive charges during a constant current stress decreases with increasing temperature whereas the generation of the interface states increases with increasing temperature. Since the oxide breakdown and the interface state have the same temperature dependence, it appears that the oxide breakdown is related to the generation of the interface states.

Silicon nitride films grown on silicon below 300 °C in low power nitrogen plasma

Abstract: Device quality silicon nitride films ranging in thickness down to 30 A were successfully grown on silicon at temperatures below 300 °C in a radio frequency (rf) nitrogen plasma. The growth rate was controlled in the range 5–100 A/h by changing nitrogen pressure, rf power, and growth temperature. Electron microscopy and Auger spectroscopy showed that the films were amorphous, microcrack‐free, close to stoichiometry Si3N4, and formed a sharp interface with the Si substrate. The breakdown voltage of Al‐Si3N4‐Si capacitors was about (1.3±0.2)×107 V/cm and the typical density of the leakage current was below 3×10−7 A/cm2 at 5 V bias for films 70 A thick.

High-voltage CMOS SIMOX technology and its application to a BSH-LSI

Abstract: This paper describes high-voltage CMOS separation by implanted oxygen (SIMOX) technology and its application to a BSH-LSI that provides the basic functions of battery feed, supervision, and hybrid for subscriber line interface cuircuits. This technology is characterized by the existence of an electric-field-shielding (EFS) layer formed between the buried SiO 2 and the surface Si layer by oxygen implantation. The density of localized states at the Fermi level of the EFS layer has been estimated to be about 1 × 1019cm-3. eV-1using the Cohen-Fritzsche-Ovshinsky model. The EFS layer reduces substrate voltage dependence of the threshold voltage and increases the drain-to-source breakdown voltage for MOSFET's. Specifically, the drain-to-source breakdown voltage has been raised to 180 V. The BSH-LSI, which is composed of high-voltage CMOS of more than 60 V and low-voltage CMOS of 15 V, has been successfully fabricated containing resistors and capacitors. Compared with a conventional bipolar BSH-LSI, the chip size and the dissipation power of the LSI have been reduced to approximately one-third and one-half, respectively.

High-voltage multiple-resistivity drift-region LDMOS

Abstract: A new multiple-resistivity drift-region structure which leads to an improvement of the on-resistance of high voltage LDMOS devices is proposed. The distinctive feature of the novel structure is the low sensitivity of breakdown voltage to process variations. The important parameters of the structure such as on-resistance, threshold voltage and punchthrough voltage in the channel are discussed, and related to breakdown voltage. Experimental structures are fabricated and characterized to illustrate the advantages of the structure.

MOSFET drain breakdown voltage

Abstract: The grounded-gate or gate-assisted drain breakdown voltage of n-channel MOSFET's has been characterized for wide ranges of oxide thickness and substrate doping concentration. Two distinct regimes, one being channel-doping limited and the other being oxide-thickness limited, have been identified. We propose that these two regimes reflect two possible locations of breakdown-at the n+-p junction and in the deep-depletion layer in the n+ drain. They can be separated by their different breakdown voltage dependences on V g and require different approaches to process improvement.

Power down sense circuit

Abstract: A low voltage sense circuit for a microprocessor controlled television receiver includes a 5 volt regulator having a large electrolytic capacitor coupled across its output, which is the power input terminal of a microprocessor. The microprocessor includes a sleep terminal for initiating operation in a minimum power consumption mode. The 12 volt input to the 5 volt regulator is coupled to the bias circuit of a PNP transistor that includes a Zener diode and which is in saturation as long as the input voltage to the 5 volt regulator is greater than the breakdown voltage of the Zener diode. The collector output of the transistor is connected to the sleep terminal of the microprocessor. When the transistor is driven out of saturation, an appropriate voltage change is developed at the sleep terminal for causing the microprocessor to switch to its low power sleep mode.

The Effects of Frequency and Temperature on Water Tree Degradation of Miniature XLPE Cables

Abstract: This paper presents results of water treeing aging tests on miniature crosslinked polyethylene cables. To produce the water trees, the cables were immersed in water and subjected to HV at frequencies of 600, 400, and 1000 Hz. The times to breakdown and ac ramp breakdown voltages after preset times of aging were measured. The effect of temperature cycling was also examined. The ac ramp voltage was found to be a good indicator of the severity of water tree degradation at room temperature as the time to breakdown distributions correlated well with a reduction in the ac ramp breakdown voltage. Temperature cycling of the cables increased the number and the lengths of bow-tie trees compared to room temperature aged cables but decreased the number of vented trees. Correlation between ramp breakdown voltages and times to breakdown was poor for temperature-cycled cables. Microscopic examinations of some of the breakdown channels and possible causes of the different mechanisms of breakdown as the final stage of aging are discussed.

Regulator circuit for converting alternating input to a constant direct output

Abstract: A high efficiency integrated power converter adapted for direct connection to line voltage and having on chip protection from overcurrent may be implemented utilizing a GTO-SCR as the switch element in a switching power converter such that the converter requires no external transformer or inductor based voltage reducing circuitry. The input voltage may vary over a wide dynamic range without deterioration in circuit performance due to the extremely high anode to cathode breakdown voltage of the switching element and further due to the on chip protection from excess current flow through the switching element.

An accurate DC model for high-voltage lateral DMOS transistors suited for CACD

Abstract: Double-diffused lateral MOS transistors with a drain-source breakdown voltage larger than 280 V have been integrated in an epitaxial junction isolated IC process. For these devices a four-component dc model suited for computer-aided circuit design (CACD) is developed based upon 2-D device simulation. The nonhomogeneously doped backgate is well described by two cascoded MOS transistors with different threshold voltages and gain factors. In the drift region the nonlinear dependence of the electron drift velocity on the applied electrical field is taken into account, and modulation of the on-resistance caused by a varying substrate voltage is incorporated properly. In order to model the characteristics in the entire range of operation, 10 parameters have to be optimized. The method for the parameter extraction is discussed, and a comparison between measured I-V characteristics and calculated values according to the model is given.

Semiconductor device having a protection circuit with lateral bipolar transistor

Abstract: A protection circuit for inner elements such as metal insulator semiconductor (MIS) field effect transistors in a semiconductor device of high packing density has been improved. The protection circuit comprises protective elements of two types. One type has a deep diffusion region providing the element with high surge capacity, that is an ability to withstand the energy of an incoming surge, and the other type has a shallow diffusion region providing a low breakdown voltage. With a combination of these two types of protective element, the protection circuit can withstand high energy of an input surge and, at the same time, provide a low protection voltage suitable to protect the inner elements from breakdown.

Comparison of measured and calculated SF6 breakdown in rf electric fields

Abstract: Measured breakdown characteristics of SF6 at 4–14 MHz are compared with the breakdown predicted with an electron‐balance model. This balance includes terms for the formation of electrons from ionization of neutral molecules and electron losses by attachment to neutral molecules, electric‐field‐driven fluxes, and diffusion. With model parameters obtained from existing literature on electron properties in dc electric fields, the model predicts radio frequency (rf) breakdown voltages in agreement with the experimental values. The electron balance model is also expressed in a nondimensional form to aid in generalizing rf breakdown to other gases. The electron concentration profiles formed when including the electric‐field‐driven fluxes are compared with the sinusoidal distribution achieved for diffusion‐controlled breakdown. The success of this model suggests that glow discharges can be modeled in a similar fashion.

Second breakdown prediction by two-dimensonal numerical analysis of BJT turnoff

Abstract: An isothermal two-dimensional numerical calculation of the potential and current distribution in an n+-p-n-n+bipolar power transistor driving an inductive load during its turnoff transient has been carried out. The transistor is initially considered to be in a heavily saturated ON-state and is then turned off by extracting a nearly constant base current. The simulation shows that during the turnoff transient, current constriction to the center of the emitter together with the increasing collector-emitter voltage produce a high electric field near the collector n-n+junction which can initiate avalanche injection. It has been found that the collector-current density is not uniform vertically (from collector to emitter) due to the current spreadout in the collector n-region. Previous one-dimensional analytical analyses of second breakdown did not consider this important effect. Thus, for an accurate prediction of reverse second breakdown voltage, the two-dimensional current flow should be considered.

High voltage lateral MOS structure with depleted top gate region

Abstract: The present invention provides an improved lateral drift region for both bipolar and MOS devices where improved breakdown voltage and low ON resistance are desired. A top gate of the same conductivity type as the device region with which it is associated is provided along the surface of the substrate and overlying the lateral drift region. In an MOS device, the extremity of the lateral drift region curves up to the substrate surface beyond the extremity of the top gate to thereby provide contact between the JFET channel and the MOS channel.

SOLID-II: High-voltage high-gain kilo-Ångstrom-channel-length CMOSFET's using Silicide with self-aligned ultrashallow (3S) junction

Abstract: A simple novel pile-up phenomenon which leads to an available layered structure of silicide with self-aligned ultrashallow (3S) junction is described. Heavily piled-up impurity (P or B) layers less than 50 nm deep under refractory metal (Ti, W, or Pd) silicide accomplish excellent p-n junction characteristics. Good ohmic properties are also obtained with contact resistivity less than 4 × 10-6ω cm2independent of substrate concentration. This notable profile can easily be realized when a high dose (≥ 5 × 1015cm-2) of impurity is implanted not through but into the refractory metal without intermixing, and followed by Silicidation. An application of this new phenomenon for a kilo-Angstrom-channel-length CMOSFET is also proposed and evaluated using two-dimensional numerical simulation. In the advanced device, silicide on lightly doped drain II (SOLID-II), the breakdown voltage and current gain product of kilo-Angstrom-channel-length MOSFET's with 3S junction can be significantly improved in comparison with those of conventional LDD devices. In the 0.3-µm-channel-length devices, current gain reduction in SOLID-II is less than 10 percent compared with that in the standard device. However, in the LDD more than a 20-percent reduction is unavoidable with the same breakdown voltage of 8.5 V. It is proved that the SOLID-II: structures can be used very effectively as a 0.2-0.5-µm-channel-length CMOSFET operatable with 5-V power supply.

Discharge Characteristics of Gaseous Dielectrics

Abstract: This chapter reviews studies of discharge characteristics and insulating properties of SF6 gas conducted in Japan, stressing works of the recent five to ten years. It deals with the following items. (a) computer simulation of basic processes of discharge in SF6, (b) discharge characteristics in non-uniform fields, (c) breakdown characteristics in nearly uniform fields: breakdown criterion and breakdown voltage, (d) electrode effect, (e) breakdown voltage-time characteristics, (f) characteristics of spacers: surface flashover and internal breakdown (puncture), (g) effect of conducting particles: gas gaps, surface flashover, and preventive measures, (h) electrode coating, and (i) characteristics for dc.